Substrate and preparation method thereof, graphics processor board, and electronic equipment

Abstract

The embodiments of the present application provide a substrate and a method for preparing the same, a graphics processor board, and an electronic device, which relate to the field of semiconductor technology and are intended to improve the integrity and reliability of signal transmission. The substrate includes a trace arranged within the substrate, the trace including a first conductive structure and a second conductive structure, the second conductive structure being connected to the surface of the first conductive structure, and the second conductive structure covering at least a portion of the surface of the first conductive structure. Along a first direction from the first conductive structure to the second conductive structure, the second conductive structure includes alternating barrier layers and conductive layers, the resistivity of the conductive layer being less than the resistivity of the barrier layer. The above-mentioned substrate can be used for chip packaging to achieve interconnected signal transmission.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate and a preparation method thereof, a graphics processor board, and an electronic device. Background Art

[0002] During high-frequency signal transmission, the current distribution within a trace is uneven, concentrating on the trace's "skin." This means the current is concentrated on the surface of the trace. The closer to the surface, the greater the current density. The actual current inside the trace is smaller, increasing the trace's resistance and power loss. This phenomenon is known as the skin effect. Furthermore, as the signal frequency increases, the skin effect becomes more severe, leading to increased conductor loss in the trace and, consequently, signal attenuation. Summary of the Invention

[0003] The embodiments of the present application provide a substrate and a preparation method thereof, a graphics processor board, and an electronic device, aiming to improve the integrity and reliability of signal transmission.

[0004] In one aspect, embodiments of the present application provide a substrate comprising a trace disposed within the substrate, the trace comprising a first conductive structure and a second conductive structure, the second conductive structure being connected to a surface of the first conductive structure and covering at least a portion of the surface of the first conductive structure. The second conductive structure comprises alternating barrier layers and conductive layers along a first direction from the first conductive structure toward the second conductive structure, wherein the resistivity of the conductive layers is less than that of the barrier layers.

[0005] In the above-mentioned embodiment of the present application, an alternating structure of a blocking layer and a conductive layer is set on the surface of the routing, and the resistivity of the conductive layer is less than the resistivity of the blocking layer. Compared with setting only a blocking layer on the surface of the routing, this structure can reduce the resistance of the routing surface.

[0006] Due to the skin effect during high-speed signal transmission, current concentrates on the surface of the trace. By reducing the surface resistance of the trace, signal attenuation caused by conductor loss can be minimized, thereby improving signal transmission integrity. Furthermore, the barrier layer prevents atoms from the first conductive structure and the conductive layer from diffusing into the substrate dielectric, preventing short circuits between adjacent traces and increasing the reliability of the system design.

[0007] In some embodiments, along a second direction perpendicular to the plane of the substrate, the first conductive structure includes a first surface and a second surface opposite to each other, and the trace includes two second conductive structures, one second conductive structure covering the first surface and the other second conductive structure covering the second surface.

[0008] In some embodiments, a plurality of barrier layers and a plurality of conductive layers of the second conductive structure alternately surround the surface of the first conductive structure.

[0009] In some embodiments, along the first direction, a thickness of the first conductive structure is greater than a thickness of the second conductive structure.

[0010] In some embodiments, along the first direction, the thickness of the conductive layer is greater than the thickness of the blocking layer, which can increase the proportion of the film layer thickness with lower resistivity in the surface layer of the routing, further reduce the resistance and conductor loss of the routing surface, and improve the signal attenuation caused by the skin effect, so as to enhance the integrity of signal transmission.

[0011] In some embodiments, the ratio of the thickness of the conductive layer to the thickness of the barrier layer is in a range of 4-8.

[0012] In some embodiments, along the first direction, the second conductive structure includes a plurality of barrier layers and a plurality of conductive layers alternately arranged. The plurality of conductive layers includes a first conductive layer proximal to the first conductive structure and a second conductive layer distal to the first conductive structure, wherein the second conductive layer is closer to the surface of the trace than the first conductive layer.

[0013] By setting the thickness of the second conductive layer to be greater than that of the first conductive layer, and making the resistance of the second conductive layer less than that of the first conductive layer, the conductor loss in the second conductive layer can be reduced in a targeted manner, thereby reducing the conductor loss in the surface layer as a whole, improving the signal attenuation caused by the skin effect, and improving the integrity of signal transmission.

[0014] In some embodiments, along the first direction, the thicknesses of multiple conductive layers increase successively, and the resistance of the conductive layer closer to the trace surface is smaller, which can specifically reduce the conductor loss in each conductive layer, thereby reducing the conductor loss of the surface layer as a whole, improving the signal attenuation phenomenon caused by the skin effect, and improving the integrity of signal transmission.

[0015] In some embodiments, along the first direction, the second conductive structure includes a plurality of barrier layers and a plurality of conductive layers alternately arranged. The plurality of barrier layers includes a first barrier layer proximal to the first conductive structure and a second barrier layer distal to the first conductive structure, wherein the second barrier layer is closer to the surface of the trace than the first barrier layer.

[0016] It can be understood that by setting the thickness of the second blocking layer to be smaller than that of the first blocking layer, the thickness ratio of the blocking layer near the surface can be reduced, and the thickness ratio of the conductive layer near the surface can be increased, thereby reducing the resistance near the surface, thereby reducing the conductor loss of the surface layer as a whole, improving the signal attenuation phenomenon caused by the skin effect, and improving the integrity of signal transmission.

[0017] In some embodiments, along the first direction, the thickness of the multiple blocking layers decreases successively, and the thickness of the blocking layer closer to the trace surface is smaller, which can specifically reduce the resistance near the surface, thereby reducing the conductor loss of the surface as a whole, improving the signal attenuation caused by the skin effect, and improving the integrity of the signal transmission.

[0018] In some embodiments, along the first direction, the second conductive structure includes multiple barrier layers and multiple conductive layers arranged alternately. Along the length of the trace, the barrier layer includes multiple portions spaced apart, which can reduce the proportion of high-resistivity material on the trace surface. This saves material for the barrier layer and reduces the resistance of the trace surface, thereby reducing signal attenuation caused by conductor loss and improving signal transmission integrity.

[0019] Along the first direction, of the two adjacent blocking layers, one blocking layer corresponds to the spacing area of ​​the other blocking layer, that is, the two adjacent blocking layers are staggered, one blocking layer can cover the spacing area of ​​the adjacent blocking layers, and the two adjacent blocking layers can form a full-surface barrier for the conductive layer. While reducing the resistance of the surface layer of the routing, it also prevents the atoms in the first conductive structure and the conductive layer from diffusing into the medium, avoids short circuits between adjacent routings, and increases the reliability of the system design.

[0020] In some embodiments, two adjacent conductive layers are connected through the spacing area of ​​the barrier layer, thereby achieving parallel connection between adjacent conductive layers, increasing the cross-sectional area of ​​the conductive part in the wiring surface layer, thereby reducing the resistance of the wiring surface layer, reducing the signal attenuation caused by conductor loss, and improving the integrity of signal transmission.

[0021] In some embodiments, in the second conductive structure, the film layer farthest from the first conductive structure is a barrier layer.

[0022] In some embodiments, along the first direction, the thickness of the first conductive structure is 17.5 μm. In the second conductive structure, six barrier layers and five conductive layers are alternately arranged, the thickness of the barrier layer is 25 nm, and the thickness of the conductive layer is 150 nm.

[0023] In some embodiments, the material of the first conductive structure includes copper, the material of the barrier layer includes cobalt, and the material of the conductive layer includes copper.

[0024] In some embodiments, the substrate further comprises a laminated core board and a prepreg, wherein the traces are arranged between the core board and the prepreg. Along the first direction, the thickness of the core board is 3 mils, and the thickness of the prepreg is 4 mils.

[0025] In another aspect, embodiments of the present application provide a method for preparing a substrate, the method comprising: forming a trace within the substrate, the trace comprising a first conductive structure and a second conductive structure, the second conductive structure being connected to a surface of the first conductive structure and covering at least a portion of the surface of the first conductive structure. The second conductive structure comprises alternating barrier layers and conductive layers along a first direction from the first conductive structure to the second conductive structure, the resistivity of the conductive layers being less than the resistivity of the barrier layers.

[0026] In the above-described embodiment of the present application, barrier layers and conductive layers are alternately formed on the surface of the traces. The resistivity of the conductive layers is lower than that of the barrier layers. Compared to providing barrier layers only on the surface of the traces, this structure can reduce the resistance of the trace surface, mitigate signal attenuation caused by conductor loss, and improve signal transmission integrity. Furthermore, the barrier layers can prevent atoms in the first conductive structure and the conductive layers from diffusing into the substrate medium, preventing short circuits between adjacent traces and increasing the reliability of the system design.

[0027] In some embodiments, forming a trace includes: alternately forming a plurality of stacked barrier layers and a plurality of conductive layers on the substrate along a second direction perpendicular to the plane of the substrate to obtain a second conductive structure; forming a first conductive structure on a side of the second conductive structure away from the substrate; and alternately forming a plurality of stacked barrier layers and a plurality of conductive layers on a side of the first conductive structure away from the substrate along the second direction to obtain a second conductive structure.

[0028] In some embodiments, forming a trace includes: forming a groove on the surface of a substrate; alternately forming a plurality of stacked barrier layers and a plurality of conductive layers on the surface of the groove to obtain a first alternating structure; forming a first conductive structure in the groove, the first conductive structure being located on the inner side of the first alternating structure; and alternately forming a plurality of stacked barrier layers and a plurality of conductive layers on the first conductive structure along a second direction perpendicular to the plane of the substrate to obtain a second alternating structure, the second alternating structure and the first alternating structure together forming a second conductive structure.

[0029] In another aspect, embodiments of the present application provide a graphics processor board, comprising a baseboard according to any of the aforementioned embodiments, an open acceleration module, and a graphics processor chip. Multiple open acceleration modules are disposed on the baseboard and electrically connected to wiring on the baseboard. A graphics processor chip is disposed on a side of an open acceleration module away from the baseboard, and the graphics processor chip is electrically connected to the open acceleration module.

[0030] In some embodiments, the plurality of open acceleration modules comprises a plurality of rows and columns arranged in an array, with each row arranged along a third direction parallel to the plane of the substrate, and each column arranged along a fourth direction parallel to the plane of the substrate, with the third direction intersecting the fourth direction. The plurality of rows of open acceleration modules comprises rows 1 through n, where n ≥ 2; and the plurality of columns of open acceleration modules comprises columns 1 through m, where m ≥ 2.

[0031] The routing of the substrate includes at least a first routing, and the first routing includes a first section, a second section, and a third section connected in sequence. The first section extends along the fourth direction and is located on a side of the open acceleration module in the first column away from the open acceleration module in the mth column. The first section is electrically connected to the open acceleration module in the first row and the first column; the second section extends along the third direction and is located between the open acceleration module in the i-th row and the open acceleration module in the i+1-th row, 1≤i≤n-1; the third section extends along the fourth direction and is located on a side of the open acceleration module in the m-th column away from the open acceleration module in the first column. The third section is electrically connected to the open acceleration module in the n-th row and the m-th column.

[0032] On the other hand, an embodiment of the present application further provides an electronic device, which includes a mainboard and the graphics processor board in the above embodiment, wherein the graphics processor board is electrically connected to the mainboard.

[0033] The above-mentioned graphics processor board and electronic device have the same structure and beneficial technical effects as the substrate provided in some of the above-mentioned embodiments, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below should be considered schematic diagrams and do not represent the actual dimensions of the products or the actual processes of the methods involved in the embodiments of this application.

[0035] Figure 1 A schematic structural diagram of a substrate provided in an embodiment of the present application;

[0036] Figure 2 for Figure 1 A local enlarged view of the substrate at position M;

[0037] Figure 3 for Figure 2 The cross-sectional view of the alignment along the section line AA';

[0038] Figure 4 A partial enlarged view of another substrate at position M provided in an embodiment of the present application;

[0039] Figure 5 Insertion loss simulation curve diagram of the routing provided in the embodiment of the present application;

[0040] Figure 6 A detailed structural diagram of a substrate provided in an embodiment of the present application;

[0041] Figure 7A to Figure 7C A diagram of the steps for preparing a substrate provided in an embodiment of the present application;

[0042] Figure 8 A design flow chart for routing provided in an embodiment of the present application;

[0043] Figure 9 A cross-sectional schematic diagram of wiring in another substrate provided in an embodiment of the present application;

[0044] Figure 10A to Figure 10D A diagram of the steps for preparing another substrate provided in an embodiment of the present application;

[0045] Figure 11 A partial enlarged view of a wiring in another substrate provided in an embodiment of the present application;

[0046] Figure 12 A planar structural diagram of a graphics processor board provided in an embodiment of the present application;

[0047] Figure 13 for Figure 12 A partial cross-sectional view of the graphics processor board along section line BB';

[0048] Figure 14 This is a structural block diagram of the electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicably coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0056] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] For high-speed data center networks, next-generation serial interfaces require data rates exceeding 100 Gbps. This requirement pushes the Nyquist frequency to 28 GHz, ultimately creating new bandwidth requirements and link configuration requirements. Four-level pulse amplitude modulation (PAM-4) has been adopted in the 56 Gbps long-haul standard because it shares the same 28 Gbps symbol rate as non-return-to-zero line code (NRZ) modulation while offering twice the data rate. This makes PAM-4 a suitable technology for next-generation 112 Gbps applications. However, PAM-4 technology is more sensitive to noise and often exhibits lower signal-to-noise ratio (SNR) performance. Insertion loss is a key parameter for improving SNR and signal integrity; lower insertion loss helps achieve a wider eye opening at 112 Gbps.

[0059] In high-frequency signals, conductor loss of the trace is the main reason. Conductor loss is determined by the series resistance of the signal path and the return path. In the signal path and return path, the series resistance of the signal is related to the volume resistivity of the trace and the cross-section through which the current propagates. When the signal is DC, the current is evenly distributed in the trace, and the resistance of the trace is: , where R represents the resistance of the trace, ρ represents the bulk resistivity of the trace, Len represents the length of the trace, w represents the width of the trace, and t represents the thickness of the trace.

[0060] When there is alternating current or alternating electromagnetic field in the wiring, the current distribution inside the conductor is uneven. The current is concentrated in the "skin" part of the conductor, that is, the current is concentrated in the thin layer on the surface of the conductor. The closer to the surface of the conductor, the greater the current density. The current inside the conductor is actually smaller, resulting in an increase in the resistance of the conductor and its power loss. This phenomenon is called the skin effect.

[0061] At high frequencies, the thickness of the cross section through which current flows in a copper trace is approximately equal to the skin depth, i.e. , where δ represents the skin depth and f represents the sine wave frequency. Therefore, the higher the signal frequency, the smaller the skin depth, and the more the signal current tends to flow on the surface of the conductor. Due to the existence of the skin effect, the actual resistance of the trace is: , the skin depth δ of the trace is smaller than the thickness t, so the actual resistance of the trace is larger.

[0062] In chip packaging design, copper is the mainstream material for traces, but copper easily diffuses into surrounding insulating materials (such as silicon dioxide), easily causing short circuits between adjacent traces. Cobalt is used to cover the surface of copper traces as a barrier layer to prevent copper diffusion. Cobalt not only has a strong diffusion barrier but can also be made thinner (1nm-2nm), saving wiring space while improving trace conductivity. At 7nm and higher nodes, some manufacturers use pure cobalt directly in the local interconnect layer. This is because cobalt has better conductivity than copper at extremely narrow line widths (<20nm) (copper has a more significant electron scattering effect). Therefore, cobalt is widely used in chip packaging.

[0063] However, the resistivity of cobalt and copper at room temperature (20°C) is about 6.64×10 -8 Ω·m and 1.678×10 -8 Ω·m, the resistivity of cobalt is greater than that of copper. As shown in the theoretical analysis above, the link loss is proportional to the bulk resistivity of the conductor surface. Due to the skin effect, cobalt with a higher resistivity acts as a barrier layer, which increases the link loss.

[0064] In order to solve the above problems, the embodiments of the present application provide a substrate. Figure 1 A schematic structural diagram of a substrate provided in an embodiment of the present application; Figure 2 for Figure 1 A local enlarged view of the substrate at position M; Figure 3 for Figure 2 A cross-sectional view of the trace along section line AA'.

[0065] See also Figures 1 to 3 The substrate 1 includes a trace 2 disposed in the substrate 1 . The trace 2 includes a first conductive structure 21 and a second conductive structure 22 . The second conductive structure 22 is connected to the surface of the first conductive structure 21 , and the second conductive structure 22 covers at least a portion of the surface of the first conductive structure 21 . For example, Figure 2 and Figure 3 In the embodiment, the second conductive structure 22 covers the upper surface and the lower surface of the first conductive structure 21 .

[0066] Exemplarily, along the first direction U pointing from the first conductive structure 21 to the second conductive structure 22, the thickness of the first conductive structure 21 is greater than the thickness of the second conductive structure 22. The first conductive structure 21 can serve as the internal body of the trace 2, and the second conductive structure 22 serves as the surface layer of the trace 2. The thickness of the main body of the trace 2 is greater than the thickness of the surface layer, which can ensure that the overall resistance of the trace 2 is small, which is beneficial to reducing the conductor loss of the trace 2.

[0067] See also Figure 2 and Figure 3Along the first direction U, the second conductive structure 22 includes barrier layers 23 and conductive layers 24 alternately arranged, and the resistivity of the conductive layer 24 is lower than the resistivity of the barrier layer 23. Exemplarily, the material of the first conductive structure 21 includes copper, the material of the barrier layer 23 includes cobalt, and the material of the conductive layer 24 includes copper, and the resistivity of copper is lower than the resistivity of cobalt.

[0068] In the above-mentioned embodiment of the present application, in the high-speed signal wiring design of the chip substrate, an alternating structure of a blocking layer 23 and a conductive layer 24 is set on the surface of the trace 2, and the resistivity of the conductive layer 24 is less than the resistivity of the blocking layer 23. Compared with only setting a blocking layer on the surface of the trace, this structure can reduce the resistance of the surface of the trace 2.

[0069] Due to the skin effect during high-speed signal transmission, current concentrates on the surface of trace 2. By reducing the surface resistance of trace 2, signal attenuation caused by conductor loss can be reduced, thereby improving signal transmission integrity. Furthermore, barrier layer 23 prevents atoms in first conductive structure 21 and conductive layer 24 from diffusing into the dielectric, preventing short circuits between adjacent traces 2 and increasing the reliability of the system design.

[0070] In some embodiments, see Figure 2 and Figure 3 In the alternating structure of the second conductive structure 22, the film layer farthest from the first conductive structure 21 is the barrier layer 23, that is, the surface of the trace 2 is the barrier layer 23, which can further prevent the atoms in the conductive layer 24 from diffusing into the medium, avoid short circuits between adjacent traces 2, and increase the reliability of the system design.

[0071] In some embodiments, see Figure 2 and Figure 3 Along the first direction U, the thickness of the conductive layer 24 is greater than the thickness of the blocking layer 23. It can be understood that the resistivity of the conductive layer 24 is less than the resistivity of the blocking layer 23. By setting the thickness of the conductive layer 24 to be greater than the thickness of the blocking layer 23, the proportion of the thickness of the film layer with lower resistivity in the surface layer of the trace 2 can be increased, further reducing the resistance and conductor loss of the surface layer of the trace 2, improving the signal attenuation phenomenon caused by the skin effect, and thus improving the integrity of the signal transmission.

[0072] Exemplarily, the ratio of the thickness of the conductive layer 24 to the thickness of the blocking layer 23 is in the range of 4 to 8. Within this ratio range, a thicker thickness of the conductive layer 24 is beneficial to reducing the resistance of the surface layer of the trace 2, and a thinner thickness of the blocking layer 23 is also beneficial to reducing the resistance of the surface layer of the trace 2, and a thinner blocking layer 23 can meet the effect of preventing the conductive material in the first conductive structure 21 and the conductive layer 24 from diffusing into the medium.

[0073] For example, the ratio of the thickness of the conductive layer 24 to the thickness of the blocking layer 23 is 4, 5, 6, 7 or 8. When these ratios are met, the thicker thickness of the conductive layer 24 is beneficial to reducing the resistance of the surface of the trace 2, and the thinner thickness of the blocking layer 23 is also beneficial to reducing the resistance of the surface of the trace 2, and the thinner blocking layer 23 can meet the effect of preventing the conductive material in the first conductive structure 21 and the conductive layer 24 from diffusing into the medium.

[0074] In the embodiment of the present application, the thickness of the barrier layer is 25 nm and the thickness of the conductive layer is 150 nm. The ratio of the thickness of the conductive layer 24 to the thickness of the barrier layer 23 is 6.

[0075] In some embodiments, see Figure 2 and Figure 3 Along the first direction U, the second conductive structure 22 includes a plurality of barrier layers 23 and a plurality of conductive layers 24 arranged alternately. The thickness of the plurality of conductive layers 24 can be set to be equal, ensuring the consistency of the film thickness and reducing the difficulty of the preparation process.

[0076] Alternatively, see Figure 4 , Figure 4 This is a partial enlarged view of another substrate at position M provided in an embodiment of the present application. The thicknesses of the multiple conductive layers 24 can also be set to be unequal. It is understood that the thickness design of the conductive layer 24 is related to the resistance of the surface layer of the trace 2. The conductor loss can be reduced by designing the thickness of the multiple conductive layers 24. For example, the multiple conductive layers 24 include a first conductive layer 24a close to the first conductive structure 21 and a second conductive layer 24b away from the first conductive structure 21. The thickness of the second conductive layer 24b is greater than the thickness of the first conductive layer 24a.

[0077] It can be understood that the second conductive layer 24b is closer to the surface of the trace 2 than the first conductive layer 24a. According to the skin effect principle during high-speed signal transmission, the current density in the second conductive layer 24b is greater than the current density in the first conductive layer 24a.

[0078] By setting the thickness of the second conductive layer 24b to be greater than the thickness of the first conductive layer 24a, the resistance of the second conductive layer 24b is made smaller than the resistance of the first conductive layer 24a, and the conductor loss in the second conductive layer 24b can be reduced in a targeted manner, thereby reducing the conductor loss in the surface layer as a whole, improving the signal attenuation caused by the skin effect, and improving the integrity of signal transmission.

[0079] Exemplarily, along the first direction U, the thicknesses of the multiple conductive layers 24 increase successively, that is, the closer the conductive layer 24 is to the surface of the trace 2, the smaller the resistance. According to the skin effect principle during high-speed signal transmission, the current density in the conductive layer 24 closer to the surface is greater. Through the above-mentioned design, the conductor loss in each conductive layer 24 can be reduced in a targeted manner, thereby reducing the conductor loss of the surface layer as a whole, improving the signal attenuation phenomenon caused by the skin effect, and improving the integrity of the signal transmission.

[0080] In some embodiments, see Figure 2 and Figure 3 Along the first direction U, the second conductive structure 22 includes a plurality of barrier layers 23 and a plurality of conductive layers 24 arranged alternately. The thickness of the plurality of barrier layers 23 can be set to be equal, ensuring the consistency of the film thickness and reducing the difficulty of the preparation process.

[0081] Alternatively, see Figure 4 The thicknesses of the multiple barrier layers 23 can also be set to be unequal. It is understood that the thickness design of the barrier layer 23 is also related to the surface resistance of the trace 2. Conductor loss can be reduced by designing the thickness of the multiple barrier layers 23. For example, the multiple barrier layers 23 include a first barrier layer 23a close to the first conductive structure 21 and a second barrier layer 23b farther from the first conductive structure 21. The thickness of the second barrier layer 23b is less than that of the first barrier layer 23a.

[0082] It can be understood that the second blocking layer 23b is closer to the surface of the trace 2 than the first blocking layer 23a. According to the principle of skin effect during high-speed signal transmission, the current is concentrated on the surface of the trace 2. By setting the thickness of the second blocking layer 23b to be smaller than the thickness of the first blocking layer 23a, the thickness ratio of the blocking layer 23 near the surface can be reduced, and the thickness ratio of the conductive layer 24 near the surface can be increased, thereby reducing the resistance near the surface, thereby reducing the conductor loss of the surface as a whole, improving the signal attenuation phenomenon caused by the skin effect, and improving the integrity of the signal transmission.

[0083] Exemplarily, along the first direction U, the thicknesses of the plurality of blocking layers 23 decrease successively, that is, the closer the blocking layer 23 is to the surface of the trace 2, the smaller the thickness is. According to the principle of skin effect during high-speed signal transmission, the closer to the surface, the greater the current density is. The above-mentioned design can specifically reduce the resistance near the surface, thereby reducing the conductor loss of the surface as a whole, improving the signal attenuation phenomenon caused by the skin effect, and improving the integrity of the signal transmission.

[0084] In some embodiments, see Figure 4The multiple conductive layers 24 include a first conductive layer 24a close to the first conductive structure 21 and a second conductive layer 24b away from the first conductive structure 21. The thickness of the second conductive layer 24b is greater than that of the first conductive layer 24a. Furthermore, the multiple barrier layers 23 include a first barrier layer 23a close to the first conductive structure 21 and a second barrier layer 23b away from the first conductive structure 21. The thickness of the second barrier layer 23b is less than that of the first barrier layer 23a.

[0085] By setting the thickness of the second conductive layer 24b to be greater than the thickness of the first conductive layer 24a, the resistance of the second conductive layer 24b is made smaller than the resistance of the first conductive layer 24a, and the conductor loss in the second conductive layer 24b can be reduced in a targeted manner, thereby reducing the conductor loss in the surface layer as a whole, improving the signal attenuation caused by the skin effect, and improving the integrity of signal transmission.

[0086] Moreover, by setting the thickness of the second blocking layer 23b to be smaller than the thickness of the first blocking layer 23a, the thickness ratio of the blocking layer 23 near the surface can be reduced, and the thickness ratio of the conductive layer 24 near the surface can be increased, thereby reducing the resistance near the surface, thereby reducing the conductor loss of the surface layer as a whole, improving the signal attenuation phenomenon caused by the skin effect, and improving the integrity of signal transmission.

[0087] Exemplarily, along the first direction U, the thickness of multiple conductive layers 24 increases successively, and the thickness of multiple blocking layers 23 decreases successively, that is, the thickness of the conductive layer 24 closer to the surface of the trace 2 is greater, and the thickness of the blocking layer 23 closer to the surface of the trace 2 is smaller.

[0088] According to the principle of skin effect during high-speed signal transmission, the current density increases closer to the surface. The aforementioned design can specifically reduce the resistance near the surface, thereby reducing the overall surface conductor loss, improving the signal attenuation caused by the skin effect, and thus improving the integrity of signal transmission.

[0089] In some embodiments, see Figure 2 and Figure 3 , along a second direction Z perpendicular to the plane of the substrate 1, the first conductive structure 21 includes a first surface 101 and a second surface 102 relative to each other, and the trace 2 includes two second conductive structures 22, one second conductive structure 22 is arranged on the first surface 101, and the other second conductive structure 22 is arranged on the second surface 102.

[0090] It can be understood that in direction Z, the barrier layers 23 and conductive layers 24 are alternately stacked on the upper and lower surfaces of the first conductive structure 21. This reduces the resistance of both the upper and lower surfaces of trace 2, thereby minimizing signal attenuation caused by conductor loss and improving signal transmission integrity. Furthermore, the barrier layers 23 provided on both the upper and lower surfaces of trace 2 prevent the conductive material in these upper and lower surfaces from diffusing into the dielectric medium.

[0091] To verify that the conductor loss of trace 2 is reduced, the inventors of this application conducted a comparative test and obtained the following results: Figure 5 The simulation curve diagram shown.

[0092] See also Figure 5 The simulation graph shows the frequency of the signal transmitted by the trace on the horizontal axis (GHz), and the insertion loss of the signal transmitted by the trace on the vertical axis (dB). The black curve represents the trace in the design. The trace is 10 inches long, with a 17.5μm thick inner body (copper) and a 1μm thick barrier layer (cobalt) on the surface.

[0093] The "blue curve" represents trace 2 in the embodiment of this application, with a length of 10 inches. Along the first direction U, the thickness of the first conductive structure 21 (copper) of trace 2 is 17.5 μm. The second conductive structure 22 includes six barrier layers 23 (cobalt) and five conductive layers 24 (copper), alternating between them. The barrier layers 23 are 25 nm thick, and the conductive layers 24 are 150 nm thick. This results in a thickness of 0.9 μm for the second conductive structure 22, which is significantly less than that of the first conductive structure 21.

[0094] By comparison, it can be seen that when the signal frequency is greater than or equal to 10GHz, the insertion loss of the routing 2 of the present application is lower than that of the routing of the related design. When the signal frequency is 30GHz, the insertion loss of the routing 2 of the present application is about -4dB, and the insertion loss of the routing of the related design is about -5dB. Compared with the insertion loss of the related design, the insertion loss of the present application is significantly improved by 1.0dB, indicating that the routing of the present application has a lower insertion loss when transmitting high-frequency signals, which can reduce the signal attenuation caused by conductor loss and improve the integrity of signal transmission.

[0095] The embodiments of the present application also provide a detailed structural diagram of the substrate, such as Figure 6 As shown, the substrate 1 further includes a laminated core 3 and a prepreg (PP) 4, with the trace 2 disposed between the core 3 and the prepreg 4. Along the first direction U, the thickness of the core 3 is 3 mils, and the thickness of the prepreg 4 is 4 mils.

[0096] It should be noted that in order to clearly show the internal structure of the substrate 1, Figure 5 The substrate 1 in the figure only shows one core board 3, two prepregs 4 and two wiring layers. The embodiment of the present application does not limit the number of core boards 3, prepregs 4 and wiring layers in the substrate 1.

[0097] Compared with the 5mil core 6 mil pp substrate design, that is, the core board is 5mil thick and the prepreg is 6mil thick, when the substrate includes 40 routing layers, 39 core boards and prepregs, the total thickness of the substrate can reach 4mm. The risks brought by this thick board are high machining risks, including drill bit wear and breakage during drilling, resulting in defects such as vacancy deviation and inconsistent aperture, which affect the reliability of the substrate. At the same time, the thick board has higher mechanical strength and stricter tolerance control, which increases the scrap rate. What is more serious is that the thick board increases the length of high-speed vias. The inductance of long vias exceeds the capacitance, resulting in increased via impedance. The impedance exceeded by the via due to the increased inductance is difficult to optimize and control, resulting in discontinuous link impedance and increased reflection noise, which affects the signal eye width and thus the signal quality.

[0098] In the above-mentioned embodiment of the present application, the stacking of the system link is optimized. On the basis of the copper and cobalt alternating structure design of the routing 2, the stacking design is changed to 3mil core 4 mil pp. When the substrate 1 includes 40 routing layers, core boards 3 and prepregs 4, a total of 39, this design reduces the total thickness of the substrate 1 by 1.6mm, and the board thickness is reduced to 2.4mm, thereby reducing the difficulty and cost of machining and improving the yield and reliability of the substrate 1. In addition, the thinning of the substrate 1 also reduces the length of the via, which is beneficial to reducing the impedance of the via and can improve the integrity of the system signal.

[0099] The embodiments of the present application also provide a method for preparing a substrate. Figure 7A to Figure 7C A diagram of the steps for preparing a substrate provided in an embodiment of the present application.

[0100] The method for preparing the substrate 1 includes forming a trace 2 within the substrate 1. The trace 2 includes a first conductive structure 21 and a second conductive structure 22. The second conductive structure 22 is connected to the surface of the first conductive structure 21 and covers at least a portion of the surface of the first conductive structure 21. The second conductive structure 22 includes alternating barrier layers 23 and conductive layers 24. The resistivity of the conductive layers 24 is lower than that of the barrier layers 23.

[0101] For example, see Figure 7AAlong the direction Z, a plurality of barrier layers 23 and a plurality of conductive layers 24 are alternately formed on the core board 3 of the substrate 1 to obtain the second conductive structure 22. For example, an electroplating process can be used to form the alternately stacked barrier layers 23 and conductive layers 24 on both the upper and lower surfaces of the core board 3.

[0102] See also Figure 7B The first conductive structure 21 is formed on the side of the second conductive structure 22 away from the core board 3. For example, the first conductive structure 21 can be formed on both the upper and lower surfaces of the core board 3 by using an electroplating process.

[0103] See also Figure 7C Multiple barrier layers 23 and multiple conductive layers 24 are alternately formed on the side of the first conductive structure 21 away from the core board 3 to obtain the second conductive structure 22. For example, an electroplating process can be used to form barrier layers 23 and conductive layers 24 on both the upper and lower surfaces of the core board 3. Thus, traces 2 are formed on both the upper and lower surfaces of the core board 3. Trace 2 includes a first conductive structure 21 and two second conductive structures 22. The first conductive structure 21, the multiple barrier layers 23, and the multiple conductive layers 24 are stacked along the direction Z.

[0104] In the above-described embodiment of the present application, barrier layers 23 and conductive layers 24 are alternately formed on the surface of trace 2. The resistivity of conductive layer 24 is lower than that of barrier layer 23. Compared to providing barrier layers only on the surface of the trace, this structure can reduce the surface resistance of trace 2, mitigate signal attenuation caused by conductor loss, and improve signal transmission integrity. Furthermore, barrier layers 23 can prevent atoms in first conductive structure 21 and conductive layer 24 from diffusing into the substrate dielectric, preventing short circuits between adjacent traces and increasing the reliability of the system design.

[0105] Before preparing and forming the trace 2, it is necessary to design the trace 2 in advance to determine the number and thickness of the barrier layer 23 (cobalt) and the conductive layer 24 (copper) in the second conductive structure 22, such as Figure 8 As shown, the design process of trace 2 includes the following steps S1 to S4:

[0106] S1: Establishing a routing model and evaluating the number and thickness of copper / cobalt layers in the alternating structure required for the routing to determine the initial values ​​of the number and thickness of the barrier layer 23 and the conductive layer 24 in the second conductive structure 22 .

[0107] S2: According to the skin effect theory, adjust the number and thickness of copper / cobalt layers in the alternating structure.

[0108] S3: Calculate the impedance and insertion loss of trace 2 under the parameters in step S2 to see if they meet the link requirements. If not, return to step S2 for adjustment.

[0109] S4: When the impedance and insertion loss of trace 2 meet the link requirements, the number of layers and thickness parameters of the alternating structure copper / cobalt are handed over to the manufacturer for processing and production.

[0110] The embodiments of the present application also provide a substrate and wiring design. Figure 9 A cross-sectional schematic diagram of wiring in another substrate provided in an embodiment of the present application.

[0111] See also Figure 9 The trace 2 includes a first conductive structure 21 and a second conductive structure 22. The multiple barrier layers 23 and the multiple conductive layers 24 of the second conductive structure 22 are alternately surrounded on the surface of the first conductive structure 21, that is, the second conductive structure 22 surrounds the outside of the first conductive structure 21, which can not only reduce the surface resistance of the trace 2, reduce the signal attenuation caused by conductor loss, and improve the integrity of signal transmission, but also realize the wrapping of the barrier layer 23 on the trace 2, further preventing copper diffusion, and increasing the reliability of the system design.

[0112] The embodiments of the present application also provide a method for preparing the above substrate. Figure 10A to Figure 10D A diagram of the steps for preparing another substrate provided in an embodiment of the present application.

[0113] The method for preparing the substrate 1 includes forming a trace 2 within the substrate 1. The trace 2 includes a first conductive structure 21 and a second conductive structure 22. The second conductive structure 22 is connected to the surface of the first conductive structure 21 and covers at least a portion of the surface of the first conductive structure 21. The second conductive structure 22 includes alternating barrier layers 23 and conductive layers 24. The resistivity of the conductive layers 24 is lower than that of the barrier layers 23.

[0114] For example, see Figure 10A , a groove 30 is formed on the surface of the core plate 3 of the substrate 1.

[0115] See also Figure 10B A plurality of barrier layers 23 and a plurality of conductive layers 24 are alternately formed on the surface of the groove 30 to obtain a first alternating structure 25. For example, an electroplating process can be used to form the alternately stacked barrier layers 23 and conductive layers 24 on the surface of the groove 30.

[0116] See also Figure 10C , a first conductive structure 21 is formed in the groove 30, and the first conductive structure 21 is located inside the first alternating structure 25. For example, the first conductive structure 21 can be formed in the groove 30 by using an electroplating process.

[0117] See also Figure 10DAlong the direction Z, a plurality of barrier layers 23 and a plurality of conductive layers 24 are alternately formed on the first conductive structure 21 to obtain a second alternating structure 26. The second alternating structure 26 and the first alternating structure 25 together form a second conductive structure 22 surrounding the first conductive structure 21. For example, an electroplating process can be used to form the barrier layers 23 and the conductive layers 24 on the first conductive structure 21. At this point, the preparation of the trace 2 is completed.

[0118] In the above-mentioned embodiment of the present application, a first alternating structure 25 is obtained by digging grooves on the substrate 1 and alternately forming a barrier layer 23 and a conductive layer 24 in the groove 30. Then, a first conductive structure 21 is formed in the groove 30. The first alternating structure 25 can wrap the bottom and side surfaces of the first conductive structure 21. Finally, a plurality of stacked barrier layers 23 and a plurality of conductive layers 24 are alternately formed on the first conductive structure 21 to obtain a second alternating structure 26. The alternating structure surrounds the first conductive structure 21, which can reduce the surface resistance of the trace 2, reduce the signal attenuation caused by conductor loss, and improve the integrity of the signal transmission. It can also realize the wrapping of the barrier layer 23 around the trace 2, further prevent the phenomenon of copper diffusion, and increase the reliability of the system design.

[0119] The embodiments of the present application also provide a substrate and wiring design. Figure 11 This is a partial enlarged view of the wiring in another substrate provided in an embodiment of the present application.

[0120] See also Figure 11 Along the first direction U, the second conductive structure 22 includes a plurality of barrier layers 23 and a plurality of conductive layers 24 arranged alternately. Along the length extension direction X of the trace 2, the barrier layer 23 includes a plurality of spaced portions, that is, the barrier layer 23 is arranged in segments.

[0121] Typically, the material of the blocking layer 23 includes cobalt, and the material of the conductive layer 24 includes copper. As mentioned above, the resistivity of cobalt is greater than that of copper at room temperature. Based on this, by setting the blocking layer 23 into multiple spaced segments, the proportion of materials with higher resistivity in the surface layer of the trace 2 can be reduced, which can save the material of the blocking layer 23 and reduce the resistance of the surface layer of the trace 2, thereby reducing the signal attenuation caused by conductor loss and improving the integrity of signal transmission.

[0122] Moreover, along the first direction U, one of the two adjacent barrier layers 23 corresponds to the spacing area E of the other barrier layer 23, that is, the two adjacent barrier layers 23 are staggered in the direction X, and one barrier layer 23 can cover the spacing area E of the adjacent barrier layer 23. The two adjacent barrier layers 23 can form a full-surface barrier for the conductive layer 24, while reducing the surface resistance of the trace 2, it also prevents the atoms in the first conductive structure 21 and the conductive layer 24 from diffusing into the medium, avoiding short circuits between adjacent traces 2, and increasing the reliability of the system design.

[0123] For example, see Figure 11 The barrier layer 23 is the farthest from the first conductive structure 21 in the second conductive structure 22. The barrier layer 23 is located on the outermost side of the trace 2. The trace 2 can be arranged in sections or not. Figure 11 , the outermost barrier layer 23 is not segmented. The barrier layer 23 is a continuous film layer, which can better protect the surface of the trace 2 and prevent the copper in the trace 2 from diffusing into the medium of the substrate 1.

[0124] In some embodiments, see Figure 11 The two adjacent conductive layers 24 are connected via the spacing area E of the barrier layer 23. It can be understood that the spacing area E of the barrier layer 23 is a through opening, and the two adjacent conductive layers 24 are electrically connected via the through opening, thereby realizing parallel connection between the adjacent conductive layers 24, increasing the cross-sectional area of ​​the conductive part in the surface layer of the trace 2, thereby reducing the resistance of the surface layer of the trace 2, reducing the signal attenuation caused by conductor loss, and improving the integrity of signal transmission.

[0125] The embodiment of the present application further provides a graphics processing unit (GPU) board, for example, a GPU server high-speed and high-density UBB (Universal Baseboard) board. Figure 12 A planar structural diagram of a graphics processor board provided in an embodiment of the present application; Figure 13 for Figure 12 A partial cross-sectional view of the graphics processor board along section line BB'.

[0126] See also Figure 12 and Figure 13 The graphics processor board 10 includes a baseboard 1, multiple open accelerator modules (OAMs) 5, and multiple graphics processor chips 6. The multiple OAMs 5 are disposed on the baseboard 1 and electrically connected to the baseboard 1. A graphics processor chip 6 is disposed on a side of each OAM 5 away from the baseboard 1 and electrically connected to the OAM 5.

[0127] For example, the substrate 1 can be a UBB, which carries eight open acceleration modules 5. The multiple open acceleration modules 5 are interconnected through the traces 2 on the substrate 1 (transmitting 112G PAM4 signals), enabling the transmission of large amounts of management information, monitoring data, and service configuration data between the open acceleration modules 5. This allows for rapid data transfer between different open acceleration modules 5 entities, meeting the requirements of high-speed communication.

[0128] Furthermore, through low-latency data transmission, the Open Accelerator Module 5 can promptly obtain device status information, performance data, and more, and quickly respond and make decisions, improving the management efficiency and real-time performance of the Open Accelerator Module 5 system. At the same time, PAM4 technology achieves higher data rates without proportionally increasing the signal rate, thereby more effectively managing power consumption and heat dissipation. Compared with traditional NRZ technology, PAM4 technology reduces overall power consumption while ensuring information transmission, meeting the requirements of green communications and energy conservation.

[0129] Exemplarily, the graphics processor board 10 further includes a connector 7 (Mezz), through which the open acceleration module 5 is electrically connected to the trace 2 on the substrate 1. For example, the substrate 1 further includes a conductive via 9, which is electrically connected to the trace 2. The connector 7 has pins, and the pins of the connector 7 can be inserted into the conductive via 9, thereby achieving sequential electrical connection between the connector 7, the conductive via 9, and the trace 2.

[0130] Exemplarily, the graphics processor board 10 further includes a plurality of pins 8, which are used to connect the graphics processor board 10 to the server motherboard. Each open acceleration module 5 is connected to the server motherboard via a high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, PCIe) interface, meeting the requirements for fast data exchange between the UBB board and the server motherboard and ensuring efficient data transmission.

[0131] In UBB board design, signal attenuation increases with frequency in the transmission medium, and 112G PAM4 signals, due to their inclusion of higher-order harmonics, experience even more significant attenuation. Therefore, the integrity of 112G PAM4 signals is of particular concern during design. Based on this, the inventors of this application selected trace 2, the longest on substrate 1, and conducted simulation experiments on this trace 2, as detailed below:

[0132] In some embodiments, see Figure 12The multiple open acceleration modules 5 include multiple rows and columns arranged in an array, each row of open acceleration modules 5 is arranged along a third direction A parallel to the plane where the substrate 1 is located, and each column of open acceleration modules 5 is arranged along a fourth direction B parallel to the plane where the substrate 1 is located, and the third direction A intersects with the fourth direction B. For example, the third direction A and the fourth direction B are perpendicular to each other.

[0133] The multiple rows of open acceleration modules 5 include rows 1 to n, where n≥2, and the multiple columns of open acceleration modules 5 include columns 1 to m, where m≥2. For example, the graphics processor board 10 includes 8 open acceleration modules 5, and the 8 open acceleration modules 5 include 2 rows and 4 columns arranged in an array.

[0134] In the design, we found that Figure 12 The first trace 20 between the open acceleration module 53 in the first row and first column (the open acceleration module 5 located in the upper left) and the open acceleration module 54 in the nth row and mth column (the open acceleration module 5 located in the lower right) is the longest link trace on the substrate 1. By way of example, the length of the first trace 20 is 30 inches. It will be appreciated that multiple open acceleration modules 5 are interconnected via different traces 2. To clearly illustrate the longest trace 20, the other traces are omitted in the figure.

[0135] Continue to see Figure 12 The first trace 20 includes a first segment 20a, a second segment 20b, and a third segment 20c connected in sequence. The first segment 20a extends along the fourth direction B, and the first segment 20a is located on the side of the open acceleration module 51 in the first column away from the open acceleration module 52 in the mth column. The first segment 20a is electrically connected to the open acceleration module 53 located in the first row and the first column.

[0136] The second section 20b extends along the third direction A and is located between the i-th row of open acceleration modules and the i+1-th row of open acceleration modules, where 1≤i≤n-1. That is, the second section 20b is located between two adjacent rows of open acceleration modules 5. For example, if the open acceleration modules 5 include two rows, the second section 20b is located between the first row of open acceleration modules and the second row of open acceleration modules. This is not a limitation of the present application. If the open acceleration modules 5 include three or more rows, the second section 20b may be located between the first row of open acceleration modules and the second row of open acceleration modules, between the second row of open acceleration modules and the third row of open acceleration modules, or between any other two adjacent rows.

[0137] The third section 20c extends along the fourth direction A and is located on a side of the open acceleration module 52 in the mth column away from the open acceleration module 51 in the first column. The third section 20c is electrically connected to the open acceleration module 54 in the nth row and the mth column.

[0138] Based on the above, the inventors of this application set up three groups of simulation experiments. In Example 1, the substrate 1 adopts a 5milcore 6mil PP design, the routing adopts a conventional setting (a layer of cobalt covering the copper surface), and the length of the routing is 30 inches; in Example 2, the substrate 1 adopts a 5mil core 6mil PP design, the routing adopts an alternating structure of a barrier layer 23 and a conductive layer 24, and the length of the routing is 30 inches; in Example 3, the substrate 1 adopts a 3mil core 4mil PP design, the routing adopts an alternating structure of a barrier layer 23 and a conductive layer 24, and the length of the routing is 30 inches.

[0139] The structures of the three sets of simulation experiments are as follows:

[0140]

[0141] As shown in the table above, in Example 1, the routing loss was controlled at 0.74dB / inch, resulting in an actual insertion loss of 27.4dB for the entire link. This difference is small compared to the designed insertion loss of 28dB, indicating a small link margin. The COM simulation results show an actual insertion loss of 3.024dB, which is also small compared to the designed COM insertion loss of 3dB, indicating poor signal transmission integrity and a medium risk.

[0142] In Example 2, the routing uses an alternating copper and cobalt structure. Compared to Example 1, the routing loss is reduced to 0.54dB / inch. The actual insertion loss of the entire link is 21.6dB, which is significantly different from the designed insertion loss of 28dB, indicating a large link margin. In the COM simulation results, the actual insertion loss (COM) is 6.161dB, which is significantly higher than the designed COM insertion loss of 3dB, indicating good signal transmission integrity and low risk.

[0143] In Example 3, substrate 1 adopts a 3-mil core 4-mil PP design. The thickness of substrate 1 is reduced, and the routing adopts an alternating structure of barrier layers 23 and conductive layers 24. The routing loss is reduced to 0.7 dB / inch. The actual insertion loss of the entire link is 26.1 dB, and the actual COM insertion loss is 3.388 dB. Compared with Example 1, this link (Example 3) is judged to be low risk.

[0144] An embodiment of the present application further provides an electronic device, Figure 14 This is a structural block diagram of the electronic device provided in an embodiment of the present application.

[0145] See also Figure 14The electronic device 100 can be a computer. The electronic device 100 includes a motherboard 101 and a graphics processor board 10. The graphics processor board is electrically connected to the motherboard 101. The graphics processor board 10 and the motherboard 101 exchange data quickly to ensure efficient data transmission.

[0146] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A substrate, characterized in that including traces disposed within the substrate; The trace includes a first conductive structure and a second conductive structure, wherein the second conductive structure is connected to a surface of the first conductive structure and covers at least a portion of the surface of the first conductive structure; Along a first direction pointing from the first conductive structure to the second conductive structure, the second conductive structure includes a plurality of barrier layers and a plurality of conductive layers alternately arranged, and the resistivity of the conductive layer is smaller than the resistivity of the barrier layer; Along the length extension direction of the trace, the barrier layer includes a plurality of portions arranged at intervals; Along the first direction, in two adjacent barrier layers, one barrier layer corresponds to the spaced region of the other barrier layer.

2. The substrate according to claim 1, wherein Along a second direction perpendicular to the plane where the substrate is located, the first conductive structure includes a first surface and a second surface opposite to each other; The trace includes two second conductive structures, one second conductive structure covers the first surface, and the other second conductive structure covers the second surface.

3. The substrate according to claim 1, wherein The second conductive structure has a plurality of barrier layers and a plurality of conductive layers that alternately surround the surface of the first conductive structure.

4. The substrate according to claim 1, wherein Along the first direction, the thickness of the first conductive structure is greater than the thickness of the second conductive structure.

5. The substrate according to claim 1, wherein Along the first direction, the thickness of the conductive layer is greater than the thickness of the barrier layer.

6. The substrate according to claim 5, wherein The ratio of the thickness of the conductive layer to the thickness of the barrier layer is in a range of 4 to 8.

7. The substrate according to claim 1, wherein Along the first direction, the second conductive structure includes a plurality of barrier layers and a plurality of conductive layers arranged alternately; The multiple conductive layers include a first conductive layer close to the first conductive structure and a second conductive layer far from the first conductive structure, and the thickness of the second conductive layer is greater than that of the first conductive layer.

8. The substrate according to claim 7, wherein Along the first direction, the thicknesses of the plurality of conductive layers increase sequentially.

9. The substrate according to claim 1, wherein Along the first direction, the second conductive structure includes a plurality of barrier layers and a plurality of conductive layers arranged alternately; The plurality of barrier layers include a first barrier layer close to the first conductive structure and a second barrier layer far from the first conductive structure, wherein the thickness of the second barrier layer is smaller than that of the first barrier layer.

10. The substrate according to claim 9, wherein Along the first direction, the thicknesses of the plurality of barrier layers decrease sequentially.

11. The substrate according to claim 1, wherein Two adjacent conductive layers are connected via the spacer region of the barrier layer.

12. The substrate according to claim 1, wherein In the second conductive structure, the film layer farthest from the first conductive structure is a barrier layer.

13. The substrate according to claim 1, wherein Along the first direction, the thickness of the first conductive structure is 17.5 μm; In the second conductive structure, six barrier layers and five conductive layers are alternately arranged; the thickness of the barrier layer is 25 nm, and the thickness of the conductive layer is 150 nm.

14. The substrate according to claim 1, wherein The material of the first conductive structure includes copper, the material of the barrier layer includes cobalt, and the material of the conductive layer includes copper.

15. The substrate according to claim 1, wherein The substrate further comprises a laminated core plate and a prepreg, wherein the wiring is arranged between the core plate and the prepreg; Along the first direction, the thickness of the core board is 3 mil, and the thickness of the prepreg is 4 mil.

16. A method for preparing a substrate, characterized in that: include: forming a trace in the substrate, the trace comprising a first conductive structure and a second conductive structure, wherein the second conductive structure is connected to a surface of the first conductive structure and covers at least a portion of the surface of the first conductive structure; Wherein, along a first direction from the first conductive structure to the second conductive structure, the second conductive structure includes a plurality of barrier layers and a plurality of conductive layers alternately arranged, and the resistivity of the conductive layer is smaller than the resistivity of the barrier layer; Along the length extension direction of the trace, the barrier layer includes a plurality of portions arranged at intervals; Along the first direction, in two adjacent barrier layers, one barrier layer corresponds to the spaced region of the other barrier layer.

17. The preparation method according to claim 16, characterized in that Forming the routing includes: Alternately forming a plurality of stacked barrier layers and a plurality of conductive layers on the substrate along a second direction perpendicular to the plane of the substrate to obtain the second conductive structure; forming the first conductive structure on a side of the second conductive structure away from the substrate; Along the second direction, a plurality of barrier layers and a plurality of conductive layers are alternately stacked on a side of the first conductive structure away from the substrate to obtain the second conductive structure.

18. The preparation method according to claim 16, characterized in that Forming the routing includes: forming a groove on a surface of the substrate; Alternately forming a plurality of stacked barrier layers and a plurality of conductive layers on the surface of the groove to obtain a first alternating structure; forming the first conductive structure in the groove, wherein the first conductive structure is located inside the first alternating structure; Along a second direction perpendicular to the plane of the substrate, multiple barrier layers and multiple conductive layers are alternately formed on the first conductive structure to obtain a second alternating structure. The second alternating structure and the first alternating structure together form the second conductive structure.

19. A graphics processor board, characterized in that: include: The substrate according to any one of claims 1 to 15; a plurality of open acceleration modules, disposed on the substrate and electrically connected to the wiring of the substrate; A plurality of graphics processor chips are provided, wherein one graphics processor chip is arranged on a side of an open acceleration module away from the substrate, and the graphics processor chip is electrically connected to the open acceleration module.

20. The graphics processor board according to claim 19, wherein: The plurality of open acceleration modules include a plurality of rows and columns arranged in an array, each row is arranged along a third direction parallel to the plane where the substrate is located, and each column is arranged along a fourth direction parallel to the plane where the substrate is located, and the third direction intersects the fourth direction; The multi-row open acceleration module includes the 1st row to the nth row, n≥2; the multi-column open acceleration module includes the 1st column to the mth column, m≥2; The routing includes at least a first routing, the first routing includes a first section, a second section, and a third section connected in sequence, the first section extending along the fourth direction and located on a side of the open acceleration module in the first column away from the open acceleration module in the mth column, and the first section is electrically connected to the open acceleration module in the first row and the first column; the second section extends along the third direction and is located between the open acceleration module in the i-th row and the open acceleration module in the i+1-th row, 1≤i≤n-1; the third section extends along the fourth direction and is located on a side of the open acceleration module in the m-th column away from the open acceleration module in the first column, and the third section is electrically connected to the open acceleration module in the n-th row and the m-th column.

21. An electronic device, characterized in that: include: Motherboard; The graphics processor board according to claim 19 or 20, wherein the graphics processor board is electrically connected to the mainboard.

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