Chip capable of saving bus wiring
By using the signal lines of the JTAG interface in the SoC chip instead of the traditional APB bus signal lines, the problem of high bus routing complexity between hard-core modules is solved, and low-power chip design is achieved.
CN120743846AActive Publication Date: 2025-10-03XIAMEN UNISOC TECH CO LTD
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Patent Information
- Application Number
- CN202511246888.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-02
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2045-09-02
AI Technical Summary
Technical Problem
In existing SoC chip designs, the bus routing between hard-core modules is highly complex and occupies a large area, resulting in high chip power consumption.
Method used
The signal lines (TCK, TDI, TMS, TDO) of the JTAG interface are used to replace the traditional APB bus signal lines. The conversion and timing synchronization of bus configuration information are realized through the instruction conversion unit and data synchronization unit, reducing the number of signal lines.
Benefits of technology
The chip design complexity is reduced, the bus routing amount is reduced, and low-power chip design is achieved.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention discloses a chip capable of saving bus routing, which comprises a master hardcore module and at least two slave hardcore modules, the master hardcore module comprises a chip bus master device, each slave hardcore module comprises an instruction conversion unit, a data synchronization unit and a register, the chip bus master device generates a JTAG instruction, and the JTAG instruction is transmitted to the slave hardcore module. A clock signal, a TMS signal and a TDI signal contained in a JTAG instruction are sent to each instruction conversion unit through a TCK signal line, a TMS signal line and a TDI signal line respectively, and the instruction conversion unit converts the TDI signal into an APB operation instruction and sends the APB operation instruction to the data synchronization unit; under the driving of the clock signal, based on the TMS signal and the TDI signal, obtaining output data, and sending the output data to a chip bus master device through a TDO signal line; the data synchronization unit carries out time sequence synchronization on the APB operation instruction and sends the APB operation instruction to the register for configuration; and the chip bus master device selects the output data and outputs the output data to the APB. According to the invention, low power consumption can be realized.
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