Special waveform generation method of extensible architecture
By adopting a scalable architecture on the hardware platform and utilizing a combination of SRAM, FLASH, and network chips, the problem of low efficiency in storing and retrieving large and multiple waveforms on domestically produced hardware platforms has been solved, enabling fast and flexible waveform switching and storage, and reducing hardware costs.
Patent Information
- Application Number
- CN202511143149.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2025-11-21
AI Technical Summary
In existing technologies, domestically produced hardware platforms suffer from low efficiency and high cost when storing and retrieving large or multiple waveforms, and require manual intervention, making it impossible to achieve fast and flexible waveform switching.
It adopts a scalable and open architecture, and uses SRAM, FLASH and network chips to realize the burning, storage and retrieval of special waveforms. The visual interface and host computer unpack data are written in Visual Basic language to generate three file formats, which store waveform address, length and cache information respectively. The FPGA retrieves data from SRAM as needed, and the DAC generates specific baseband waveforms.
It enables fast and flexible waveform switching and storage, reduces manual intervention, lowers hardware costs, and improves waveform retrieval efficiency.
Smart Images
Figure CN120994133A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of signal processing, and particularly relates to a waveform generation technology. BACKGROUND
[0002] At present, a radar mainly uses a linear frequency modulation (LFM) which has good pulse compression characteristics, effectively balances the contradiction between the radar action distance and the resolution, and is widely applied to a linear frequency modulation continuous wave radar, a pulse compression radar, a synthetic aperture radar (SAR) and an inverse synthetic aperture radar (ISAR).
[0003] The waveform of the LFM signal is simple, and the generation and processing are simple, and the LFM signal is easily interfered in a complex electromagnetic environment. The waveforms of nonlinear frequency modulation, phase coding, Barker code and M sequence are special, and change in the time domain, the frequency domain and the coding domain, the intrapulse modulation is complex, the waveform is agile between pulses, and good anti-interference performance is achieved.
[0004] Many special waveforms are iteratively generated by an artificial intelligence algorithm, and real-time calculation cannot be achieved, and a mainstream method is to store the waveforms on a board card, and the waveforms are called each time the power is turned on. SUMMARY
[0005] In order to solve the technical problems of storing and calling large waveforms and multiple waveforms of a domestic hardware platform, a technical scheme of an extensible and open architecture is adopted, SRAM, FLASH and a network chip for storing are used to realize the burning, storage and calling of special waveforms, and specifically, the technical scheme comprises the following steps. A visual interface is written by using a Visual Basic language, and original code element data is received, and a host computer unpacks the original code element data into a plurality of 1KB packet data.
[0006] The 1KB packet data format is as follows: 2 bytes of 55AA at the beginning, 2 bytes of the total waveform number, 2 bytes of the current waveform serial number, 2 bytes of the total packet number of the waveform, 2 bytes of the current packet number, 2 bytes of the number of the first point, 2 bytes of the number of the second point, 2 bytes of the number of the Mth point, and 2 bytes of AA55 at the end, wherein the packet number = the waveform length / 1K.
[0007] The packet data generates three files: a first file stores all FLASH block addresses, a second file stores the lengths of all waveforms, and a third file stores the starting addresses of each waveform buffer to SRAM.
[0008] The format of the file one is: the first two bytes 66EE, the total waveform number 2 bytes, the FLASH block address used by the first waveform 2 bytes, the FLASH block address used by the second waveform 2 bytes, and so on, the FLASH block address used by the Nth waveform 2 bytes, and the end 2 bytes EE66.
[0009] The format of the file two is: the first two bytes 66AA, the total waveform number 2 bytes, the waveform length used by the first waveform 4 bytes, the waveform length used by the second waveform 4 bytes, and so on, the waveform length used by the Nth waveform 4 bytes, and the end 2 bytes AA66, wherein the waveform length = signal pulse width * DAC chip sampling rate.
[0010] The format of the file three is: the first two bytes 66CC, the total waveform number 2 bytes, the SRAM start address used by the first waveform 4 bytes, the SRAM start address used by the second waveform 4 bytes, and so on, the SRAM start address used by the Nth waveform 4 bytes, and the end 2 bytes CC66.
[0011] The burning process is fast, and the calibration function is provided, the burned waveform is error-free, and the user can burn the special waveform according to the requirement without the developer on site.
[0012] The three files are sent to the network chip, the network chip sends the data to M FLASH solidification, and then calls N SRAM, the FPGA calls the data from the SRAM according to the requirement, sends the special waveform code element to the DAC, the DAC generates the specific baseband waveform, and sends the specific baseband waveform to the excitation source.
[0013] According to different scenes, the number N of SRAM and the number M of FLASH can be adjusted according to the use requirement, and the extensible program architecture is matched, so that the hardware cost is saved. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figure 1 It is a principle framework diagram. DETAILED DESCRIPTION
[0015] The principle framework of the application is shown in Figure 1 The visual interface is written by using the Visual Basic language, the original code element data is received, the upper computer unpacks the original code element data into a plurality of 1KB packet data, generates three files, and sends the three files to the network chip, the network chip sends the data to M FLASH solidification, and then calls N SRAM, the FPGA calls the data from the SRAM according to the requirement, sends the special waveform code element to the DAC, the DAC generates the specific baseband waveform, and sends the specific baseband waveform to the excitation source.
[0016] 1KB sub-packet data format is: the first two bytes 55AA, total waveform number 2 bytes, current waveform number 2 bytes, total packet number 2 bytes, current packet number 2 bytes, the first point number 2 bytes, the second point number 2 bytes, and so on, the Mth point number 2 bytes, the last two bytes AA55, wherein the packet number = waveform length / 1K.
[0017] File one stores all used FLASH block addresses, file two stores the length of all waveforms, and file three stores the starting address of each waveform cache to SRAM.
[0018] The format of file one is: the first two bytes 66EE, total waveform number 2 bytes, the first waveform used FLASH block address 2 bytes, the second waveform used FLASH block address 2 bytes, and so on, the Nth waveform used FLASH block address 2 bytes, and the last two bytes EE66.
[0019] The format of file two is: the first two bytes 66AA, total waveform number 2 bytes, the first waveform used waveform length 4 bytes, the second waveform used waveform length 4 bytes, and so on, the Nth waveform used waveform length 4 bytes, and the last two bytes AA66, wherein the waveform length = signal pulse width * DAC chip sampling rate.
[0020] The format of file three is: the first two bytes 66CC, total waveform number 2 bytes, the first waveform used SRAM starting address 4 bytes, the second waveform used SRAM starting address 4 bytes, and so on, the Nth waveform used SRAM starting address 4 bytes, and the last two bytes CC66.
[0021] The prior art waveform loading method manually calculates the storage size, occupies human resources, and is stored in the FPGA program in the form of a programming language. Each time a waveform is added or changed, the FPGA program needs to be recompiled and regression tested, which consumes a lot of time.
[0022] The number N of SRAM and the number M of FLASH can be adjusted according to the use requirements.
[0023] The above is an embodiment of the present application, which does not limit the present application. Any modification, equivalent replacement, and improvement within the spirit and principle of the present application are included in the protection scope of the present application.
Claims
1. A method for generating a special waveform of an extensible architecture, characterized by, The application relates to a special waveform code symbol generation method and device. The visual interface is programmed by using a Visual Basic language, original code symbol data is received, and an upper computer unpacks the original code symbol data into a plurality of 1KB subpackaged data; the subpackaged data generates three files: a first file stores all used FLASH block addresses, a second file stores the lengths of all waveforms, and a third file stores the starting addresses of each waveform buffer in SRAM; the three files are sent to a network chip, the network chip sends the data to M FLASH solidification, and then calls the data into N SRAM, the FPGA calls the data from the SRAM according to requirements, sends special waveform codes to a DAC, the DAC generates specific baseband waveforms, and the waveforms are sent to an excitation source.
2. The method of claim 1, wherein, The 1KB subpackaged data format is: 2 bytes of 55AA at the beginning, 2 bytes of total waveform numbers, 2 bytes of current waveform serial numbers, 2 bytes of total package numbers of waveforms, 2 bytes of current package numbers, 2 bytes of the number of first points, 2 bytes of the number of second points, 2 bytes of the number of M points, and 2 bytes of AA55 at the end, wherein the package number=the waveform length / 1K.
3. The method of claim 1, wherein the special waveform is generated by a scalable architecture, and The format of the first file is: 2 bytes of 66EE at the beginning, 2 bytes of total waveform numbers, 2 bytes of the FLASH block address used by the first waveform, 2 bytes of the FLASH block address used by the second waveform, 2 bytes of the FLASH block address used by the Nth waveform, and 2 bytes of EE66 at the end.
4. The method of claim 1, wherein the special waveform is generated by a scalable architecture, and The format of the second file is: 2 bytes of 66AA at the beginning, 2 bytes of total waveform numbers, 4 bytes of the waveform length used by the first waveform, 4 bytes of the waveform length used by the second waveform, 4 bytes of the waveform length used by the Nth waveform, and 2 bytes of AA66 at the end, wherein the waveform length=the signal pulse width*DAC chip sampling rate.
5. The method of claim 1, wherein the special waveform is generated by the scalable architecture. The format of the third file is: 2 bytes of 66CC at the beginning, 2 bytes of total waveform numbers, 4 bytes of the SRAM starting address used by the first waveform, 4 bytes of the SRAM starting address used by the second waveform, 4 bytes of the SRAM starting address used by the Nth waveform, and 2 bytes of CC66 at the end.
6. The method of claim 1, wherein the special waveform is generated by the scalable architecture. The number N of SRAM and the number M of FLASH can be adjusted according to use requirements, and the program architecture is expandable.