Special waveform generation method of extensible architecture

By adopting a scalable architecture on the hardware platform and utilizing a combination of SRAM, FLASH, and network chips, the problem of low efficiency in storing and retrieving large and multiple waveforms on domestically produced hardware platforms has been solved, enabling fast and flexible waveform switching and storage, and reducing hardware costs.

CN120994133APending Publication Date: 2025-11-21NANJING RES INST OF ELECTRONICS TECH
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Patent Information

Application Number
CN202511143149.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-15
Publication Date
2025-11-21

AI Technical Summary

Technical Problem

In existing technologies, domestically produced hardware platforms suffer from low efficiency and high cost when storing and retrieving large or multiple waveforms, and require manual intervention, making it impossible to achieve fast and flexible waveform switching.

Method used

It adopts a scalable and open architecture, and uses SRAM, FLASH and network chips to realize the burning, storage and retrieval of special waveforms. The visual interface and host computer unpack data are written in Visual Basic language to generate three file formats, which store waveform address, length and cache information respectively. The FPGA retrieves data from SRAM as needed, and the DAC generates specific baseband waveforms.

Benefits of technology

It enables fast and flexible waveform switching and storage, reduces manual intervention, lowers hardware costs, and improves waveform retrieval efficiency.

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Abstract

A special waveform generation method of an extensible framework is characterized by comprising the steps that a Visual Basic language is used for compiling a visual interface, original code element data are received, and an upper computer unpacks the original code element data into multiple pieces of subpackage data with the size being 1 KB; the first file stores the addresses of all used FLASH blocks, the second file stores the lengths of all waveforms, and the third file stores the initial address of each waveform cached to an SRAM (Static Random Access Memory); 3 files are sent to the network chip, the network chip sends data to the M FLASH for solidification and then calls the data to the N SRAMs, the FPGA calls the data from the SRAMs according to requirements and sends special waveform code elements to the DAC, and the DAC generates specific baseband waveforms and sends the baseband waveforms to the excitation source.
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