Convolution input structure multiplexing method and device based on signal sliding window row block cache

By employing a signal sliding window row block caching method in convolutional neural network hardware, the problems of redundant loading of row pixels and waste of cache resources are solved, achieving an efficient convolutional input structure and improving the operating efficiency and energy efficiency of the CNN module.

CN120996109AInactive Publication Date: 2025-11-21CHANGSHA HAIGE BEIDOU INFORMATION TECH CO LTD
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Patent Information

Application Number
CN202511529229.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-10-24
Publication Date
2025-11-21
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

Existing convolutional neural network hardware designs suffer from problems such as redundant loading of row pixels, insufficiently intelligent cache refresh, large on-chip SRAM usage, and low efficiency of GNSS signal structure reuse.

Method used

A signal sliding window-based row block caching method is adopted to construct a row block sliding window, bank alternation refresh and row address rotation mechanism to realize on-demand refresh, inter-row reuse, bank alternation and address rotation, and optimize the convolution input structure.

Benefits of technology

It significantly reduces redundant input loading, improves data reuse rate, reduces SRAM access frequency and power consumption, and improves the operating efficiency of CNN modules, making it suitable for small SoC designs with limited area.

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Abstract

The embodiment of the invention provides a convolution input structure multiplexing method and device based on signal sliding window row block cache, and relates to the technical field of embedded intelligent sensing. The method is applied to a front-end cache of a multiply-accumulate array, and comprises the following steps: determining a cache configuration parameter according to a parameter of an executed convolution operation; establishing a plurality of line caches in the front-end cache according to the cache configuration parameters; newly added data obtained through the sliding window operation is written into a row cache; and reading data from the row cache when the multiply-accumulate array executes a calculation operation. According to the implementation mode provided by the invention, the input redundant loading is remarkably reduced, the reuse rate of the overlapped part of the adjacent sliding windows is increased, and the average access frequency of the SRAM is reduced.
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