Display panel, driving method thereof and display device

Abstract

The invention discloses a display panel, a driving method thereof and a display device. The display panel includes: a plurality of sub-pixels; the data lines are electrically connected with the sub-pixels; each demultiplexer comprises n transistors, first electrodes of the n transistors in the same demultiplexer are electrically connected with the same data signal end, second electrodes of the n transistors in the same demultiplexer are electrically connected with the n data lines in a one-to-one correspondence mode, and n is an integer larger than 1; in the first time period, the conduction sequence of the n transistors in the same demultiplexer is a first sequence, in the second time period, the conduction sequence of the n transistors in the same demultiplexer is a second sequence, and the first sequence is different from the second sequence. The embodiment of the invention provides a display panel, a driving method thereof and a display device. The problem of uneven display of the display panel can be solved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and its driving method, and a display device. Background Technology

[0002] With the continuous development of display technology, devices with display functions have been widely used in people's production and daily life. These devices include display panels, which contain multiple sub-pixels. Each sub-pixel includes pixel circuitry and a light-emitting element. The pixel circuitry drives the light-emitting element to emit light, thus realizing the display panel's light-emitting function. However, in existing technologies, display panels still suffer from the problem of uneven display (mura). Summary of the Invention

[0003] This application provides a display panel and its driving method and display device, which can improve the problem of uneven display on the display panel.

[0004] In a first aspect, embodiments of this application provide a display panel including multiple sub-pixels; multiple data lines electrically connected to the sub-pixels; a demultiplexer including n transistors, wherein the first terminals of the n transistors in the same demultiplexer are all electrically connected to the same data signal terminal, and the second terminals of the n transistors in the same demultiplexer are electrically connected to the n data lines one-to-one, where n is an integer greater than 1; in a first time period, the conduction sequence of the n transistors in the same demultiplexer is a first sequence, and in a second time period, the conduction sequence of the n transistors in the same demultiplexer is a second sequence, wherein the first sequence and the second sequence are different.

[0005] Secondly, embodiments of this application provide a driving method for a display panel, used to drive the display panel, the display panel including: multiple sub-pixels; multiple data lines, the data lines being electrically connected to the sub-pixels; a demultiplexer including n transistors, the first terminals of the n transistors in the same demultiplexer being electrically connected to the same data signal terminal, the second terminals of the n transistors in the same demultiplexer being electrically connected to the n data lines one-to-one, where n is an integer greater than 1; The driving methods include: In the first time period, the turn-on sequence of n transistors in the same demultiplexer is the first sequence; In the second time period, the turn-on sequence of the n transistors in the same demultiplexer is the second sequence, which is different from the first sequence.

[0006] Thirdly, embodiments of this application provide a display device, including: a display panel as described in the first aspect embodiment.

[0007] In this embodiment, the demultiplexer includes n transistors. In the first time period and the second time period, the conduction order of the n transistors in the same demultiplexer is different. Thus, the order in which the demultiplexer writes data voltage to the n data lines it is connected is also different. Compared with the demultiplexer in related technologies where the conduction order of multiple transistors is always the same in different time periods, this embodiment disrupts the inherent pattern of the demultiplexer writing data voltage to the data lines. Even if a display mura occurs, the display mura is no longer constant. For example, it can prevent the same display mura from always appearing in the same position or the display mura from always appearing in the same position, so that the human eye cannot recognize the display mura, thereby improving the problem of uneven display on the display panel. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 A schematic diagram of a display panel in the related art is shown; Figure 2 Show Figure 1 A timing diagram; Figure 3 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application; Figure 4 Show Figure 3 A timing diagram; Figure 5 Show Figure 3 Another timing diagram; Figure 6 This illustration shows another structural diagram of the display panel provided in an embodiment of this application; Figure 7 Show Figure 6 A timing diagram; Figure 8 Show Figure 3 Another timing diagram; Figure 9 Show Figure 3 Another timing diagram; Figure 10 Show Figure 3 Another timing diagram; Figure 11 Show Figure 6 Another timing diagram; Figure 12 Show Figure 6 Another timing diagram; Figure 13 Show Figure 6 Another timing diagram; Figure 14 Show Figure 6 Another timing diagram; Figure 15 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application; Figure 16 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 17 Show Figure 16 A timing diagram; Figure 18 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0010] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0011] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0012] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0013] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0014] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components. The term "drive" can refer to "control" or "operation." The display panel can be a display device or a module / part of a display device.

[0015] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0016] like Figure 1 As shown, in related technologies, the display panel adopts a diamond RGB pixel arrangement. Some data lines DL are used to transmit data voltage to the red sub-pixel R and the blue sub-pixel G, while other data lines DL are used to transmit data voltage to the green sub-pixel G. The demultiplexer 20' includes two transistors and is used to transmit data voltage to the two data lines DL in a time-division multiplexing manner. The two transistors are turned on or off under the control of control signals CKH1' and CKH2', respectively. Figure 2 As shown, taking the conduction of the transistors in the demultiplexer 20' when the control signals CKH1' and CKH2' are low as an example, during different periods of the display panel's operation, the control signal CKH1' is low first, followed by the control signal CKH2'. That is, the conduction sequence of the two transistors in the demultiplexer 20' is always the same at different times, resulting in the data voltage being written to the sub-pixels in the same way. If a display mura occurs, the pattern of the mura is the same (e.g., fixed brightness), making it easy for the human eye to recognize the display mura.

[0017] To address the aforementioned technical problems, this application provides a display panel and its driving method, as well as a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0018] like Figure 3 As shown, the display panel 100 provided in this application embodiment includes multiple sub-pixels 10, multiple data lines DL, and multiple demultiplexers 20.

[0019] Multiple sub-pixels 10 are arranged in an array along an intersecting first direction X and second direction Y. For example, the first direction X can be a row direction, and the second direction Y can be a column direction.

[0020] Sub-pixel 10 includes pixel circuit 11 and light-emitting element 12. Pixel circuit 11 is used to drive light-emitting element 12 to emit light. Light-emitting element 12 can be an organic light-emitting diode (OLED), or other types of light-emitting devices.

[0021] The data line DL is electrically connected to the sub-pixel 10. Specifically, the data line DL is electrically connected to the pixel circuit 11. The data line DL extends along the second direction Y, and one data line DL can be electrically connected to multiple pixel circuits 11 arranged in the second direction Y. Figure 3 The pixel circuit 11 is represented by a dashed box, and the data line DL is electrically connected to the pixel circuit 11 represented by the overlapping dashed box.

[0022] The demultiplexer 20 includes n transistors, where n is an integer greater than 1. The first terminals of the n transistors in the same demultiplexer 20 are all electrically connected to the same data signal terminal Source, and the second terminals of the n transistors in the same demultiplexer 20 are electrically connected to n data lines DL one-to-one. Additionally, the data signal terminal Source is electrically connected to the output pin of the driver chip (not shown in the figure). The demultiplexer 20 is used to transmit data voltage to the data lines DL to which it is electrically connected. The data voltage on the data lines DL is used to write data to the pixel circuit 11. The pixel circuit 11 generates a driving current based on the written data voltage to drive the light-emitting element 12 to emit light. The magnitude of the driving current generated by the pixel circuit 11 can vary depending on the data voltage.

[0023] Reference Figure 3 and Figure 4 In the first time period t1, the conduction sequence of n transistors in the same demultiplexer 20 is the first sequence. In the second time period t2, the conduction sequence of n transistors in the same demultiplexer 20 is the second sequence. The first sequence and the second sequence are different.

[0024] For example, refer to Figure 3 and Figure 4Taking a demultiplexer 20 comprising two transistors, namely transistor M1 and transistor M2, as an example, the gate of transistor M1 is used to receive control signal CKH1, and the gate of transistor M2 is used to receive control signal CKH2. For example, when control signals CKH1 and CKH2 are low, transistors M1 and M2 are turned on respectively. During the same period, transistors M1 and M2 of the demultiplexer 20 are turned on in a time-division manner; when transistor M1 is on, transistor M2 is off; when transistor M2 is on, transistor M1 is off. When transistor M1 is on, the data voltage at the data signal terminal Source is written to the data line DL connected to transistor M1; when transistor M2 is on, the data voltage at the data signal terminal Source is written to the data line DL connected to transistor M2. The data voltages transmitted by transistors M1 and M2 may be the same or different.

[0025] In the first time period t1, the first sequence is: transistor M1 turns on first, followed by transistor M2; in the second time period t2, the second sequence is: transistor M2 turns on first, followed by transistor M1. That is, the turn-on order of transistors M1 and M2 is different in the first time period t1 and the second time period t2, and the order in which the demultiplexer 20 writes data voltage to the two data lines DL connected to it is different.

[0026] For example, pixel circuit 11 is connected to scan signal scan2. Scan signal scan2 is used to control whether the data voltage on data line DL can be written to pixel circuit 11. For example, when scan signal scan2 is low, the data voltage on data line DL can be written to pixel circuit 11. In the accompanying drawings of this application, the conduction levels (e.g., low levels) of the multiple control signals CKH connected to demultiplexer 20 and the conduction level (e.g., low level) of scan signal scan2 do not overlap. In other embodiments, the last conduction level (e.g., low level) of the multiple control signals CKH connected to demultiplexer 20 may at least partially overlap with the conduction level (e.g., low level) of scan signal scan2.

[0027] It should be noted that, Figure 3 Taking the demultiplexer 20 as an example, which includes two transistors, this is not intended to limit this application. For example, in the illustrations of the following examples of this application, the demultiplexer 20 may include three transistors. Of course, the technical concept of this application can also be applied to the demultiplexer 20 including four or more transistors.

[0028] In this embodiment, the demultiplexer 20 includes n transistors. During the first time period t1 and the second time period t2, the conduction order of the n transistors in the same demultiplexer 20 is different. Therefore, the order in which the demultiplexer 20 writes data voltages to the n connected data lines DL is also different. Figure 2The multiple transistors of the demultiplexer shown in the application have the same turn-on sequence at different times. The embodiment of this application is equivalent to disrupting the inherent pattern of the demultiplexer writing data voltage to the data line DL. Even if a display mura occurs, the display mura is no longer constant. For example, it can avoid the same display mura from always appearing in the same position or the display mura always appearing in the same position, so that the human eye cannot recognize the display mura, thereby improving the problem of uneven display on the display panel.

[0029] In some embodiments, such as Figure 5 As shown, the same frame F includes the first time period t1 and the second time period t2.

[0030] For example, the display panel includes P rows of sub-pixels 10. Scan signals scan2_1 to scan2_P represent the scan signals received by sub-pixels 10 from the first row to the Pth row. Within one frame F, each row of sub-pixels 10 is scanned row by row, meaning that scan signals scan2_1 to scan2_P are successively turned on (e.g., low level). In other words, one frame F includes multiple row scanning stages HF. In one row scanning stage HF, the demultiplexer 20 is used to transmit data voltage to a row of sub-pixels 10.

[0031] The n transistors of the demultiplexer 20 are electrically connected one-to-one with the n columns of sub-pixels 10. During the row scanning phase HF corresponding to each row of sub-pixels 10, the n transistors of the demultiplexer 20 are turned on in a time-division manner.

[0032] For example, a portion of the row scanning phase HF corresponding to the row sub-pixels 10 includes a first time period t1, and another portion of the row scanning phase HF corresponding to the row sub-pixels 10 includes a second time period t2.

[0033] In this embodiment, the order in which the demultiplexer 20 writes data voltages to the n data lines DL connected to it within a frame F can be different. This is equivalent to disrupting the inherent pattern of the demultiplexer writing data voltages to the data lines DL within a frame. Even if a display mura appears in a frame, the display mura is no longer constant. For example, it can prevent the same display mura from appearing continuously at the same position within a frame or the display mura from appearing continuously at the same position, making it impossible for the human eye to recognize the display mura, thereby improving the problem of uneven display on the display panel.

[0034] In some embodiments, such as Figure 3 and Figure 5 As shown, the same data line DL is electrically connected to sub-pixels 10 of the same luminous color. A frame F includes multiple line scanning stages HF. The i-th line scanning stage HF includes the first time period t1, and the (i+1)-th line scanning stage HF includes the second time period t2. i is an integer greater than or equal to 1.

[0035] As an example, the display panel 100 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103 with different emitting colors. The first sub-pixel 101 in the same column is electrically connected to the first data line DL1, the second sub-pixel 102 in the same column is electrically connected to the second data line DL2, and the third sub-pixel 103 in the same column is electrically connected to the third data line DL3. In this way, the same data line DL only needs to transmit data voltage to the sub-pixel with one emitting color. When displaying a solid color image in the entire display area, the data voltage on the data line DL will not jump back and forth. That is, the data signal terminal Source does not need to provide jumping data voltage to the same data line DL, which can reduce power consumption.

[0036] Within the same frame, during the i-th line scan phase HF, demultiplexer 20 provides data voltage to sub-pixel 10 in the i-th row; during the (i+1)-th line scan phase HF, demultiplexer 20 provides data voltage to sub-pixel 10 in the (i+1)-th row. The i-th line scan phase HF and the (i+1)-th line scan phase HF are any two adjacent line scan phases, and sub-pixel 10 in the i-th row and sub-pixel 10 in the (i+1)-th row are any two adjacent rows of sub-pixels.

[0037] In this embodiment, the conduction order of the n transistors in the demultiplexer 20 is different during the adjacent row scanning stage, which makes the order in which the data voltage corresponding to the sub-pixels 10 of different rows and the same light emission color in the same frame is written to the data line different. This is equivalent to disrupting the inherent rule of the demultiplexer providing data voltage to the sub-pixels 10 of different rows and the same light emission color in a frame, thereby improving the problem of uneven display.

[0038] In some embodiments, please refer to the reference Figure 3 and Figure 5 The operation of the demultiplexer 20 within the same frame F includes multiple first conduction cycles W1, each of which includes a first time period t1 and a second time period t2.

[0039] In the first time period t1 of different first conduction cycles W1, the conduction sequence of the n transistors of the demultiplexer 20 is always the first sequence; in the second time period t2 of different first conduction cycles W1, the conduction sequence of the n transistors of the demultiplexer 20 is always the second sequence. In this embodiment, the working process of the demultiplexer 20 within the same frame F is divided into multiple first conduction cycles W1. The conduction sequence of the n transistors of the demultiplexer 20 is different in different time periods of the first conduction cycle W1. This not only disrupts the inherent pattern of the demultiplexer writing data voltage to the data line DL in different time periods to improve the problem of uneven display on the display panel, but also makes the conduction sequence of the n transistors of the demultiplexer 20 exhibit a certain periodicity in the overall time of a frame, so as to avoid the driving timing being too complex.

[0040] In some embodiments, such as Figure 3 and Figure 5 As shown, n=2, the first conduction period W1 includes two row scan phases HF. The demultiplexer 20 includes two transistors, one row scan phase HF within the first conduction period W1 includes a first time period t1, and the other row scan phase HF within the first conduction period W1 includes a second time period t2.

[0041] For example, within the same frame, the row scanning phase HF corresponding to the sub-pixels of odd-numbered rows includes a first time period t1, and the row scanning phase HF corresponding to the sub-pixels of even-numbered rows includes a second time period t2. The two transistors of the demultiplexer 20 are turned on in a first order to transmit data voltage to the sub-pixels of odd-numbered rows, and the two transistors of the demultiplexer 20 are turned on in a second order to transmit data voltage to the sub-pixels of even-numbered rows. In this embodiment, when the same data line DL is electrically connected to sub-pixels 10 of the same emission color, within the same frame, the order in which the data voltages corresponding to sub-pixels of different rows but the same color are written to the data line by the demultiplexer 20 is alternately rotated.

[0042] In other embodiments, such as Figure 6 and Figure 7 As shown, n=3, the first conduction cycle W1 includes 3 row scan stages HF.

[0043] The demultiplexer 20 includes three transistors. For example, the first row scan phase HF within the first conduction cycle W1 includes a first time period t1, and the second row scan phase HF within the first conduction cycle W1 includes a second time period t2. Furthermore, within the third row scan phase HF within the first conduction cycle W1, the conduction order of the three transistors in the demultiplexer 20 can be the same as the first order within the first time period t1.

[0044] For example, such as Figure 6 and Figure 7 As shown, when n=3, one row scan phase HF of the first conduction cycle W1 includes a third time period t3. In the third time period t3, the conduction sequence of the three transistors in the same demultiplexer 20 is the third sequence, and the first, second, and third sequences are all different. For example, the first row scan phase HF in the first conduction cycle W1 includes the first time period t1, the second row scan phase HF in the first conduction cycle W1 includes the second time period t2, and the third row scan phase HF in the first conduction cycle W1 includes the third time period t3.

[0045] The three transistors of the demultiplexer 20 are transistor M1, transistor M2 and transistor M3. The gate of transistor M1 is used to receive the control signal CKH1, the gate of transistor M2 is used to receive the control signal CKH2, and the gate of transistor M3 is used to receive the control signal CKH3. For example, when the control signals CKH1, CKH2 and CKH3 are low, they control transistors M1, M2 and M3 to turn on respectively.

[0046] Within the same first conduction period W1 of the same frame, there are three time periods: t1, t2, and t3. In the first time period t1, the first sequence is: transistor M1 turns on first, then transistor M2 turns on, and finally transistor M3 turns on.

[0047] In the second time period t2, the second sequence is: transistor M2 turns on first, then transistor M3 turns on, and finally transistor M1 turns on.

[0048] In the third time period t3, the sequence of transistors is as follows: transistor M3 turns on first, then transistor M1 turns on, and finally transistor M2 turns on.

[0049] That is, the turn-on sequence of transistors M1, M2 and M3 is different in the first time period t1, the second time period t2 and the third time period t3, and the order in which the demultiplexer 20 writes data voltage to the three data lines DL connected to it is different.

[0050] For example, within the same frame, the line scanning phase HF corresponding to the sub-pixel of the 3a+1th row includes a first time period t1, the line scanning phase HF corresponding to the sub-pixel of the 3a+2th row includes a second time period t2, and the line scanning phase HF corresponding to the sub-pixel of the 3a+3th row includes a third time period t3, where a is an integer greater than or equal to 0. The three transistors of demultiplexer 20 are turned on in a first sequence to transmit data voltage to the sub-pixels in row 3a+1, in a second sequence to transmit data voltage to the sub-pixels in row 3a+2, and in a third sequence to transmit data voltage to the sub-pixels in row 3a+3. In this embodiment, when the same data line DL is electrically connected to sub-pixels 10 of the same emission color, within the same frame, the order in which the data voltages corresponding to sub-pixels of different rows but the same color are written to the data line by demultiplexer 20 is alternately rotated.

[0051] The above Figure 5 and Figure 7 As illustrated in the example, the turn-on sequence of the demultiplexer 20 can be different at different times within the same frame.

[0052] In other examples, the turn-on order of the demultiplexer 20 may be different for the row scanning phase corresponding to the same row of subpixels in different frames, as illustrated below.

[0053] As described above, a frame consists of multiple line scanning stages. Within one line scanning stage, the demultiplexer 20 is used to provide data voltage to a line of sub-pixels. Figure 8 As shown, the k-th line scanning phase HF_k of frame j F_j includes the first time period t1, and the k-th line scanning phase HF_k of frame m F_m includes the second time period t2, where j and k are both integers greater than or equal to 1.

[0054] In the k-th row scan phase HF_k, demultiplexer 20 provides data voltage for the k-th row sub-pixel 10, which can be any row of sub-pixels. It is understood that the k-th row scan phase HF_k of frame j F_j and the k-th row scan phase HF_k of frame m F_m refer to the same row of sub-pixels.

[0055] In this embodiment, the order in which the demultiplexer 20 transmits data voltage to the same row of sub-pixels is different in different frames. This is equivalent to disrupting the inherent pattern of the demultiplexer writing data voltage to the data line DL in different frames. Even if display muras appear in different frames, the display muras are no longer constant. For example, it can prevent the same display mura from appearing in the same position in different frames or the display mura from appearing in the same position, so that the human eye cannot recognize the display muras, thereby improving the problem of uneven display on the display panel.

[0056] For example, frame j and frame m are two adjacent frames. Frame j and frame m can be any two adjacent frames. In this way, for the same row of sub-pixels, the conduction order of the n transistors in the demultiplexer 20 is different in the k-th row scanning stage of adjacent frames. This results in different order in which the data voltage corresponding to the sub-pixels in the same row is written to the data lines in any two adjacent frames. This is equivalent to disrupting the inherent pattern of the demultiplexer providing data voltage to the same row of sub-pixels in different frames, thereby improving the problem of uneven display.

[0057] In some embodiments, please refer to Figure 3 as well as Figure 9 or Figure 10 The working process of the demultiplexer 20 includes a second conduction period W2, which includes at least two frames F and a first time period t1 and a second time period t2.

[0058] For example, such as Figure 9As shown, within the second conduction period W2, at least one frame F includes only the first time period t1, and at least another frame F includes only the second time period t2. In this case, the conduction sequence of the n transistors of the demultiplexer 20 is the same in different line scan stages within the same frame F; however, the conduction sequence of the n transistors of the demultiplexer 20 is different in different frames within the second conduction period W2.

[0059] Or, such as Figure 10 As shown, within the second conduction period W2, at least one frame F includes a first time period t1 and a second time period t2. In this case, the conduction order of the n transistors of the demultiplexer 20 is different in at least two different line scan stages within the same frame F; and, within different frames of the second conduction period W2, the conduction order of the n transistors of the demultiplexer 20 is different for the line scan stage corresponding to the same row sub-pixel. This example achieves that the conduction order of the demultiplexer 20 is different in different time periods within the same frame, and also different in different frames for the line scan stage corresponding to the same row sub-pixel. This not only disrupts the inherent pattern of the demultiplexer providing data voltage to different row sub-pixels within the same frame, but also breaks the inherent pattern of the demultiplexer providing data voltage to the same row sub-pixel within different frames, thus better improving the problem of uneven display on the display panel.

[0060] As an example, please refer to Figure 3 as well as Figure 9 or Figure 10 If n=2, the second conduction cycle W2 includes two frames F. That is, when the demultiplexer 20 includes two transistors, every two frames F constitute one second conduction cycle W2.

[0061] like Figure 3 and Figure 9 As shown, in the first frame F of the second conduction period W2, each line scan phase HF includes a first time period t1. When scanning each line of pixels, the conduction sequence of the demultiplexer 20 is always the first sequence, which includes: transistor M1 is turned on first, followed by transistor M2. In the second frame F of the second conduction period W2, each line scan phase HF includes a second time period t2. When scanning each line of pixels, the conduction sequence of the demultiplexer 20 is always the second sequence, which includes: transistor M2 is turned on first, followed by transistor M1.

[0062] Or, such as Figure 3 and Figure 10As shown, each frame F of the second conduction period W2 includes a first conduction period W1, and each first conduction period W1 includes a first time period t1 and a second time period t2. Specifically, the low level of the scan signal scan2_1 corresponds to the line scan phase HF of the first row of sub-pixels, the low level of the scan signal scan2_2 corresponds to the line scan phase of the second row of sub-pixels, the low level of the scan signal scan2_3 corresponds to the line scan phase of the third row of sub-pixels, and so on.

[0063] In the first frame F of the second conduction period W2, the row scanning phase corresponding to the first row of sub-pixels includes a first time period t1. The conduction sequence of the demultiplexer 20 is a first sequence, which includes: transistor M1 is turned on first, followed by transistor M2. In the second frame F of the second conduction period W2, the row scanning phase corresponding to the first row of sub-pixels includes a second time period t2. The conduction sequence of the demultiplexer 20 is a second sequence, which includes: transistor M2 is turned on first, followed by transistor M1.

[0064] In the first frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a second time period t2. The conduction sequence of the demultiplexer 20 is a second sequence, which includes: transistor M2 is turned on first, followed by transistor M1. In the second frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a first time period t1. The conduction sequence of the demultiplexer 20 is a first sequence, which includes: transistor M1 is turned on first, followed by transistor M2.

[0065] The timing of the row scan phase corresponding to the third row of sub-pixels and subsequent odd-numbered row sub-pixels is the same as that of the row scan phase corresponding to the first row of sub-pixels; the timing of the row scan phase corresponding to the fourth row of sub-pixels and subsequent even-numbered row sub-pixels is the same as that of the row scan phase corresponding to the second row of sub-pixels; these will not be elaborated further here.

[0066] As another example, please refer to Figure 6 as well as Figure 11 or Figure 12 or Figure 13 If n=3, the second conduction cycle W2 consists of 3 frames. That is, when the demultiplexer 20 includes 3 transistors, every 3 frames F constitute one second conduction cycle W2.

[0067] When n=3, the second conduction period W2 includes a first time period t1, a second time period t2, and a third time period t3. The conduction sequence of the three transistors in the same demultiplexer 20 in the first time period t1 is the first sequence, the conduction sequence of the three transistors in the same demultiplexer 20 in the second time period t2 is the second sequence, and the conduction sequence of the three transistors in the same demultiplexer 20 in the third time period t3 is the third sequence. The first sequence, the second sequence, and the third sequence are all different.

[0068] like Figure 6 and Figure 11 As shown, in the first frame F of the second conduction period W2, each line scan phase HF includes a first time period t1. When scanning each line of pixels, the conduction sequence of the demultiplexer 20 is always the first sequence, which includes: transistor M1 is turned on first, then transistor M2 is turned on, and transistor M3 is turned on last. In the second frame F of the second conduction period W2, each line scan phase HF includes a second time period t2. When scanning each line of pixels, the conduction sequence of the demultiplexer 20 is always the second sequence, which includes: transistor M2 is turned on first, then transistor M3 is turned on, and transistor M1 is turned on last. In the third frame F of the second conduction period W2, each line scan phase HF includes a third time period t3. When scanning each line of pixels, the conduction sequence of the demultiplexer 20 is always the third sequence, which includes: transistor M3 is turned on first, then transistor M1 is turned on, and transistor M2 is turned on last.

[0069] Or, such as Figure 12 or Figure 13 As shown, each frame F of the second conduction period W2 includes a first conduction period W1, and each first conduction period W1 includes a first time period t1, a second time period t2, and a third time period t3. Specifically, the low level of the scan signal scan2_1 corresponds to the line scan phase HF of the first row of sub-pixels, the low level of the scan signal scan2_2 corresponds to the line scan phase of the second row of sub-pixels, the low level of the scan signal scan2_3 corresponds to the line scan phase of the third row of sub-pixels, and so on.

[0070] Figure 12In the second conduction period W2, in the first frame F, the row scanning phase corresponding to the first row of sub-pixels includes a first time period t1. The conduction sequence of the demultiplexer 20 is a first sequence, which includes: transistor M1 is turned on first, then transistor M2 is turned on, and transistor M3 is turned on last. In the second frame F of the second conduction period W2, the row scanning phase corresponding to the first row of sub-pixels includes a second time period t2. The conduction sequence of the demultiplexer 20 is a second sequence, which includes: transistor M2 is turned on first, then transistor M3 is turned on, and transistor M1 is turned on last. In the third frame F of the second conduction period W2, the row scanning phase corresponding to the first row of sub-pixels includes a third time period t3. The conduction sequence of the demultiplexer 20 is a third sequence, which includes: transistor M3 is turned on first, then transistor M1 is turned on, and transistor M2 is turned on last.

[0071] Figure 12 In the second conduction period W2, in the first frame F, the row scanning phase corresponding to the second row of sub-pixels includes a second time period t2. The conduction sequence of demultiplexer 20 is a second sequence, which includes: transistor M2 is turned on first, then transistor M3 is turned on, and transistor M1 is turned on last. In the second frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a third time period t3. The conduction sequence of demultiplexer 20 is a third sequence, which includes: transistor M3 is turned on first, then transistor M1 is turned on, and transistor M2 is turned on last. In the third frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a first time period t1. The conduction sequence of demultiplexer 20 is a first sequence, which includes: transistor M1 is turned on first, then transistor M2 is turned on, and transistor M3 is turned on last.

[0072] Figure 12 In the first frame F of the second conduction period W2, the row scanning phase corresponding to the third row of sub-pixels includes a third time period t3. The conduction sequence of demultiplexer 20 is the third sequence, which includes: transistor M3 is turned on first, then transistor M1 is turned on, and transistor M2 is turned on last. In the second frame F of the second conduction period W2, the row scanning phase corresponding to the third row of sub-pixels includes a first time period t1. The conduction sequence of demultiplexer 20 is the first sequence, which includes: transistor M1 is turned on first, then transistor M2 is turned on, and transistor M3 is turned on last. In the third frame F of the second conduction period W2, the row scanning phase corresponding to the third row of sub-pixels includes a second time period t2. The conduction sequence of demultiplexer 20 is the second sequence, which includes: transistor M2 is turned on first, then transistor M3 is turned on, and transistor M1 is turned on last.

[0073] Figure 13 and Figure 12The difference lies in the order of the first time period t1, the second time period t2, and the third time period t3 within the first conduction cycle W1. Specifically, Figure 13 In the second conduction period W2, in the first frame F, the row scanning phase corresponding to the first row of sub-pixels includes a first time period t1; in the second frame F of the second conduction period W2, the row scanning phase corresponding to the first row of sub-pixels includes a second time period t2; in the third frame F of the second conduction period W2, the row scanning phase corresponding to the first row of sub-pixels includes a third time period t3. In the first frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a third time period t3; in the second frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a first time period t1; in the third frame F of the second conduction period W2, the row scanning phase corresponding to the second row of sub-pixels includes a second time period t2; in the first frame F of the second conduction period W2, the row scanning phase corresponding to the third row of sub-pixels includes a second time period t2; in the second frame F of the second conduction period W2, the row scanning phase corresponding to the third row of sub-pixels includes a third time period t3; in the third frame F of the second conduction period W2, the row scanning phase corresponding to the third row of sub-pixels includes a first time period t1.

[0074] Figure 12 as well as Figure 13 In the diagram, the timing of the row scanning phase corresponding to the sub-pixel of row 3a+1 is the same as that of the row scanning phase corresponding to the sub-pixel of row 1; the timing of the row scanning phase corresponding to the sub-pixel of row 3a+2 is the same as that of the row scanning phase corresponding to the sub-pixel of row 2; and the timing of the row scanning phase corresponding to the sub-pixel of row 3a+3 is the same as that of the row scanning phase corresponding to the sub-pixel of row 3. These details will not be repeated here. Here, 'a' can take the values ​​1, 2, 3, 4, etc., which are integers.

[0075] Figure 12 and Figure 13 This illustrates that when n=3, the row scanning phases corresponding to the same row of sub-pixels have different timings in adjacent frames. This can also be achieved in other embodiments, such as... Figure 14 As shown, when n=3, the timing of the row scanning phase corresponding to the same row sub-pixel can also be the same in adjacent frames.

[0076] It should be noted that when the demultiplexer 20 includes 3 transistors, there are 6 possible arrangements of the conduction sequence of the 3 transistors. Figures 11 to 14 The diagram only illustrates three conduction sequences for three transistors and is not intended to limit this application.

[0077] In some embodiments, such as Figure 3As shown, the display panel 100 includes a plurality of pixel units 10a arranged in rows and columns, and each pixel unit 10a includes sub-pixels of various emitting colors. For example, each pixel unit 10a includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103 with different emitting colors. The pixel unit 10a is capable of emitting white light. The first sub-pixel 101 can be a red sub-pixel, the second sub-pixel 102 can be a green sub-pixel, and the third sub-pixel 103 can be a blue sub-pixel.

[0078] The display panel includes multiple circuit groups 20a, each circuit group 20a including multiple demultiplexers 20, and the circuit groups 20a are electrically connected to multiple pixel units 10a in the same row via data lines DL.

[0079] As an example, pixel unit 10a includes sub-pixels 10 with three emission colors, such as Figure 3 or Figure 15 As shown, demultiplexer 20 includes 2 transistors, and circuit group 20a includes 3 demultiplexers 20. Figure 3 and Figure 15 Only two columns of pixel units 10a and one circuit group 20a are shown in the diagram. The display panel may include multiple pixel units 10a and multiple circuit groups 20a arranged in the first direction X (row direction).

[0080] As another example, pixel unit 10a includes sub-pixels 10 with three emission colors, such as Figure 6 As shown, the demultiplexer 20 includes 3 transistors, and the circuit group 20a includes 3 demultiplexers 20. Figure 6 Only three columns of pixel units 10a and one circuit group 20a are shown in the diagram. The display panel may include multiple pixel units 10a and multiple circuit groups 20a arranged in the first direction X (row direction).

[0081] Within the same line scanning phase, the transistors in the circuit group 20a that electrically connects sub-pixels of the same emission color in different pixel units 10a have different turn-on sequences.

[0082] like Figure 3 As shown, the first sub-pixel 101 is connected to the first data line DL1, the second sub-pixel 102 is connected to the second data line DL2, and the third sub-pixel 103 is connected to the third data line DL3.

[0083] For example, two first sub-pixels 101 in two adjacent pixel units 10a in the same row, one of which is electrically connected to transistor M1 and the other is electrically connected to transistor M2, and the conduction order of transistor M1 and transistor M2 is different (they are turned on one after the other).

[0084] For example, such as Figure 3As shown, in two adjacent pixel units 10a in the same row, one of the two second sub-pixels 102 is electrically connected to transistor M2, and the other is electrically connected to transistor M1. The conduction order of transistors M1 and M2 is different (they are turned on one after the other). The same applies to the two transistors connected to the two third sub-pixels 103 in two adjacent pixel units 10a in the same row.

[0085] Figure 6 as well as Figure 15 The scheme shown can also achieve this goal, namely: within the same row scanning stage, the transistors in the circuit group 20a that electrically connects sub-pixels of the same emission color in different pixel units 10a have different conduction sequences, which will not be elaborated here.

[0086] In this embodiment, for sub-pixels of the same emission color in different pixel units, the circuit group transmits their corresponding data voltages to the data lines in different orders during the same row scanning phase. This is equivalent to disrupting the inherent pattern of the demultiplexer providing data voltages to sub-pixels of the same emission color during the same row scanning phase, thereby improving the problem of uneven display.

[0087] In some embodiments, such as Figure 3 As shown, the demultiplexer 20 is electrically connected to the sub-pixels 10 of two different luminous colors. For example, circuit group 20a includes three demultiplexers 20, each including two transistors. One circuit group 20a is electrically connected to two columns of pixel units 10a. One demultiplexer 20 is electrically connected to the first sub-pixel 101 and the second sub-pixel 102. Another demultiplexer 20 is electrically connected to the third sub-pixel 103 and the first sub-pixel 101. Yet another demultiplexer 20 is electrically connected to the second sub-pixel 102 and the third sub-pixel 103.

[0088] Corresponding to the real RGB pixel arrangement, the demultiplexer 20 is electrically connected to the sub-pixels 10 of the two emitting colors, which can avoid the connection line between the demultiplexer 20 and the data line DL from crossing, and can reduce signal interference.

[0089] In other embodiments, such as Figure 6 or Figure 15 As shown, the demultiplexer 20 is electrically connected to the sub-pixel 10 of the same luminous color.

[0090] For example, such as Figure 6 As shown, circuit group 20a includes three demultiplexers 20, each demultiplexer 20 including three transistors. One circuit group 20a is electrically connected to three columns of pixel units 10a. One demultiplexer 20 is electrically connected to three columns of first sub-pixels 101, another demultiplexer 20 is electrically connected to three columns of second sub-pixels 102, and yet another demultiplexer 20 is electrically connected to three columns of third sub-pixels 103.

[0091] Or, such as Figure 15 As shown, circuit group 20a includes three demultiplexers 20, each demultiplexer 20 including two transistors. One circuit group 20a is electrically connected to two columns of pixel units 10a. One demultiplexer 20 is electrically connected to two columns of first sub-pixels 101, another demultiplexer 20 is electrically connected to two columns of second sub-pixels 102, and yet another demultiplexer 20 is electrically connected to two columns of third sub-pixels 103.

[0092] In this embodiment, a demultiplexer 20 is used only to transmit data voltage to a sub-pixel of a single luminous color. Especially when displaying a solid color image, it can avoid voltage jumps transmitted by the demultiplexer 20, thereby saving power consumption.

[0093] For example, this application can be applied to real RGB pixel arrangement. Figure 3 , Figure 6 or Figure 15 As shown, the display panel includes multiple pixel units 10a, each pixel unit 10a including a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103 with different emission colors. The first sub-pixel 101 includes a first pixel circuit 111 and a first light-emitting element 121, the second sub-pixel 102 includes a second pixel circuit 112 and a second light-emitting element 122, and the third sub-pixel 103 includes a third pixel circuit 113 and a third light-emitting element 123.

[0094] The data line DL includes a first data line DL1, a second data line DL2, and a third data line DL3; the first data line DL1 is electrically connected to a plurality of first pixel circuits 111 in the same column; the second data line DL2 is electrically connected to a plurality of second pixel circuits 112 in the same column; and the third data line DL3 is electrically connected to a plurality of third pixel circuits 113 in the same column.

[0095] In this embodiment, the pixel arrangement is a real RGB pixel arrangement, which can achieve a truly high-resolution display.

[0096] It should also be noted that the accompanying drawings of this application use a real RGB pixel arrangement as an example, and the technical concept of this application can also be applied to other forms of pixel arrangement. For example, the technical concept of this application can also be applied to... Figure 1 The Diamond RGB pixel arrangement shown.

[0097] In some embodiments, in the same pixel unit 10a, the first light-emitting element 121 and the second light-emitting element 122 are arranged in the row direction (first direction X), and the third light-emitting element 123 is arranged in the column direction (second direction Y) relative to the first light-emitting element 121 and the second light-emitting element 122.

[0098] For example, among the three light-emitting elements, the third light-emitting element 123 has the largest area. For instance, the material lifespan of the third light-emitting element 123 is relatively short. Using a larger area for the third light-emitting element 123 can balance its short material lifespan, making the lifespans of the three light-emitting elements more consistent.

[0099] As an example, the structure of a pixel circuit can be as follows: Figure 16 As shown, the pixel circuit includes a power writing transistor M11, a data writing transistor M12, a driving transistor M13, a threshold compensation transistor M14, a gate reset transistor M15, a light-emitting control transistor M16, an anode reset transistor M17, and a storage capacitor Cst. The connection relationships of each device are shown in [reference needed]. Figure 16 In this context, Vref1 represents the first reset signal line, Vref2 represents the second reset signal line, scan1 and scan2 represent scan signal lines, Emit represents the light emission control signal line, PVDD represents the power signal line, PVEE represents the common signal line, and DL represents the data line.

[0100] Please refer to the reference. Figure 16 and Figure 17 The operation of the pixel circuit includes a reset phase (c1), a data writing phase (c2), and a light emission phase (c3). During the reset phase c1, the gate reset transistor M15 is turned on, and the first reset signal on the first reset signal line Vref1 resets the gate of the drive transistor M13. The anode reset transistor M17 is turned on, and the second reset signal on the second reset signal line Vref2 resets the anode of the light-emitting element 12.

[0101] During the data writing phase c2, the scan signal scan2 controls the data writing transistor M12 and the threshold compensation transistor M14 to turn on. The data voltage on the data line DL is written to the gate of the driving transistor M13 and compensates the threshold voltage of the driving transistor M13.

[0102] During the light-emitting stage c3, the power writing transistor M11, the driving transistor M13, and the light-emitting control transistor M16 are turned on. The driving transistor M13 generates a driving current, which drives the light-emitting element 12 to emit light.

[0103] Figure 16 and Figure 17 These are merely examples and are not intended to limit this application. The technical concepts of this application can also be applied to pixel circuits with other structures.

[0104] Based on the same technical concept, this application also provides a driving method for a display panel, used to drive the display panel described in any of the above embodiments, wherein the display panel includes: a plurality of sub-pixels; a plurality of data lines, the data lines being electrically connected to the sub-pixels; a demultiplexer including n transistors, wherein the first terminals of the n transistors in the same demultiplexer are all electrically connected to the same data signal terminal, and the second terminals of the n transistors in the same demultiplexer are electrically connected to the n data lines one-to-one, where n is an integer greater than 1.

[0105] The driving methods include: In the first time period, the turn-on sequence of n transistors in the same demultiplexer is the first sequence; In the second time period, the turn-on sequence of the n transistors in the same demultiplexer is the second sequence, which is different from the first sequence.

[0106] In this embodiment, the demultiplexer 20 includes n transistors. During a first time period t1 and a second time period t2, by controlling the conduction sequence of the n transistors in the same demultiplexer 20 to be different, the order in which the demultiplexer 20 writes data voltages to the n connected data lines DL is also different. Figure 2 The multiple transistors of the demultiplexer shown in the application have the same turn-on sequence at different times. The embodiment of this application is equivalent to disrupting the inherent pattern of the demultiplexer writing data voltage to the data line DL. Even if a display mura occurs, the display mura is no longer constant. For example, it can avoid the same display mura from always appearing in the same position or the display mura always appearing in the same position, so that the human eye cannot recognize the display mura, thereby improving the problem of uneven display on the display panel.

[0107] In some embodiments, the driving method further includes: controlling a first time period and a second time period within the same frame.

[0108] In some embodiments, the same data line is electrically connected to sub-pixels of the same emitting color; The driving method also includes controlling a frame to include multiple line scanning stages, the i-th line scanning stage including a first time period, the (i+1)-th line scanning stage including a second time period, where i is an integer greater than or equal to 1.

[0109] In some embodiments, the driving method further includes: controlling the operation of the demultiplexer within the same frame to include a plurality of first conduction cycles, each first conduction cycle including a first time period and a second time period.

[0110] In some embodiments, n=2, and the first conduction cycle includes two row scan phases.

[0111] In some embodiments, n=3, and the first conduction cycle includes 3 row scan phases.

[0112] In some embodiments, the driving method further includes: controlling a row scan phase of the first conduction cycle to include a third time period, in which the conduction sequence of n transistors in the same demultiplexer is a third sequence, and the first sequence, second sequence, and third sequence are all different.

[0113] In some embodiments, the driving method further includes: a frame comprising multiple line scanning phases; The control of the k-th line scanning phase of frame j includes a first time period, and the control of the k-th line scanning phase of frame m includes a second time period, where j and k are both integers greater than or equal to 1.

[0114] In some embodiments, the j-th frame and the m-th frame are controlled to be two adjacent frames.

[0115] In some embodiments, the driving method further includes: controlling the operation of the demultiplexer to include a second conduction cycle, the second conduction cycle including multiple frames, and each second conduction cycle including a first time period and a second time period.

[0116] In some embodiments, n=2, and the second conduction period includes two frames.

[0117] In some embodiments, n=3, and the second conduction period includes 3 frames.

[0118] In some embodiments, the driving method further includes: controlling a frame of the second conduction cycle to include a third time period, in which the conduction sequence of n transistors in the same demultiplexer is a third sequence, and the first sequence, second sequence, and third sequence are all different.

[0119] In some embodiments, the display panel includes a plurality of pixel units arranged in rows and columns, and the pixel units include sub-pixels of a plurality of luminous colors; The display panel includes multiple circuit groups, each circuit group includes multiple demultiplexers, and the circuit groups are electrically connected to multiple pixel units in the same row. The driving method also includes: within the same line scanning phase, controlling the different turn-on sequences of transistors in the circuit group that controls the electrical connection of sub-pixels of the same emission color in different pixel units.

[0120] In some embodiments, the pixel unit includes sub-pixels of three emission colors; n=2 or n=3, and the circuit group includes three demultiplexers.

[0121] In some embodiments, the demultiplexer is electrically connected to sub-pixels of two different luminous colors.

[0122] In some embodiments, the demultiplexer is electrically connected to sub-pixels of the same emission color.

[0123] In some embodiments, the display panel includes a plurality of pixel units, and the pixel units include a first sub-pixel, a second sub-pixel, and a third sub-pixel with different emission colors; The first sub-pixel includes a first pixel circuit and a first light-emitting element; the second sub-pixel includes a second pixel circuit and a second light-emitting element; and the third sub-pixel includes a third pixel circuit and a third light-emitting element. The data cable includes a first data cable, a second data cable, and a third data cable; The first data line is electrically connected to multiple first pixel circuits in the same column; The second data line is electrically connected to multiple second pixel circuits in the same column; The third data line is electrically connected to multiple third pixel circuits in the same column.

[0124] In some embodiments, in the same pixel unit, the first light-emitting element and the second light-emitting element are arranged in the row direction, and the third light-emitting element is arranged in the column direction relative to the first light-emitting element and the second light-emitting element.

[0125] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 18 , Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 18 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 18 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0126] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels; Multiple data lines, wherein the data lines are electrically connected to the sub-pixel; A demultiplexer includes n transistors. The first terminals of the n transistors in the same demultiplexer are all electrically connected to the same data signal terminal, and the second terminals of the n transistors in the same demultiplexer are electrically connected to the n data lines one by one, where n is an integer greater than 1. In the first time period, the conduction sequence of the n transistors in the same demultiplexer is a first sequence, and in the second time period, the conduction sequence of the n transistors in the same demultiplexer is a second sequence, wherein the first sequence is different from the second sequence.

2. The display panel according to claim 1, characterized in that, The same frame includes both the first time period and the second time period.

3. The display panel according to claim 2, characterized in that, The same data line is used to electrically connect the sub-pixels of the same luminous color; A frame includes multiple line scanning stages, the i-th line scanning stage includes the first time period, the (i+1)-th line scanning stage includes the second time period, and i is an integer greater than or equal to 1.

4. The display panel according to claim 3, characterized in that, The demultiplexer's operation within the same frame includes multiple first conduction cycles, each of which includes a first time period and a second time period.

5. The display panel according to claim 4, characterized in that, n=2, and the first conduction cycle includes two row scanning phases.

6. The display panel according to claim 4, characterized in that, n=3, and the first conduction cycle includes 3 row scanning phases.

7. The display panel according to claim 6, characterized in that, One row scan phase of the first conduction cycle includes a third time period, in which the conduction sequence of n transistors in the same demultiplexer is a third sequence, wherein the first sequence, the second sequence, and the third sequence are all different.

8. The display panel according to claim 1, characterized in that, A frame consists of multiple line scanning stages; The k-th line scanning phase of the j-th frame includes the first time period, and the k-th line scanning phase of the m-th frame includes the second time period, where j and k are both integers greater than or equal to 1.

9. The display panel according to claim 8, characterized in that, The j-th frame and the m-th frame are two adjacent frames.

10. The display panel according to claim 9, characterized in that, The demultiplexer operates by including a second conduction cycle, which includes multiple frames. Each second conduction cycle includes the first time period and the second time period.

11. The display panel according to claim 10, characterized in that, n=2, and the second conduction period includes two frames.

12. The display panel according to claim 10, characterized in that, n=3, and the second conduction period includes 3 frames.

13. The display panel according to claim 12, characterized in that, A frame of the second conduction cycle includes a third time period, in which the conduction sequence of n transistors in the same demultiplexer is a third sequence, and the first sequence, the second sequence, and the third sequence are all different.

14. The display panel according to claim 1, characterized in that, The display panel includes multiple pixel units arranged in rows and columns, and each pixel unit includes sub-pixels with multiple luminous colors; The display panel includes multiple circuit groups, each circuit group including multiple demultiplexers, and each circuit group is electrically connected to multiple pixel units in the same row. Within the same row scanning phase, the transistors in the circuit group electrically connected to sub-pixels of the same emission color in different pixel units have different turn-on sequences.

15. The display panel according to claim 14, characterized in that, The pixel unit includes sub-pixels of three luminous colors; n=2 or n=3, and the circuit group includes three of the demultiplexers.

16. The display panel according to claim 1, characterized in that, The demultiplexer is electrically connected to the sub-pixels of the two luminous colors.

17. The display panel according to claim 1, characterized in that, The demultiplexer is electrically connected to the sub-pixels of the same luminous color.

18. The display panel according to claim 1, characterized in that, The display panel includes multiple pixel units, and each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel with different emitting colors; The first sub-pixel includes a first pixel circuit and a first light-emitting element, the second sub-pixel includes a second pixel circuit and a second light-emitting element, and the third sub-pixel includes a third pixel circuit and a third light-emitting element; The data lines include a first data line, a second data line, and a third data line; The first data line is electrically connected to multiple first pixel circuits in the same column; The second data line is electrically connected to multiple second pixel circuits in the same column; The third data line is electrically connected to multiple third pixel circuits in the same column.

19. The display panel according to claim 18, characterized in that, In the same pixel unit, the first light-emitting element and the second light-emitting element are arranged in the row direction, and the third light-emitting element is arranged in the column direction relative to the first light-emitting element and the second light-emitting element.

20. A driving method for a display panel, characterized in that, For driving a display panel, the display panel includes: Multiple sub-pixels; Multiple data lines, wherein the data lines are electrically connected to the sub-pixel; A demultiplexer includes n transistors. The first terminals of the n transistors in the same demultiplexer are all electrically connected to the same data signal terminal, and the second terminals of the n transistors in the same demultiplexer are electrically connected to the n data lines one by one, where n is an integer greater than 1. The driving method includes: In the first time period, the turn-on sequence of the n transistors in the same demultiplexer is the first sequence; In the second time period, the turn-on sequence of the n transistors in the same demultiplexer is a second sequence, which is different from the first sequence.

21. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 19.

Images