Duty cycle monitoring circuit and semiconductor device using it

Abstract

This application discloses a duty cycle monitoring circuit and a semiconductor device using the same. The duty cycle monitoring circuit includes a duty cycle reduction circuit, a duty cycle detection circuit, and a latching circuit. The duty cycle reduction circuit reduces the duty cycle of a first clock signal and a second clock signal to generate a first input signal and a second input signal. The duty cycle detection circuit detects the duty cycle of the first input signal and the second input signal to generate a first output signal and a second output signal. The latching circuit generates a duty cycle detection signal based on the first output signal and the second output signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0169687, filed with the Korean Intellectual Property Office on November 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to integrated circuit technology, including but not limited to duty cycle monitoring circuits and semiconductor devices using duty cycle monitoring circuits. Background Technology

[0004] Electronic devices include many electronic components, and computer systems include many semiconductor devices, which are semiconductor components. The semiconductor devices included in a computer system communicate with each other by sending and receiving system clock signals and data signals. The semiconductor devices operate in synchronization with the clock signal. As the operating speed of the computer system and the frequency of the system clock signal increase, the pulse width of the system clock signal decreases, and the setup and hold margins required to synchronize the data signals with the system clock signal decrease.

[0005] Semiconductor devices can sample data signals synchronously with a system clock signal or by generating an internal clock signal through delaying or dividing the system clock signal. The duty cycle of either the system clock signal or the internal clock signal must be kept consistent to produce accurately sampled data signals. When the duty cycle fluctuates, the setup and hold margins for sampling the data signal may change, potentially causing malfunctions and reliability issues in the semiconductor device. Summary of the Invention

[0006] In one embodiment, a duty cycle monitoring circuit may include a duty cycle reduction circuit, a duty cycle detection circuit, and a latching circuit. The duty cycle reduction circuit may be configured to: receive a first clock signal and a second clock signal; reduce the duty cycle of the first clock signal by an amount to generate a first input signal; and reduce the duty cycle of the second clock signal by the same amount to generate a second input signal. The duty cycle detection circuit may be configured to detect the duty cycle of the first input signal and the duty cycle of the second input signal to generate a first output signal and a second output signal. The latching circuit may be configured to generate a duty cycle detection signal when one of the first output signal and the second output signal reaches a trigger voltage.

[0007] In one embodiment, a duty cycle monitoring circuit may include a clock chopper circuit, a duty cycle reduction circuit, a duty cycle monitoring circuit, and a latch circuit. The clock chopper circuit may be configured to receive a first clock signal and a second clock signal, and based on a toggle signal, output the first of the first and second clock signals as a first selected clock signal and output the second of the first and second clock signals as a second selected clock signal. The duty cycle reduction circuit may be configured to reduce the duty cycle of the first and second selected clock signals by an amount to generate a first input signal and a second input signal. The duty cycle detection circuit may be configured to detect the duty cycle of the first and second input signals to generate a first output signal and a second output signal. The latch circuit may be configured to generate a duty cycle detection signal based on the first and second output signals.

[0008] In one embodiment, a semiconductor device may include a gating receiver circuit, a first duty cycle adjustment circuit, a data receiving circuit, and a duty cycle monitoring circuit. The gating receiver circuit may be configured to receive a first gating signal and a second gating signal from an external device. The first duty cycle adjustment circuit may be configured to adjust the duty cycle of the first gating signal and the duty cycle of the second gating signal based on a first duty cycle control signal to generate a first internal gating signal and a second internal gating signal, respectively. The data receiving circuit may be configured to receive data synchronously with the first internal gating signal and the second internal gating signal. The duty cycle monitoring circuit may be configured to reduce the duty cycle of the first internal gating signal and the second internal gating signal by an amount to generate a first input signal and a second input signal, and to detect the duty cycle of the first input signal and the second input signal to generate a duty cycle detection signal. The first duty cycle control signal may be generated based on the duty cycle detection signal.

[0009] In one embodiment, a method may include reducing the duty cycle of a first clock signal by an amount to generate a first input signal, reducing the duty cycle of a second clock signal by the same amount to generate a second input signal; generating a first output signal based on the duty cycle of the first input signal, generating a second output signal based on the duty cycle of the second input signal; and generating a duty cycle detection signal when one of the first output signal and the second output signal reaches a trigger voltage. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating the configuration of a duty cycle monitoring circuit according to one embodiment.

[0011] Figure 2 This is a timing diagram of the operation period of a duty cycle monitoring circuit according to one embodiment.

[0012] Figure 3 This is a diagram illustrating the configuration of a duty cycle monitoring circuit according to one embodiment.

[0013] Figure 4A This is a diagram illustrating the configuration of a reduction circuit according to one embodiment.

[0014] Figure 4B This is a diagram illustrating a buffer of a reduction circuit according to one embodiment.

[0015] Figure 4C This is a timing diagram of the operation period of a duty cycle reduction circuit according to one embodiment.

[0016] Figure 5 This is a timing diagram of the operation period of a duty cycle monitoring circuit according to one embodiment.

[0017] Figure 6A This is a diagram illustrating the configuration of a reduction circuit according to one embodiment.

[0018] Figure 6B This is a timing diagram illustrating the operation of a duty cycle reduction circuit according to one embodiment.

[0019] Figure 7 This is a timing diagram of the operation period of a duty cycle monitoring circuit according to one embodiment.

[0020] Figure 8 This is a diagram illustrating the configuration of a duty cycle monitoring circuit according to one embodiment.

[0021] Figure 9 This is a diagram illustrating the configuration of a semiconductor device according to one embodiment.

[0022] Figure 10 This is a timing diagram of the operation of a semiconductor device according to an embodiment.

[0023] Figure 11 This is a diagram illustrating the configuration of a semiconductor system according to one embodiment. Detailed Implementation

[0024] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples illustrating the concepts disclosed in this application. Examples or embodiments of the concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0025] When one element is identified as "coupled" to another element, these elements can be directly coupled or coupled through at least one intermediary element between the elements. When two elements are identified as "directly coupled," one element is directly coupled to the other element, and there is no intermediary element between the two elements.

[0026] Semiconductor devices detect the duty cycle of an internal clock signal and adjust the duty cycle of the internal clock signal when duty cycle distortion exists, thereby improving the operation of the semiconductor device.

[0027] Figure 1 This is a diagram illustrating the configuration of a duty cycle monitoring circuit 100 according to one embodiment. (See reference) Figure 1 The duty cycle monitoring circuit 100 receives a first clock signal CLK1 and a second clock signal CLK2, and generates a duty cycle detection signal DOUT based on the clock signals CLK1 and CLK2. The duty cycle monitoring circuit 100 generates the duty cycle detection signal DOUT by comparing the duty cycle of the first clock signal CLK1 with the duty cycle of the second clock signal CLK2. For example, the duty cycle monitoring circuit 100 generates the duty cycle detection signal DOUT by detecting the duty cycle of the first clock signal CLK1 relative to the duty cycle of the second clock signal CLK2. The second clock signal CLK2 can be a complementary clock signal with a phase opposite to that of the first clock signal CLK1. When the duty cycle of the first clock signal CLK1 is greater than the duty cycle of the second clock signal CLK2, the duty cycle monitoring circuit 100 can generate the duty cycle detection signal DOUT at a first logic level. When the duty cycle of the first clock signal CLK1 is less than the duty cycle of the second clock signal CLK2, the duty cycle monitoring circuit 100 can generate the duty cycle detection signal DOUT at a second logic level.

[0028] The duty cycle monitoring circuit 100 includes a duty cycle detection circuit 110 and a latching circuit 120. The duty cycle detection circuit 110 receives clock signals CLK1 and CLK2, generates a first output signal OUT1 and a second output signal OUT2, and detects the duty cycles of clock signals CLK1 and CLK2. The duty cycle detection circuit 110 generates the first output signal OUT1 based on the duty cycle of the first clock signal CLK1. The duty cycle detection circuit 110 generates the second output signal OUT2 based on the duty cycle of the second clock signal CLK2. The duty cycle detection circuit 110 generates a first output signal OUT1 at a lower voltage level as the duty cycle of the first clock signal CLK1 increases, and generates a first output signal OUT1 at a higher voltage level as the duty cycle of the first clock signal CLK1 decreases. The duty cycle detection circuit 110 generates a second output signal OUT2 at a lower voltage level as the duty cycle of the second clock signal CLK2 increases, and generates a second output signal OUT2 at a higher voltage level as the duty cycle of the second clock signal CLK2 decreases. When the duty cycle of the first clock signal CLK1 is greater than the duty cycle of the second clock signal CLK2, the duty cycle detection circuit 110 generates a first output signal OUT1 with a voltage level lower than that of the second output signal OUT2. When the duty cycle of the first clock signal CLK1 is less than the duty cycle of the second clock signal CLK2, the duty cycle detection circuit 110 generates a first output signal OUT1 with a voltage level higher than that of the second output signal OUT2. The duty cycle detection circuit 110 provides output signals OUT1 and OUT2 to the latch circuit 120.

[0029] Latch circuit 120 receives output signals OUT1 and OUT2, and generates a duty cycle detection signal DOUT based on OUT1 and OUT2. Latch circuit 120 generates duty cycle detection signal DOUT when either output signal OUT1 or OUT2 reaches a trigger voltage. For example, when the first output signal OUT1 drops to the trigger voltage before the second output signal OUT2 reaches the trigger voltage, latch circuit 120 generates a duty cycle detection signal DOUT at a first logic level. When the second output signal OUT2 drops to the trigger voltage before the first output signal OUT1 reaches the trigger voltage, latch circuit 120 generates a duty cycle detection signal DOUT at a second logic level. The trigger voltage can be one of several voltage levels. For example, the trigger voltage may be 50% or less of the maximum voltage level corresponding to either output signal OUT1 or OUT2, but is not limited to this example. In this example, latch circuit 120 includes a Schmitt trigger latch circuit configured to adjust the voltage level of the trigger voltage and trigger the logic level of duty cycle detection signal DOUT when one of the output signals OUT1 or OUT2 reaches the voltage level of the trigger voltage.

[0030] The duty cycle detection circuit 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Transistors T1 and T2 can both be P-channel metal-oxide-semiconductor (MOS) transistors. The gate of the first transistor T1 receives the precharge signal PCGB. The source of the first transistor T1 is electrically coupled to a terminal supplied with a first power supply voltage V1. The drain of the first transistor T1 is electrically coupled to a first output node ON1. A first output signal OUT1 can be output from the first output node ON1. The gate of the second transistor T2 receives the precharge signal PCGB. The source of the second transistor T2 is electrically coupled to a terminal supplied with the first power supply voltage V1. The drain of the second transistor T2 is electrically coupled to a second output node ON2. A second output signal OUT2 is output at the second output node ON2. The maximum voltage levels of output signals OUT1 and OUT2 can be substantially the same as the voltage level of the first power supply voltage V1. Transistors T3, T4, and T5 can all be N-channel MOS transistors. The gate of the third transistor T3 receives the first clock signal CLK1. The drain of the third transistor T3 is electrically coupled to the first output node ON1. The source of the third transistor T3 is electrically coupled to the common node CN. The gate of the fourth transistor T4 receives the second clock signal CLK2. The drain of the fourth transistor T4 is electrically coupled to the second output node ON2. The source of the fourth transistor T4 is electrically coupled to the common node CN. The gate of the fifth transistor T5 can receive the precharge signal PCGB. The drain of the fifth transistor T5 is electrically coupled to the common node CN. The source of the fifth transistor T5 is electrically coupled to the terminal supplied with the second power supply voltage V2. The second power supply voltage V2 is at a voltage level lower than the first power supply voltage V1. One end of the first capacitor C1 is electrically coupled to the first output node ON1. The other end of the first capacitor C1 is electrically coupled to the terminal supplied with the second power supply voltage V2. One end of the second capacitor C2 is electrically coupled to the second output node ON2. The other end of the second capacitor C2 is electrically coupled to the terminal supplied with the second power supply voltage V2. The duty cycle detection circuit 110 generates a first output signal OUT1 by discharging a first capacitor C1 electrically coupled to the first output node ON1 within the pulse width corresponding to the first clock signal CLK1. The duty cycle detection circuit 110 generates a second output signal OUT2 by discharging a second capacitor C2 electrically coupled to the second output node ON2 within the pulse width corresponding to the second clock signal CLK2.

[0031] When the precharge signal PCGB is enabled at a low logic level, transistors T1 and T2 are turned on, and transistors T3, T4, and T5 are turned off. The first transistor T1 supplies the first power supply voltage V1 to the first output node ON1, and the second transistor T2 supplies the first power supply voltage V1 to the second output node ON2. As the first power supply voltage V1 is supplied to output nodes ON1 and ON2, capacitors C1 and C2 are charged. Output nodes ON1 and ON2 are precharged at a voltage level corresponding to the voltage level of the first power supply voltage V1. When the precharge signal PCGB is disabled at a high logic level, transistors T1 and T2 are turned off, and transistors T3, T4, and T5 are turned on. The fifth transistor T5 activates the current path from the common node CN to the terminal supplied with the second power supply voltage V2. During each cycle of the first clock signal CLK1, the third transistor T3 sinks current from the first output node ON1 to the common node CN during the period when the pulse of the first clock signal CLK1 is enabled, thereby discharging the first capacitor C1 and reducing the voltage level of the first output node ON1. During each cycle of the second clock signal CLK2, the fourth transistor T4 sinks current from the second output node ON2 to the common node CN during the period when the pulse of the second clock signal CLK2 is enabled, thereby discharging the second capacitor C2 and reducing the voltage level of the second output node ON2.

[0032] The duty cycle detection circuit 110 includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. Transistors T6 and T7 can both be P-channel MOS transistors. The sixth transistor T6 is electrically coupled between the first output node ON1 and the third transistor T3. The gate of the sixth transistor T6 receives the enable signal EN. The drain of the sixth transistor T6 is electrically coupled to the first output node ON1. The source of the sixth transistor T6 is electrically coupled to the drain of the third transistor T3. The seventh transistor T7 is electrically coupled between the second output node ON2 and the fourth transistor T4. The gate of the seventh transistor T7 receives the enable signal EN. The drain of the seventh transistor T7 is electrically coupled to the second output node ON2. The source of the seventh transistor T7 is electrically coupled to the drain of the fourth transistor T4. When the enable signal EN is disabled at a low logic level, transistors T6 and T7 are electrically coupled to output nodes ON1 and ON2 to balance the voltage levels of output nodes ON1 and ON2, respectively. When the enable signal EN is enabled at a high logic level, transistors T6 and T7 electrically decouple output nodes ON1 and ON2. The eighth transistor T8 may be an N-channel MOS transistor. The eighth transistor T8 is electrically coupled between the common node CN and the fifth transistor T5. The gate of the eighth transistor T8 receives the enable signal EN. The drain of the eighth transistor T8 is electrically coupled to the common node CN. The source of the eighth transistor T8 is electrically coupled to the drain of the fifth transistor T5. When the enable signal EN is enabled, the eighth transistor T8 activates the current path between the common node CN and the fifth transistor T5. In one embodiment, the eighth transistor T8 is electrically coupled between the fifth transistor T5 and the terminal supplied with the second power supply voltage V2. The enable signal EN is a signal that enables or triggers the duty cycle monitoring circuit 100 to perform a duty cycle monitoring operation. The enable signal EN remains enabled throughout the entire period during which the duty cycle monitoring circuit 100 performs the duty cycle monitoring operation. When the enable signal EN is enabled, the precharge signal PCGB is enabled for a predetermined time period. The precharge signal PCGB is disabled after a predetermined time period. The predetermined time period can be sufficient to charge capacitors C1 and C2 to a voltage level corresponding to the voltage level of the first power supply voltage V1. In one embodiment, the precharge signal PCGB is periodically enabled while the enable signal EN remains enabled. For example, the precharge signal PCGB is enabled again after a sufficient time has elapsed following the generation of the duty cycle detection signal DOUT by the latch circuit 120.

[0033] Figure 2 This is a timing diagram showing the operation of a duty cycle monitoring circuit 100 according to one embodiment. (Reference) Figure 1 and Figure 2 The operation of a duty cycle monitoring circuit 100 according to one embodiment is described. Figure 2The vertical axis of the graph shown represents voltage V. Capacitors C1 and C2 are in a pre-charge state, and the voltage levels of output signals OUT1 and OUT2 are at the voltage level of the first power supply voltage V1. Figure 2In this clock signal, the duty cycle of the second clock signal CLK2 is greater than that of the first clock signal CLK1. During the first cycle of clock signals CLK1 and CLK2, the voltage levels of output signals OUT1 and OUT2 decrease according to the pulse widths of clock signals CLK1 and CLK2, respectively. Because the pulse width of the second clock signal CLK2 is greater than that of the first clock signal CLK1, the voltage level of the second output signal OUT2 is lower than that of the first output signal OUT1. For example, the second output signal OUT2 has a voltage level α lower than that of the first output signal OUT1. With each cycle of clock signals CLK1 and CLK2, the voltage level difference between the second output signal OUT2 and the first output signal OUT1 increases by a multiple of the number of cycles elapsed. During the second cycle of clock signals CLK1 and CLK2, the voltage level difference between output signals OUT1 and OUT2 is 2α. When the third cycle of clock signals CLK1 and CLK2 has elapsed, the voltage level difference between output signals OUT1 and OUT2 is 3α. When the (n-1)th cycle of clock signals CLK1 and CLK2 has elapsed, the voltage level difference between output signals OUT1 and OUT2 is (n-1)α. When the nth cycle of clock signals CLK1 and CLK2 has elapsed, the voltage level difference between output signals OUT1 and OUT2 is nα. For example, n is an integer greater than or equal to 5. When the nth cycle of clock signals CLK1 and CLK2 has elapsed, the voltage level of the second output signal OUT2 decreases to be equal to or lower than the trigger voltage Vth. The latch circuit 120 detects that the voltage level of the second output signal OUT2 has decreased to be equal to or lower than the trigger voltage Vth, and the logic level of the trigger duty cycle detection signal DOUT is at the active level. The latch circuit 120 outputs a duty cycle detection signal DOUT in the RESET state, and outputs a duty cycle detection signal DOUT at the second logic level when the voltage level of the second output signal OUT2 is lower than the voltage level of the trigger voltage Vth. When the duty cycles of clock signals CLK1 and CLK2 are relatively large, the duty cycle monitoring circuit 100 may not be able to accurately generate the duty cycle detection signal DOUT, and the difference between the duty cycles of clock signals CLK1 and CLK2 may not be significant. When the frequencies of clock signals CLK1 and CLK2 are relatively low, the duty cycle monitoring circuit 100 may not be able to accurately generate the duty cycle detection signal DOUT.Because the second clock signal CLK2 has a phase opposite to that of the first clock signal CLK1, the voltage level of the first output signal OUT1 decreases first according to the pulse width of the first clock signal CLK1 during the first half of a period. During the second half of the period, the voltage level of the second output signal OUT2 decreases according to the pulse width of the second clock signal CLK2. When both clock signals CLK1 and CLK2 have relatively large duty cycles and the difference between their duty cycles is not significant (e.g., when the duty cycle of the second clock signal CLK2 is slightly larger than that of the first clock signal CLK1), the first output signal OUT1 reaches the trigger voltage Vth before the second output signal OUT2. Due to an offset in the latch circuit 120, a fault may occur during the period when the first output signal OUT1 reaches the trigger voltage Vth before the second output signal OUT2. When the duty cycles of both clock signals CLK1 and CLK2 are too large, or when the frequency is too low, the pulse widths of clock signals CLK1 and CLK2 increase. Therefore, one of the output signals OUT1 and OUT2 reaches the trigger voltage, but there is no significant voltage level difference between them. To prevent this fault, the duty cycle of clock signal CLK1 and the duty cycle of clock signal CLK2 are reduced before performing the duty cycle monitoring operation.

[0034] Figure 3 This is a diagram illustrating the configuration of a duty cycle monitoring circuit 200 according to one embodiment. (See reference) Figure 3 The duty cycle monitoring circuit 200 receives a first clock signal CLK1 and a second clock signal CLK2, and generates a duty cycle detection signal DOUT by comparing the duty cycles of clock signals CLK1 and CLK2. The second clock signal CLK2 can be a complementary clock signal with a phase opposite to that of the first clock signal CLK1. The duty cycle monitoring circuit 200 reduces the duty cycles of both clock signals CLK1 and CLK2 by the same amount of time, and can accurately generate the duty cycle detection signal DOUT by comparing the duty cycles of the clock signals with the reduced duty cycles. The duty cycle monitoring circuit 200 includes a duty cycle reduction circuit 230, a duty cycle detection circuit 210, and a latching circuit 220.

[0035] The duty cycle reduction circuit 230 receives clock signals CLK1 and CLK2, and generates a first input signal IN1 and a second input signal IN2. The duty cycle reduction circuit 230 generates input signals IN1 and IN2 by reducing the duty cycle of each clock signal CLK1 and clock signal CLK2 by the same time period. The duty cycle reduction circuit 230 reduces the pulse width of clock signals CLK1 and CLK2 by the same time period, thereby reducing the duty cycle of clock signals CLK1 and CLK2. The duty cycle reduction circuit 230 generates the first input signal IN1 by reducing the duty cycle of the first clock signal CLK1 by a predetermined amount, such that the first input signal IN1 has a duty cycle reduced by the predetermined amount compared to the duty cycle of the first clock signal CLK1. The duty cycle reduction circuit 230 generates the second input signal IN2 by reducing the duty cycle of the second clock signal CLK2 by a predetermined amount, such that the second input signal IN2 has a duty cycle reduced by the predetermined amount compared to the duty cycle of the second clock signal CLK2. The predetermined quantity can have a variety of different values, which can vary based on control signals, for example, as per [the control signal]. Figure 4B , Figure 6A or Figure 9 Described.

[0036] The duty cycle reduction circuit 230 includes a first reduction circuit 231 and a second reduction circuit 232. The first reduction circuit 231 receives a first clock signal CLK1 and generates a first input signal IN1 by reducing the duty cycle of the first clock signal CLK1 by a predetermined amount. The first reduction circuit 231 adjusts the pulse width of the first clock signal CLK1 to generate a first input signal IN1 with a duty cycle different from that of the first clock signal CLK1. The first reduction circuit 231 further reduces the pulse width of the first clock signal CLK1 to generate a first input signal IN1 with a duty cycle smaller than that of the first clock signal CLK1. The second reduction circuit 232 receives a second clock signal CLK2 and generates a second input signal IN2 by reducing the duty cycle of the second clock signal CLK2 by a predetermined amount. The second reduction circuit 232 adjusts the pulse width of the second clock signal CLK2 to generate a second input signal IN2 with a duty cycle different from that of the second clock signal CLK2. The second reduction circuit 232 reduces the pulse width of the second clock signal CLK2 to generate a second input signal IN2 with a duty cycle smaller than that of the second clock signal CLK2. The duty cycle reduction circuit 230 provides input signals IN1 and IN2 to the duty cycle detection circuit 210.

[0037] The duty cycle detection circuit 210 receives input signals IN1 and IN2, and generates a first output signal OUT1 and a second output signal OUT2 by comparing the duty cycles of input signals IN1 and IN2. The duty cycle detection circuit 210 may have... Figure 1 The duty cycle detection circuit 110 shown in the diagram has a configuration that is substantially similar to the one described above, and can perform substantially the same function. The latch circuit 220 receives output signals OUT1 and OUT2, and generates a duty cycle detection signal DOUT. The latch circuit 220 may have a configuration similar to the one described above. Figure 1 The latch circuit 120 shown in the figure has a basically similar configuration and can perform basically the same functions.

[0038] Figure 4A This is a diagram illustrating the configuration of a reduction circuit 300 according to one embodiment. (See reference) Figure 4A The reduction circuit 300 includes at least a first buffer circuit 310. For example... Figure 4B As shown, the first buffer circuit 310 generates the input signal IN by buffering the clock signal CLK. The threshold voltage of the first buffer circuit 310 is at a voltage level higher than the midpoint of the swing range of the clock signal CLK. The first buffer circuit 310 uses the threshold voltage, which is higher than the midpoint voltage, to generate the input signal IN with a pulse width reduced compared to the pulse width of the clock signal CLK. The reduction circuit 300 includes a second buffer circuit 320, a third buffer circuit 330, and a fourth buffer circuit 340. The second buffer circuit 320 is configured as the preceding stage of the first buffer circuit 310, while the buffer circuits 330 and 340 are sequentially configured as the following stages of the first buffer circuit 310. The threshold voltages of the buffer circuits 320, 330, and 340 are at a voltage level substantially similar to the midpoint voltage. Therefore, the buffer circuits 320, 330, and 340 generate an output signal with the same duty cycle characteristics as the input signal. The second buffer circuit 320 receives the clock signal CLK and buffers the clock signal CLK. The output signal of the second buffer circuit 320 has a duty cycle that is substantially the same as that of the clock signal CLK. The first buffer circuit 310 receives the output signal of the second buffer circuit 320 and generates an output signal with a reduced duty cycle compared to the output signal of the second buffer circuit 320. The third buffer circuit 330 receives the output signal of the first buffer circuit 310 and generates an output signal with a duty cycle substantially similar to that of the output signal of the first buffer circuit 310. The fourth buffer circuit 340 receives the output signal of the third buffer circuit 330 and generates an input signal IN with a duty cycle substantially similar to that of the output signal of the third buffer circuit 330. Although... Figure 4AThe first buffer circuit 310 is shown in the second stage of the reduction circuit 300, but the first buffer circuit 310 can be located in any stage from the first to the fourth stage.

[0039] refer to Figure 4B The first buffer circuit 310 includes a first inverter 311, a second inverter 312, and a threshold voltage regulator 313. The first buffer circuit 310 receives a first power supply voltage V1 and a second power supply voltage V2, and operates using both power supply voltages V1 and V2. Power supply voltages V1 and V2 can be used with… Figure 1The power supply voltages V1 and V2 are essentially the same. The first inverter 311 receives the buffer input signal BIN (i.e., the output signal of the second buffer circuit 320), inverts the buffer input signal BIN, and outputs an inverted signal IV at the first node ND1. The second inverter 312 receives the inverted signal IV, inverts the inverted signal IV, and outputs the buffer output signal BOUT (i.e., the output signal of the first buffer circuit 310) at the second node ND2. The threshold voltage regulator 313 receives the inverted signal IV and the threshold control signal NC. The threshold voltage regulator 313 pulls down the voltage at the second node ND2 based on the inverted signal IV and the threshold control signal NC. The threshold voltage regulator 313 adjusts the driving strength of the pull-down driving of the voltage at the second node ND2 based on the threshold control signal NC. The threshold voltage regulator 313 includes a first transistor 313-1 and a second transistor 313-2. Transistors 313-1 and 313-2 may both include N-channel MOS transistors. The gate of the first transistor 313-1 receives the inverted signal IV, and the drain of the first transistor 313-1 is electrically coupled to the second node ND2. The gate of the second transistor 313-2 receives the threshold control signal NC. The drain of the second transistor 313-2 is electrically coupled to the source of the first transistor 313-1. The source of the second transistor 313-2 is electrically coupled to a terminal supplied with the second power supply voltage V2. In one embodiment, the threshold control signal NC is an analog signal, and the current drive intensity of the second transistor 313-2 varies according to the voltage level of the threshold control signal NC. In one embodiment, the threshold control signal NC is a digital signal, and the second transistor 313-2 is implemented using multiple transistors electrically coupled in parallel. The multiple transistors change the current drive intensity of the threshold voltage regulator 313 in response to each bit of the threshold control signal NC. When the inverted signal IV is at a low logic level, the first transistor 313-1 is turned off, and the threshold voltage regulator 313 does not affect the voltage level of the buffer output signal BOUT. When the inverting signal IV is at a high logic level, the first transistor 313-1 is turned on, and the threshold voltage regulator 313 lowers the voltage level of the buffer output signal BOUT. Compared to the pull-up drive strength, the threshold voltage regulator 313 increases the pull-down drive strength of the first buffer circuit 310, thereby performing the function of increasing the threshold voltage of the first buffer circuit 310. Figure 3 The reduction circuits 231 and 232 shown can both have a configuration substantially similar to that of reduction circuit 300 and can perform substantially the same functions. The first reduction circuit 231 and the second reduction circuit 232 can be implemented similarly to reduction circuit 300, wherein the first clock signal CLK1 and the second clock signal CLK2 are respectively used as inputs, and the first input signal IN1 and the second input signal IN2 are used as outputs.

[0040] Figure 4C For example, Figure 3 The timing diagram shown illustrates the operation of the duty cycle reduction circuit 230. The reduction circuits 231 and 232 of the duty cycle reduction circuit 230 are configured with... Figure 4A The configuration of the reduction circuit 300 is shown in the figure. (See reference.) Figure 3 , Figure 4A , Figure 4B and Figure 4C The first downsampling circuit 231 buffers the first clock signal CLK1, adjusts the pulse width of the first clock signal CLK1, and generates the first input signal IN1. The first downsampling circuit 231 uses a buffer circuit with a threshold voltage at a voltage level higher than the middle voltage of the swing range of the first clock signal CLK1 to buffer the first clock signal CLK1. The first input signal IN1 is generated with a smaller duty cycle and / or pulse width than the first clock signal CLK1. The second downsampling circuit 232 buffers the second clock signal CLK2, adjusts the pulse width of the second clock signal CLK2, and generates the second input signal IN2. The rising edge of the first input signal IN1 is generated 0.5tD later than the rising edge of the first clock signal CLK1, and the falling edge of the first input signal IN1 is generated 0.5tD earlier than the falling edge of the first clock signal CLK1. The value of tD varies according to the value of the threshold control signal NC. The second reduction circuit 232 uses a buffer circuit with a threshold voltage at a voltage level higher than the midpoint of the swing range of the second clock signal CLK2 to buffer the second clock signal CLK2. The second input signal IN2 is generated with a smaller duty cycle and / or pulse width than the second clock signal CLK2. The rising edge of the second input signal IN2 is generated 0.5tD later than the rising edge of the second clock signal CLK2, and the falling edge of the second input signal IN2 is generated 0.5tD earlier than the falling edge of the second clock signal CLK2. Therefore, the duty cycle reduction circuit 230 reduces the pulse width of clock signals CLK1 and CLK2 by tD, thereby reducing the corresponding duty cycles of clock signals CLK1 and CLK2 by the same time period, and generating input signals IN1 and IN2.

[0041] Figure 5 This is a timing diagram showing the operation of a duty cycle monitoring circuit 200 according to one embodiment. (Reference) Figures 3 to 5 The operation of a duty cycle monitoring circuit 200 according to one embodiment is described. A duty cycle reduction circuit 230 receives clock signals CLK1 and CLK2, and generates input signals IN1 and IN2 by reducing the duty cycles of clock signals CLK1 and CLK2 by the same time period. When the first reduction circuit 231 and the second reduction circuit 232 utilize... Figure 4AWhen implemented by the duty cycle reduction circuit 300, the rising edge of the first input signal IN1 is generated 0.5tD later than the rising edge of the first clock signal CLK1, and the falling edge of the first input signal IN1 is generated 0.5tD earlier than the falling edge of the first clock signal CLK1. The rising edge of the second input signal IN2 is generated 0.5tD later than the rising edge of the second clock signal CLK2, and the falling edge of the second input signal IN2 is generated 0.5tD earlier than the falling edge of the second clock signal CLK2. Compared with clock signals CLK1 and CLK2 respectively, input signals IN1 and IN2 both have pulse widths reduced by a time period tD. Because the duty cycle reduction circuit 230 reduces the duty cycle of clock signals CLK1 and CLK2 by the same time period, the duty cycle difference between input signals IN1 and IN2 is essentially similar to the duty cycle difference between clock signals CLK1 and CLK2.

[0042] The duty cycle detection circuit 210 receives input signals IN1 and IN2, and detects the duty cycle of input signals IN1 and IN2. Figure 5 The vertical axis of the timing diagram represents voltage V. When the capacitor of the duty cycle detection circuit 210 is in the pre-charge state, the voltage levels of output signal OUT1 and output signal OUT2 correspond to the voltage levels of the first power supply voltage V1. Figure 5In this clock signal, the duty cycle of the second clock signal CLK2 is greater than that of the first clock signal CLK1. During the first cycle of clock signals CLK1 and CLK2, the voltage levels of output signals OUT1 and OUT2 decrease according to the pulse widths of input signals IN1 and IN2, respectively. Because the pulse width of the second input signal IN2 is greater than that of the first input signal IN1, the voltage level of the second output signal OUT2 is lower than that of the first output signal OUT1. For example, the second output signal OUT2 is at a voltage level α lower than that of the first output signal OUT1. With each cycle of clock signals CLK1 and CLK2, the voltage level difference between the second output signal OUT2 and the first output signal OUT1 increases by a multiple of the number of cycles elapsed. During the second cycle of clock signals CLK1 and CLK2, the voltage level difference between output signals OUT1 and OUT2 is 2α. During the third cycle of clock signals CLK1 and CLK2, the voltage level difference between output signals OUT1 and OUT2 is 3α. When the clock signals CLK1 and CLK2 have passed their (m-1)th cycles, the voltage level difference between output signals OUT1 and OUT2 is (m-1)α. When the clock signals CLK1 and CLK2 have passed their (m-1)th cycles, the voltage level difference between output signals OUT1 and OUT2 is mα. For example, m is an integer greater than or equal to 6. The decrease in voltage level of the first output signal OUT1 in response to the first input signal IN1 is less than the decrease in voltage level of the first output signal OUT1 in response to the first clock signal CLK1. The decrease in voltage level of the second output signal OUT2 in response to the second input signal IN2 is less than the decrease in voltage level of the second output signal OUT2 in response to the second clock signal CLK2. Figure 5 The rate at which the voltage levels of output signals OUT1 and OUT2 decrease is less than that shown in the figure. Figure 2 The rate at which the voltage levels of output signals OUT1 and OUT2 decrease is shown. When the duty cycle detection circuit 210 detects that the input signals IN1 and IN2 have a lower duty cycle compared to clock signals CLK1 and CLK2, the time it takes for output signals OUT1 and OUT2 to reach the trigger voltage Vth of the latch circuit 220 increases. Therefore, the number of cycles that clock signals CLK1 and CLK2 take to reach the trigger voltage Vth corresponding to output signals OUT1 and OUT2 increases.

[0043] When the m-th cycle of clock signals CLK1 and CLK2 has elapsed, the voltage level of the second output signal OUT2 decreases to be equal to or lower than the trigger voltage Vth. Latch circuit 220 outputs a duty cycle detection signal DOUT in reset state RESET, and when it detects that the voltage level of the second output signal OUT2 has decreased to be equal to or lower than the trigger voltage Vth, the logic level of the trigger duty cycle detection signal DOUT is at the active level. When the voltage level of the second output signal OUT2 becomes lower than the trigger voltage Vth, latch circuit 220 outputs a duty cycle detection signal DOUT at the second logic level. Duty cycle monitoring circuit 200 compares the duty cycles of input signals IN1 and IN2, which have decreased duty cycles, and for one of the first output signal OUT1 and the second output signal OUT2, increases the number of cycles of clock signals CLK1 and CLK2 to reach the trigger voltage Vth. Therefore, when one of the first output signal OUT1 and the second output signal OUT2 reaches the trigger voltage Vth, the voltage level difference between the first output signal OUT1 and the second output signal OUT2 becomes larger. For example, in Figure 2 In the above, the voltage level difference between output signal OUT1 and output signal OUT2 is nα, while... Figure 5 In this circuit, the voltage level difference between output signals OUT1 and OUT2 is mα. When latch circuit 220 is triggered, a large voltage level difference between output signals OUT1 and OUT2 mitigates and / or prevents malfunctions during duty cycle monitoring operation. Duty cycle monitoring circuit 200 can accurately generate a duty cycle detection signal corresponding to the duty cycle difference between clock signals CLK1 and CLK2. A sufficiently large voltage level difference between output signals OUT1 and OUT2 mitigates and / or prevents instances where the duty cycle detection signal DOUT is generated at the opposite logic level despite offsets in latch circuit 220.

[0044] Figure 6A This is a diagram illustrating an example configuration of a reduction circuit 400 according to one embodiment. (See reference) Figure 6AThe downsampling circuit 400 adjusts the pulse width of the clock signal CLK and generates the input signal IN. The downsampling circuit 400 generates the input signal IN by delaying the timing of the rising edge of the clock signal CLK. The downsampling circuit 400 includes a pulse generator 410. The pulse generator 410 receives the clock signal CLK and generates the input signal IN by adjusting the pulse width of the clock signal CLK. The pulse generator 410 generates the input signal IN having a rising edge that occurs later than the rising edge of the clock signal CLK and a falling edge that occurs at the same timing as the falling edge of the clock signal CLK. The pulse generator 410 includes an odd number of inverters 411, NAND gates 412, and AND gates 413. The odd number of inverters 411 are electrically coupled in series sequentially. The odd number of inverters 411 serve as a delay circuit. The first-stage inverter among the odd number of inverters 411 receives the clock signal CLK and outputs an inverted signal of the clock signal CLK. The last inverter in the odd-numbered inverters 411 inverts the output signal of the previous inverter and generates an output signal with a delayed phase and opposite phase compared to the clock signal CLK. The NAND gate 412 receives the output signal of the last inverter in the odd-numbered inverters 411 and a first power supply voltage V1. The first power supply voltage V1 enables the NAND gate 412 to operate as an inverter. The first power supply voltage V1 and... Figure 1 The first power supply voltage V1 used is essentially the same. NAND gate 412 inverts the output signals of the odd number of inverters 411 and generates a delayed output signal DL. In one embodiment, NAND gate 412 is replaced by an inverter. AND gate 413 receives the clock signal CLK and the delayed output signal DL and generates the input signal IN. The propagation delay caused by the odd number of inverters 411 and NAND gate 412 can be variably set. To achieve... Figure 4A The circuit shown in the diagram has the same performance as the reduced circuit 300, with a propagation delay of tD, as shown. Figure 4C As shown in the diagram, pulse generator 410 generates an input signal IN that includes a pulse that is enabled at a time interval tD that is later than the clock signal CLK and disabled at the same time as the clock signal CLK. Figure 3 The reduction circuits 231 and 232 shown can both have a configuration substantially similar to that of reduction circuit 400 and can perform substantially the same functions. The first reduction circuit 231 and the second reduction circuit 232 can be implemented similarly to reduction circuit 400, wherein the first clock signal CLK1 and the second clock signal CLK2 are respectively used as inputs, and the first input signal IN1 and the second input signal IN2 are used as outputs.

[0045] Figure 6B For example, Figure 3 The timing diagram shown illustrates the operation of the duty cycle reduction circuit 230. The duty cycle reduction circuit 230 utilizes... Figure 6A The diagram shows the configuration of the reduction circuit 400. (Reference) Figure 3 , Figure 6A and Figure 6B The first reduction circuit 231 generates the first input signal IN1 by reducing the pulse width of the first clock signal CLK1. The rising edge of the first input signal IN1 is generated after the rising edge of the first clock signal CLK1 by a time interval tD. The falling edge of the first input signal IN1 is generated at the same time as the falling edge of the first clock signal CLK1. The second reduction circuit 232 generates the second input signal IN2 by reducing the pulse width of the second clock signal CLK2. The rising edge of the second input signal IN2 is generated after the rising edge of the second clock signal CLK2 by a time interval tD. The falling edge of the second input signal IN2 is generated at the same time as the falling edge of the second clock signal CLK2. The duty cycle reduction circuit reduces the pulse widths of clock signals CLK1 and CLK2 by a time interval tD, thereby reducing the corresponding duty cycles of clock signals CLK1 and CLK2 by the same time interval tD, and generating input signals IN1 and IN2.

[0046] Figure 7 This is a timing diagram showing the operation of a duty cycle monitoring circuit 200 according to one embodiment. (Reference) Figure 3 , Figure 6A , Figure 6B and Figure 7 The operation of a duty cycle monitoring circuit 200 according to one embodiment is described. A duty cycle reduction circuit 230 receives clock signals CLK1 and CLK2, and generates input signals IN1 and IN2 by reducing the duty cycles of clock signals CLK1 and CLK2 by the same time period. When the first reduction circuit 231 and the second reduction circuit 232 utilize... Figure 6AWhen implemented by the duty cycle reduction circuit 400, the rising edge of the first input signal IN1 is generated after a time interval tD compared to the rising edge of the first clock signal CLK1, and the falling edge of the first input signal IN1 is generated at the same time as the falling edge of the first clock signal CLK1. The rising edge of the second input signal IN2 is generated after a time interval tD compared to the rising edge of the second clock signal CLK2, and the falling edge of the second input signal IN2 is generated at the same time as the falling edge of the second clock signal CLK2. Both input signals IN1 and IN2 have pulse widths that are reduced by a time interval tD compared to clock signals CLK1 and CLK2, respectively. Because the duty cycle reduction circuit 230 reduces the duty cycle of clock signals CLK1 and CLK2 by the same time interval tD, the duty cycle difference between input signals IN1 and IN2 is substantially similar to the duty cycle difference between clock signals CLK1 and CLK2.

[0047] The duty cycle detection circuit 210 receives input signals IN1 and IN2, and detects the duty cycle of input signal IN1 and the duty cycle of input signal IN2. Figure 7 The vertical axis of the timing diagram represents voltage V. When the capacitor of the duty cycle detection circuit 210 is in the pre-charge state, the voltage levels of output signals OUT1 and OUT2 correspond to the voltage level of the first power supply voltage V1. Figure 7In this clock signal, the duty cycle of the second clock signal CLK2 is greater than that of the first clock signal CLK1. During the first cycle of clock signals CLK1 and CLK2, the voltage levels of output signals OUT1 and OUT2 decrease according to the pulse widths of input signals IN1 and IN2, respectively. Because the pulse width of the second input signal IN2 is greater than that of the first input signal IN1, the voltage level of the second output signal OUT2 is lower than that of the first output signal OUT1. For example, the second output signal OUT2 is at a voltage level α lower than that of the first output signal OUT1. With each cycle of clock signals CLK1 and CLK2, the voltage level difference between the second output signal OUT2 and the first output signal OUT1 increases by a multiple of the number of cycles elapsed. During the second cycle of clock signals CLK1 and CLK2, the voltage level difference between output signals OUT1 and OUT2 is 2α. During the third cycle of clock signals CLK1 and CLK2, the voltage level difference between output signals OUT1 and OUT2 is 3α. When the clock signals CLK1 and CLK2 have passed their (m-1)th cycles, the voltage level difference between output signals OUT1 and OUT2 is (m-1)α. When the clock signals CLK1 and CLK2 have passed their (m-1)th cycles, the voltage level difference between output signals OUT1 and OUT2 is mα. For example, m is an integer greater than or equal to 6. The decrease in voltage level of the first output signal OUT1 in response to the first input signal IN1 is less than the decrease in voltage level of the first output signal OUT1 in response to the first clock signal CLK1. The decrease in voltage level of the second output signal OUT2 in response to the second input signal IN2 is less than the decrease in voltage level of the second output signal OUT2 in response to the second clock signal CLK2. Figure 7 The rate at which the voltage levels of output signals OUT1 and OUT2 decrease is less than that shown in the figure. Figure 2 The rate at which the voltage levels of output signals OUT1 and OUT2 decrease is shown. When the duty cycle detection circuit 210 detects that the input signals IN1 and IN2 have a lower duty cycle compared to clock signals CLK1 and CLK2, the time it takes for output signals OUT1 and OUT2 to reach the trigger voltage Vth of the latch circuit 220 increases.

[0048] When the m-th cycle of clock signals CLK1 and CLK2 has elapsed, the voltage level of the second output signal OUT2 decreases to be equal to or lower than the trigger voltage Vth. Latch circuit 220 can output a duty cycle detection signal DOUT in reset state RESET, and when it detects that the voltage level of the second output signal OUT2 has decreased to be equal to or lower than the trigger voltage Vth, it triggers the logic level of the duty cycle detection signal DOUT to the active level. When the voltage level of the second output signal OUT2 becomes lower than the trigger voltage Vth, latch circuit 220 outputs a duty cycle detection signal DOUT at the second logic level. Duty cycle monitoring circuit 200 compares the duty cycles of input signals IN1 and IN2, which have decreased duty cycles, and for one of the first output signal OUT1 and the second output signal OUT2, increases the number of cycles of clock signals CLK1 and CLK2 to reach the trigger voltage Vth. Therefore, when one of the first output signal OUT1 and the second output signal OUT2 reaches the trigger voltage Vth, the voltage level difference between the first output signal OUT1 and the second output signal OUT2 becomes larger. For example, in Figure 2 In the above, the voltage level difference between output signal OUT1 and output signal OUT2 is nα, while... Figure 7 In this circuit, the voltage level difference between output signals OUT1 and OUT2 is mα. When latch circuit 220 is triggered, a large voltage level difference between output signals OUT1 and OUT2 mitigates and / or prevents malfunctions during duty cycle monitoring operation. Duty cycle monitoring circuit 200 can accurately generate a duty cycle detection signal DOUT corresponding to the duty cycle difference between clock signals CLK1 and CLK2. A sufficiently large voltage level difference between output signals OUT1 and OUT2 mitigates and / or prevents instances where the duty cycle detection signal DOUT is generated at the opposite logic level despite offsets in latch circuit 220.

[0049] Figure 8 This is a diagram illustrating the configuration of a duty cycle monitoring circuit 500 according to one embodiment. (See reference) Figure 8The duty cycle monitoring circuit 500 includes a clock chopper circuit 540, a duty cycle reduction circuit 530, a duty cycle detection circuit 510, and a latch circuit 520. The clock chopper circuit 540 receives a first clock signal CLK1, a second clock signal CLK2, and a toggle signal FL, and generates a first selected clock signal SCLK1 and a second selected clock signal SCLK2. Based on the toggle signal FL, the clock chopper circuit 540 outputs one of the clock signals CLK1 and CLK2 as the first selected clock signal SCLK1, and outputs the other of the clock signals CLK1 and CLK2 as the second selected clock signal SCLK2. For example, when the toggle signal FL is at a first logic level, the clock chopper circuit 540 outputs the first clock signal CLK1 as the first selected clock signal SCLK1, and outputs the second clock signal CLK2 as the second selected clock signal SCLK2. When the toggle signal FL is at the second logic level, the clock chopper circuit 540 outputs a second clock signal CLK2 as the first selected clock signal SCLK1, and outputs the first clock signal CLK1 as the second selected clock signal SCLK2. The clock chopper circuit 540 switches between clock signals CLK1 and CLK2 based on the logic level of the toggle signal FL, and outputs selected clock signals SCLK1 and SCLK2. The clock chopper circuit 540 controls the duty cycle monitoring circuit 500 to generate a duty cycle detection signal DOUT based on the detection result of the duty cycle of the first clock signal CLK1 relative to the duty cycle of the second clock signal CLK2, or based on the detection result of the duty cycle of the second clock signal CLK2 relative to the duty cycle of the first clock signal CLK1.

[0050] The duty cycle reduction circuit 530 receives selection clock signals SCLK1 and SCLK2, and generates a first input signal IN1 and a second input signal IN2 by reducing the duty cycle of selection clock signals SCLK1 and SCLK2 by the same amount of time. The duty cycle reduction circuit 530 may have... Figure 3 The duty cycle reduction circuit 230 shown in the diagram has a substantially similar configuration and performs substantially the same function. The duty cycle detection circuit 510 receives input signals IN1 and IN2, and generates a first output signal OUT1 and a second output signal OUT2 by detecting the duty cycles of the input signals IN1 and IN2. The latch circuit 520 receives output signals OUT1 and OUT2, and generates a duty cycle detection signal DOUT based on the output signals OUT1 and OUT2. The duty cycle detection circuit 510 and the latch circuit 520 may have respectively... Figure 3The duty cycle detection circuit 210 and latch circuit 220 are configured in a basically similar manner, and can respectively perform functions that are basically similar to those performed by the duty cycle detection circuit 210 and latch circuit 220.

[0051] The clock chopper circuit 540 includes a first selection circuit 541 and a second selection circuit 542. The first selection circuit 541 receives a first clock signal CLK1, a second clock signal CLK2, and a toggle signal FL. When the toggle signal FL is at a first logic level, the first selection circuit 541 outputs the first clock signal CLK1 as the first selected clock signal SCLK1. When the toggle signal FL is at a second logic level, the first selection circuit 541 outputs the second clock signal CLK2 as the first selected clock signal SCLK1. The second selection circuit 542 receives the first clock signal CLK1, the second clock signal CLK2, and the toggle signal FL. When the toggle signal FL is at a first logic level, the second selection circuit 542 outputs the second clock signal CLK2 as the second selected clock signal SCLK2. When the toggle signal FL is at a second logic level, the second selection circuit 542 outputs the first clock signal CLK1 as the second selected clock signal SCLK2. Both selection circuits 541 and 542 can be implemented using a 2:1 multiplexer.

[0052] The clock chopper circuit 540 enhances the reliability of the duty cycle monitoring operation of the duty cycle monitoring circuit 500. When the toggle signal FL is at the first logic level, the clock chopper circuit 540 outputs a first clock signal CLK1 as the first selected clock signal SCLK1 and a second clock signal CLK2 as the second selected clock signal SCLK2. The duty cycle monitoring circuit 500 detects the duty cycle of the first clock signal CLK1 relative to the duty cycle of the second clock signal CLK2. For example, when the duty cycle of the second clock signal CLK2 is greater than the duty cycle of the first clock signal CLK1, the duty cycle monitoring circuit 500 generates a duty cycle detection signal DOUT at the first logic level. When the toggle signal FL transitions from the first logic level to the second logic level, the clock chopper circuit 540 outputs the second clock signal CLK2 as the first selected clock signal SCLK1 and outputs the first clock signal CLK1 as the second selected clock signal SCLK2. The duty cycle monitoring circuit 500 detects the duty cycle of the second clock signal CLK2 relative to the duty cycle of the first clock signal CLK1. In this example, the duty cycle monitoring circuit 500 generates a duty cycle detection signal DOUT at a second logic level. When the duty cycle monitoring circuit 500 generates a duty cycle detection signal DOUT at a first logic level, the duty cycle difference between clock signals CLK1 and CLK2 can be estimated or measured to be minimal, allowing the detection of an offset in the duty cycle monitoring circuit 500 or a fault in the duty cycle monitoring circuit 500.

[0053] Figure 9 This diagram illustrates the configuration of a semiconductor device 600 according to one embodiment. The semiconductor device 600 is electrically coupled to an external device via multiple pads, receives various signals from the external device, and transmits various signals to the external device. The semiconductor device 600 receives a first strobe signal WDQS and a second strobe signal WDQSB from the external device via a first strobe pad 601 and a second strobe pad 602, respectively. The semiconductor device 600 receives a command address signal CA from the external device via a command address pad 603. The command address signal CA includes a row command address signal and a column command address signal. The command address pad 603 includes multiple pads. The row command address signal and the column command address signal can be received via separate pads. The semiconductor device 600 receives a system clock signal CK from the external device via a clock pad 604. The first strobe signal WDQS may have an opposite phase to the second strobe signal WDQSB. The strobe signals WDQS and WDQSB can operate at a frequency higher than the frequency of the system clock signal CK. For example, the frequencies of the strobe signals WDQS and WDQSB are twice the frequency of the system clock signal CK. In one embodiment, the frequencies of the strobe signals WDQS and WDQSB are equal to or lower than the frequency of the system clock signal CK. The semiconductor device 600 receives data DQ transmitted from an external device via data pad 605 and transmits data DQ to the external device. The semiconductor device 600 outputs a third strobe signal RDQS and a fourth strobe signal RDQSB to the external device via the third strobe pad 606 and the fourth strobe pad 607, respectively. The semiconductor device 600 transmits a data error signal DERR to the external device via the data error pad 608. The operation of the semiconductor device 600 receiving data DQ from the external device can be a write operation. The operation of the semiconductor device 600 transmitting data DQ to the external device can be a read operation. The strobe signals WDQS and WDQSB can be write strobe signals, and the strobe signals RDQS and RDQSB can be read strobe signals. The strobe signals WDQS and WDQSB can be synchronized with the system clock signal CK, and can also be synchronized with the data DQ received by the semiconductor device 600 from the external device. The strobe signals RDQS and RDQSB can be synchronized with the data DQ transmitted from the semiconductor device 600 to the external device.

[0054] Semiconductor device 600 includes a gating receiver circuit 611, a first duty cycle adjustment circuit 612, a data receiver circuit 613, and a duty cycle monitoring circuit 614. The gating receiver circuit 611 receives gating signals WDQS and WDQSB from an external device via gating pads 601 and 602. The gating receiver circuit 611 provides the gating signals WDQS and WDQSB to the first duty cycle adjustment circuit 612. The first duty cycle adjustment circuit 612 receives a first duty cycle control signal WDC. Based on the first duty cycle control signal WDC, the first duty cycle adjustment circuit 612 adjusts the duty cycle of the gating signals WDQS and WDQSB, and generates a first internal gating signal IDQS1 and a second internal gating signal IDQS1B. The first duty cycle adjustment circuit 612 adjusts the duty cycle of one or both of the strobe signals WDQS and WDQSB based on the first duty cycle control signal WDC, and generates internal strobe signals IDQS1 and IDQS1B with adjusted duty cycles. The first duty cycle control signal WDC is generated based on the result of the duty cycle monitoring operation of the duty cycle monitoring circuit 614 and / or the duty cycle detection signal DOUT. The data receiving circuit 613 receives the internal strobe signals IDQS1 and IDQS1B. The data receiving circuit 613 receives data DQ from an external device through the data pad 605. The data receiving circuit 613 receives data DQ synchronously with the internal strobe signals IDQS1 and IDQS1B. The data DQ received by the data receiving circuit 613 is provided as an internal data signal of the semiconductor device 600.

[0055] The duty cycle monitoring circuit 614 receives internal strobe signals IDQS1 and IDQS1B, and generates a duty cycle detection signal DOUT in response to detecting the duty cycles of the internal strobe signals IDQS1 and IDQS1B. The duty cycle monitoring circuit 614 reduces the duty cycles of the internal strobe signals IDQS1 and IDQS1B by the same time period, thereby generating signals such as... Figure 8 The input signals IN1 and IN2 are input signals. The duty cycle monitoring circuit 614 generates a duty cycle detection signal DOUT by detecting the duty cycle of the input signals. The duty cycle monitoring circuit 614 can have the same characteristics as... Figure 8 The duty cycle monitoring circuit 500 shown in the figure has a substantially similar configuration and can perform substantially the same functions. In one embodiment, the duty cycle monitoring circuit 614 can utilize... Figure 1 Duty cycle monitoring circuit 100 and Figure 3This is implemented using one of the duty cycle monitoring circuits 200. The duty cycle monitoring circuit 614 receives an enable signal EN and a toggle signal FL. The enable signal EN activates the duty cycle monitoring circuit 614 and controls or triggers it to perform duty cycle monitoring operations. The enable signal EN can correspond to... Figure 1 The enable signal EN is shown in the diagram. When the toggle signal FL is at the first logic level, the duty cycle monitoring circuit 614 generates a duty cycle detection signal DOUT by detecting the duty cycle of the first internal strobe signal IDQS1 relative to the duty cycle of the second internal strobe signal IDQS1B. For example, the duty cycle monitoring circuit 614 detects whether the duty cycle of the first internal strobe signal IDQS1 is greater than the duty cycle of the second internal strobe signal IDQS1B, and changes the logic level of the duty cycle detection signal DOUT accordingly. When the toggle signal FL is at the second logic level, the duty cycle monitoring circuit 614 generates a duty cycle detection signal DOUT by detecting the duty cycle of the second internal strobe signal IDQS1B relative to the duty cycle of the first internal strobe signal IDQS1. For example, the duty cycle monitoring circuit 614 detects whether the duty cycle of the second internal strobe signal IDQS1B is greater than the duty cycle of the first internal strobe signal IDQS1, and changes the logic level of the duty cycle detection signal DOUT accordingly. When the duty cycle difference between the internal strobe signal IDQS1 and the internal strobe signal IDQS1B remains constant, the logic level of the duty detection signal DOUT when the toggle signal FL is at the first logic level is opposite to the logic level of the duty detection signal DOUT when the toggle signal FL is at the second logic level.

[0056] Semiconductor device 600 includes a first clock distribution circuit 615 and a data error transmission circuit 616. The first clock distribution circuit 615 is electrically coupled between a first duty cycle adjustment circuit 612 and a data receiving circuit 613. The first clock distribution circuit 615 receives internal strobe signals IDQS1 and IDQS1B from the first duty cycle adjustment circuit 612 and distributes the internal strobe signals IDQS1 and IDQS1B to the data receiving circuit 613. Although not shown, semiconductor device 600 includes multiple data receiving circuits corresponding to the number of data channels, and the first clock distribution circuit 615 distributes the internal strobe signals IDQS1 and IDQS1B to the multiple data receiving circuits. The data error transmission circuit 616 is electrically coupled to a data error pad 608 and transmits a data error signal DERR to an external device. During normal operation, the data error transmission circuit 616 transmits the error detection result within the internal data of semiconductor device 600 as the data error signal DERR to the external device. The data error transmission circuit 616 is electrically coupled to the duty cycle monitoring circuit 614. During duty cycle monitoring operation, the data error transmission circuit 616 transmits the duty cycle detection signal DOUT received from the duty cycle monitoring circuit 614 as a data error signal DERR to an external device. During duty cycle monitoring operation, the external device receives the duty cycle detection signal DOUT within the data error signal DERR. When the semiconductor device 600 transmits the duty cycle detection signal DOUT to an external device via the data error transmission circuit 616 and the data error pad 608, the semiconductor device 600 may not include a separate pad for transmitting the duty cycle detection signal DOUT.

[0057] Semiconductor device 600 includes a second duty cycle adjustment circuit 617, a data transmission circuit 618, and a gating transmission circuit 619. The second duty cycle adjustment circuit 617 receives a first internal gating signal IDQS1, a second internal gating signal IDQS1B, and a second duty cycle control signal RDC. The second duty cycle adjustment circuit 617 generates a third internal gating signal IDQS2 and a fourth internal gating signal IDQS2B by adjusting the duty cycles of the internal gating signals IDQS1 and IDQS1B based on the second duty cycle control signal RDC. The second duty cycle adjustment circuit 617 also adjusts the duty cycle of one or both of the internal gating signals IDQS1 and IDQS1B based on the second duty cycle control signal RDC, and generates internal gating signals IDQS2 and IDQS2B with adjusted duty cycles. The second duty cycle control signal RDC is generated based on the result of a duty cycle monitoring operation of a duty cycle monitoring circuit 614 and / or a duty cycle detection signal DOUT. Data transmission circuit 618 receives internal strobe signals IDQS2 and IDQS2B, as well as internal data from semiconductor device 600. Synchronizing with internal strobe signals IDQS2 and IDQS2B, data transmission circuit 618 outputs the internal data of semiconductor device 600 as data DQ. Data transmission circuit 618 transmits data DQ to an external device. Strobe transmission circuit 619 receives internal strobe signals IDQS2 and IDQS2B. Strobe transmission circuit 619 generates strobe signals RDQS and RDQSB based on internal strobe signals IDQS2 and IDQS2B. Strobe transmission circuit 619 generates strobe signals RDQS and RDQSB by driving the voltages of internal strobe signals IDQS2 and IDQS2B, and transmits strobe signals RDQS and RDQSB to an external device via strobe pads 606 and 607.

[0058] Semiconductor device 600 includes a second clock distribution circuit 621, a command control circuit 622, and a clock receiver 623. The second clock distribution circuit 621 is electrically coupled between a second duty cycle adjustment circuit 617 and a data transmission circuit 618, and between the second duty cycle adjustment circuit 617 and a strobe transmission circuit 619. The second clock distribution circuit 621 receives internal strobe signals IDQS2 and IDQS2B from the second duty cycle adjustment circuit 617 and distributes these signals to the data transmission circuits 618 and 619. Although not shown, semiconductor device 600 may include multiple data transmission circuits based on the number of data channels, and the second clock distribution circuit 621 distributes the internal strobe signals IDQS2 and IDQS2B to multiple data transmission circuits. Command control circuit 622 receives a command address signal CA from an external device via command address pad 603. Command control circuit 622 generates an internal command signal INCMD based on command address signal CA to enable semiconductor device 600 to perform various operations. Command control circuit 622 generates a first duty cycle control signal WDC, an enable signal EN, a toggle signal FL, and a second duty cycle control signal RDC based on command address signal CA. When semiconductor device 600 performs a duty cycle monitoring operation, an external device receives a duty cycle detection signal DOUT via data error signal DERR and generates command address signal CA based on duty cycle detection signal DOUT. Command control circuit 622 generates the first duty cycle control signal WDC, the toggle signal FL, and the second duty cycle control signal RDC based on information included in command address signal CA. Command control circuit 622 provides the first duty cycle control signal WDC to first duty cycle adjustment circuit 612, the enable signal EN and the toggle signal FL to duty cycle monitoring circuit 614, and the second duty cycle control signal RDC to second duty cycle adjustment circuit 617. Clock receiver 623 can receive the system clock signal CK transmitted from external device via clock pad 604. The clock receiver 623 generates a reference clock signal RCK by buffering the system clock signal CK, and provides the reference clock signal RCK to the command control circuit 622. The command address signal CA is synchronized with the system clock signal CK and transmitted from the external device to the semiconductor device 600.

[0059] The command control circuit 622 includes a command decoder 622-1 and a mode register 622-2. The command decoder 622-1 receives a command address signal CA and a reference clock signal RCK. Synchronizing with the reference clock signal RCK, the command decoder 622-1 latches the command address signal CA and generates various internal command signals INCMD by decoding the latched command address signal. The command decoder 622-1 generates a register command signal MRW by decoding the command address signal CA. The command decoder 622-1 provides the register command signal MRW to the mode register 622-2. The mode register 622-2 receives and stores the register command signal MRW. The mode register 622-2 stores various information based on the register command signal MRW. Based on the information stored in the mode register 622-2, the mode register 622-2 outputs a first duty cycle control signal WDC, an enable signal EN, a toggle signal FL, and a second duty cycle control signal RDC.

[0060] Figure 10 This is a timing diagram showing the operation of a semiconductor device 600 according to one embodiment. (See reference) Figure 9 and Figure 10 The operation of a semiconductor device 600 according to one embodiment is described. The semiconductor device 600 is electrically coupled to an external device to perform a duty cycle monitoring operation. For example, the semiconductor device 600 performs a duty cycle monitoring operation during a duty cycle adjustment training operation using an external device. At time t1, the external device transmits a command address signal CA to the semiconductor device 600, the command address signal CA including information containing a default value of a first duty cycle control signal WDC, to perform the duty cycle monitoring operation. Figure 10In this context, the command address signal CA from which the register command signal MRW is generated is denoted as MRS. Command control circuit 622 sets the first duty cycle control signal WDC to its default value based on the command address signal CA. After a time interval tMRD has elapsed at time t2, the external device transmits the command address signal CA to initiate a duty cycle monitoring operation. The time interval tMRD includes the time interval during which the command address signal MRS associated with the register command signal MRW can be transmitted. The command address signal CA includes information activating the duty cycle monitoring circuit 614 and information setting the toggle signal FL to a first logic level. The external device transmits strobe signals WDQS and WDQSB to semiconductor device 600. After the command address signal CA is transmitted, the duty cycle monitoring operation is performed during the time interval tDCMM. The time interval tDCMM includes the time interval from the point in time where the command address signal CA associated with the duty cycle monitoring operation is transmitted to the point in time where the data error signal DERR is transmitted from semiconductor device 600. Command control circuit 622 provides the duty cycle monitoring circuit 614 with an enable signal EN at a first logic level and a toggle signal FL. Duty cycle monitoring circuit 614 monitors the duty cycle of internal strobe signals IDQS1 and IDQS1B based on enable signal EN and toggle signal FL, and generates duty cycle detection signal DOUT. Data error transmission circuit 616 outputs the duty cycle detection signal DOUT from data error signal DERR to external device. At time t3, external device transmits command address signal CA including information to set toggle signal FL to the second logic level. Command control circuit 622 provides toggle signal FL at the second logic level to duty cycle monitoring circuit 614. Duty cycle monitoring circuit 614 monitors the duty cycle of internal strobe signals IDQS1 and IDQS1B based on toggle signal FL, and generates duty cycle detection signal DOUT. Data error transmission circuit 616 outputs the duty cycle detection signal DOUT from data error signal DERR to external device. After time interval tDCMM at time t4, external device transmits command address signal CA to stop duty cycle monitoring operation. Command control circuit 622 disables the enable signal EN based on command address signal CA, and duty cycle monitoring circuit 614 is deactivated or stops performing duty cycle monitoring function. When the logic level of duty cycle detection signal DOUT generated by the duty cycle monitoring operation performed between time t2 and time t3 is opposite to the logic level of duty cycle detection signal DOUT generated by the duty cycle monitoring operation performed between time t3 and time t4, the external device provides command address signal CA to the semiconductor device at time t5 to update the value of first duty cycle control signal WDC. Command control circuit 622 updates the value of first duty cycle control signal WDC based on command address signal CA.The first duty cycle adjustment circuit 612 generates internal strobe signals IDQS1 and IDQS1B by adjusting the duty cycles of strobe signals WDQS and WDQSB based on the first duty cycle control signal WDC. When the duty cycle adjustment of the first strobe signal WDQS and the second strobe signal WDQSB is complete, the operation performed between time t2 and time t5 can be repeated. At time t6, the external device retransmits the command address signal CA to perform the duty cycle monitoring operation. The command control circuit 622 provides the duty cycle monitoring circuit 614 with an enable signal EN and a toggle signal FL at the first logic level. The duty cycle monitoring circuit 614 monitors the corresponding duty cycles of the internal strobe signals IDQS1 and IDQS1B based on the enable signal EN and the toggle signal FL, and generates a duty cycle detection signal DOUT. The data error transmission circuit 616 outputs the duty cycle detection signal DOUT from the data error signal DERR to the external device. When the first duty cycle control signal WDC is set, the second duty cycle control signal RDC is set using the same method.

[0061] Figure 11 This is a diagram illustrating the configuration of a semiconductor system 700 according to one embodiment. (See reference) Figure 11 The semiconductor system 700 includes a host device 710 and a memory device 720. The host device 710 is a master device that controls the memory device 720 and enables it to perform various operations. The host device 710 accesses the memory device 720 to write data to and read data stored in the memory device 720. For example, the host device 710 includes one or more of a central processing unit (CPU), graphics processing unit (GPU), multimedia processor (MMP), digital signal processor (DSP), application processor (AP), data processing unit (DPU), neural processing unit (NPU), and system-on-a-chip (SoC). Under the control of the host device 710, the memory device 720 stores data transferred from the host device 710 and outputs data stored in the memory device 720 back to the host device 710. For example, the memory device 720 is a high-bandwidth memory (HBM) device.

[0062] The host device 710 may include an interface circuit PHY1. The host device 710 is electrically coupled to the memory device 720 via the interface circuit PHY1, and transmits various signals to and receives various signals from the memory device 720 via the interface circuit PHY1. The host device 710 may be a device corresponding to... Figure 9 Components of the external device described herein. For example, such as... Figure 9As shown, host device 710 transmits command address signal CA, system clock signal CK, strobe signals WDQS and WDQSB, and data DQ to memory device 720 via interface circuit PHY1, and receives strobe signals RDQS and RDQSB, data DQ, and data error signal DERR transmitted from memory device 720 via interface circuit PHY1. Memory device 720 includes logic die 721 and multiple memory dies 722. The multiple memory dies 722 are sequentially stacked on or above logic die 721 and electrically coupled via vias 723 formed through each of logic die 721 and multiple memory dies 722. Logic die 721 facilitates data communication between host device 710 and multiple memory dies 722. Logic die 721 includes interface circuit PHY2 electrically coupled to host device 710 and multiple memory dies 722. The interface circuit PHY2 converts signals transmitted from the host device 710 into signals suitable for use in the memory device 720, and transmits the converted signals to multiple memory dies 722. The interface circuit PHY2 also converts signals output from the multiple memory dies 722 into signals suitable for use in the host device 710, and transmits the converted signals to the host device 710. The interface circuit PHY2 of the logic die 721 may include... Figure 9 The semiconductor device 600 is configured as shown. To support high bandwidth, the memory device 720 is electrically coupled to the host device 710 via a large number of signal transmission lines. The memory device 720 is manufactured in a form where it is stacked on or on a single substrate with the host device 710.

[0063] Semiconductor system 700 includes an interposer 730 and a package substrate 740. The interposer 730 is stacked on or above the package substrate 740, and a host device 710 and a memory device 720 are stacked on or above the interposer 730. The host device 710 is located in a first region (such as...) Figure 11 The memory device 720 is stacked on or above the interposer layer 730 in the left region. The memory device 720 is stacked on or above the interposer layer 730 in the second region (such as...). Figure 11The memory device 720 is stacked on or above the interposer 730 in the right-hand region. The package substrate 740, interposer 730, host device 710, and memory device 720 can be packaged in a single package. The package substrate 740 is electrically coupled to an external device using multiple solder balls 741. Signal paths 742 and 743, which electrically couple the interposer 730 to the solder balls 741, are formed within the package substrate 740. The interposer 730 is electrically coupled to signal paths 742 and 743 of the package substrate 740 via solder bumps 731. Signal path 732, which electrically couples the host device 710 to the memory device 720, is formed within the interposer 730. Signal path 732 can electrically couple the interface circuit PHY2 of the logic die 721 to the interface circuit PHY1 of the host device 710. Signal paths 733 and 734, which electrically couple the host device 710 and the memory device 720 to the package substrate 740, are formed within the interposer 730. Host device 710 is electrically coupled to signal path 733 of interposer 730 via microbump 711. Memory device 720 is electrically coupled to signal path 734 of interposer 730 via microbump 724. Logic die 721 is electrically coupled to signal path 734 of interposer 730 via microbump 724, and multiple memory dies 722 are sequentially stacked on or above logic die 721 via microbump 724. Microbump 724 electrically couples vias of logic die 721 to vias of multiple memory dies 722. Signal path 732 of interposer 730, which electrically couples interface circuit PHY2 of logic die 721 and interface circuit PHY1 of host device 710, may include a signal transmission line, link, bus, or channel between host device 710 and memory device 720. For example, Figure 9 The strobe signals WDQS, WDQSB, RDQS and RDQSB, data DQ, system clock signal CK, command address signal CA, and data error signal DERR shown are transmitted between the host device 710 and the memory device 720 via signal path 732. Signal path 733, which electrically couples the host device 710 to the interposer 730 of the package substrate 740, may include signal transmission lines, links, buses, or channels to allow the host device 710 to communicate with external devices. Signal path 734, which electrically couples the logic die 721 to the interposer 730 of the package substrate 740, may be a direct access path facilitating direct access between external devices and the memory device 720.

[0064] Concepts have been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions are possible without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to these descriptions. All variations within the meaning and equivalents of the claims are included within their scope.

Claims

1. A duty cycle monitoring circuit, comprising: A duty cycle reduction circuit, which: receives a first clock signal and a second clock signal; reduces the duty cycle of the first clock signal by an amount to generate a first input signal; and reduces the duty cycle of the second clock signal by the amount to generate a second input signal; A duty cycle detection circuit, which: detects the duty cycle of the first input signal and the duty cycle of the second input signal to generate a first output signal and a second output signal; and A latching circuit that generates a duty cycle detection signal when one of the first output signal and the second output signal reaches the trigger voltage.

2. The duty cycle monitoring circuit according to claim 1, wherein, The duty cycle reduction circuit generates the first input signal and the second input signal respectively by adjusting the pulse width of the first clock signal and the pulse width of the second clock signal. The first input signal and the second input signal have a reduced duty cycle compared to the duty cycle of the first clock signal and the duty cycle of the second clock signal.

3. The duty cycle monitoring circuit according to claim 1, wherein, The duty cycle reduction circuit includes: A first reduction circuit, wherein: the duty cycle of the first clock signal is reduced by the amount to generate the first input signal; and The second reduction circuit reduces the duty cycle of the second clock signal by the amount to generate the second input signal.

4. The duty cycle monitoring circuit according to claim 3, in, The first reduction circuit includes a buffer circuit that buffers the first clock signal to generate the first input signal; as well as The threshold voltage of the buffer circuit is higher than the midpoint voltage level of the swing range of the first clock signal.

5. The duty cycle monitoring circuit according to claim 3, wherein, The first reduction circuit includes: The first inverter inverts the first clock signal and outputs an inverted signal at the first node; A second inverter, which: inverts the inverted signal and outputs the first input signal at the second node; and A threshold voltage regulator that pulls down the voltage at the second node based on the inverted signal and the threshold adjustment signal.

6. The duty cycle monitoring circuit according to claim 3, wherein, The first downsampling circuit includes a pulse generator that generates the first input signal, the first input signal having a rising edge that occurs at a time later than the rising edge of the first clock signal.

7. The duty cycle monitoring circuit according to claim 6, wherein, The pulse generator includes: An odd number of inverters delay the first clock signal; A NAND gate, which: receives the output signal of the last stage of the odd number of inverters and the power supply voltage, and generates a delayed output signal; and An AND gate that receives the first clock signal and the delayed output signal, and generates the first input signal.

8. The duty cycle monitoring circuit according to claim 1, wherein, The duty cycle detection circuit generates the first output signal by discharging the first capacitor electrically coupled to the first output node within a time interval corresponding to the pulse width of the first input signal. The second output signal is generated by discharging a second capacitor electrically coupled to the second output node within a time interval corresponding to the pulse width of the second input signal.

9. The duty cycle monitoring circuit according to claim 1, wherein, The latch circuit generates a duty cycle detection signal at a first logic level when the first output signal is at a voltage level lower than the trigger voltage; and generates a duty cycle detection signal at a second logic level when the second output signal is at a voltage level lower than the trigger voltage.

10. A duty cycle monitoring circuit, comprising: A clock chopper circuit, which receives a first clock signal and a second clock signal, and outputs the first of the first clock signal and the second clock signal as a first selected clock signal based on a toggle signal, and outputs the second of the first clock signal and the second clock signal as a second selected clock signal. A duty cycle reduction circuit reduces the duty cycle of the first selected clock signal and the duty cycle of the second selected clock signal by an amount to generate a first input signal and a second input signal. A duty cycle detection circuit, which: detects the duty cycle of the first input signal and the duty cycle of the second input signal to generate a first output signal and a second output signal; and The latching circuit generates a duty cycle detection signal based on the first output signal and the second output signal.

11. The duty cycle monitoring circuit according to claim 10, wherein, The clock chopper circuit: when the toggle signal is at a first logic level, outputs the first clock signal as the first selected clock signal and outputs the second clock signal as the second selected clock signal; and when the toggle signal is at a second logic level, outputs the second clock signal as the first selected clock signal and outputs the first clock signal as the second selected clock signal.

12. The duty cycle monitoring circuit according to claim 10, wherein, The duty cycle reduction circuit generates the first input signal and the second input signal respectively by adjusting the pulse width of the first selected clock signal and the pulse width of the second selected clock signal. The first input signal and the second input signal have a reduced duty cycle compared to the duty cycle of the first selected clock signal and the duty cycle of the second selected clock signal.

13. The duty cycle monitoring circuit according to claim 10, wherein, The duty cycle reduction circuit includes: A first reduction circuit, wherein: the duty cycle of the first clock signal is reduced by the amount to generate the first input signal; and The second reduction circuit reduces the duty cycle of the second clock signal by the amount to generate the second input signal.

14. The duty cycle monitoring circuit according to claim 10, wherein, The duty cycle detection circuit generates the first output signal by discharging the first capacitor electrically coupled to the first output node within a time interval corresponding to the pulse width of the first input signal. The second output signal is generated by discharging a second capacitor electrically coupled to the second output node within a time interval corresponding to the pulse width of the second input signal.

15. The duty cycle monitoring circuit according to claim 10, wherein, The latch circuit generates a duty cycle detection signal at a first logic level when the first output signal is at a voltage level lower than the trigger voltage level; and generates a duty cycle detection signal at a second logic level when the second output signal is at a voltage level lower than the trigger voltage level.

16. A semiconductor device, comprising: A gating and receiving circuit that receives a first gating signal and a second gating signal from an external device; The first duty cycle adjustment circuit adjusts the duty cycle of the first gating signal and the duty cycle of the second gating signal based on the first duty cycle control signal to generate the first internal gating signal and the second internal gating signal, respectively. A data receiving circuit, wherein: it receives data synchronously with the first internal strobe signal and the second internal strobe signal; and A duty cycle monitoring circuit, which: reduces the duty cycle of the first internal gating signal and the duty cycle of the second internal gating signal by an amount to generate a first input signal and a second input signal; and detects the duty cycle of the first input signal and the duty cycle of the second input signal to generate a duty cycle detection signal. The first duty cycle control signal is generated based on the duty cycle detection signal.

17. The semiconductor device of claim 16, further comprising a data error transmission circuit, the data error transmission circuit: outputting the duty cycle detection signal within the data error signal to the external device.

18. The semiconductor device according to claim 16, wherein, The duty cycle monitoring circuit: Receive the flip signal; When the toggle signal is at the first logic level, the duty cycle detection signal is generated by detecting the duty cycle of the first input signal relative to the duty cycle of the second input signal; as well as When the flip signal is at the second logic level, the duty cycle detection signal is generated by detecting the duty cycle of the second input signal relative to the duty cycle of the first input signal.

19. The semiconductor device of claim 18, further comprising a command control circuit, the command control circuit: receiving a command address signal from the external device; and generating the first duty cycle control signal and the toggle signal based on the command address signal.

20. The semiconductor device of claim 16, further comprising: The second duty cycle adjustment circuit, which: The duty cycle of the first internal gating signal and the duty cycle of the second internal gating signal are adjusted based on the second duty control signal to generate the third internal gating signal and the fourth internal gating signal. A data transmission circuit, wherein: the data is output synchronously with the third internal strobe signal and the fourth internal strobe signal; and The gating transmission circuit generates a third gating signal and a fourth gating signal based on the third internal gating signal and the fourth internal gating signal, respectively.

21. The semiconductor device of claim 20, further comprising a command control circuit, the command control circuit: receiving a command address signal from the external device; and generating a second duty cycle control signal based on the command address signal.

22. A method comprising: The duty cycle of the first clock signal is reduced by an amount to generate the first input signal, and the duty cycle of the second clock signal is reduced by the amount to generate the second input signal. A first output signal is generated based on the duty cycle of the first input signal, and a second output signal is generated based on the duty cycle of the second input signal; as well as When one of the first output signal and the second output signal reaches the trigger voltage, a duty cycle detection signal is generated.

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