Silicon photomultiplier and imaging system

Abstract

The present disclosure relates to silicon photomultipliers and imaging systems. A silicon photomultiplier (SiPM) is disclosed. The SiPM includes a plurality of microcells coupled to a summing node of the SiPM. Each microcell of the plurality of microcells includes a single photon avalanche diode and a passive quenching device coupled in series with the single photon avalanche diode. Each microcell of the plurality of microcells also includes a current mirror configured to generate a microcell output current based on a current from the single photon avalanche diode.

Description

Technical Field

[0001] This disclosure generally relates to imaging systems, and more particularly to imaging sensors comprising silicon photomultiplier tubes (SiPMs) consisting of multiple single-photon avalanche diodes (SPADs). Background Technology

[0002] Modern electronic devices, such as cellular phones, cameras, and computers, often use digital image sensors. Image sensors (also called imagers) can be formed from a two-dimensional array of image-sensing pixels. In depth imaging applications, single-photon devices can be implemented to detect photons emitted from a source and reflected from a target, and to measure the precise target distance based on the time-of-flight (ToF) information of that photon. For example, a single-photon device can comprise an array of silicon photomultiplier tube (SiPM) devices. Each SiPM device can then consist of multiple single-photon avalanche diodes (SPADs). The multiple SPADs of a SiPM device can form the photosensitive region of the SiPM and provide an analog output signal.

[0003] The inventors of the embodiments of this disclosure have recognized that grouping multiple SPADs together into a single SiPM can result in voltage drops across the metal lines of the SiPM's common bias or common output line. The inventors of the embodiments of this disclosure have also recognized that such voltage drops can lead to degradation of the photon detection efficiency (PDE) uniformity of the SiPM and the imaging system in which the SiPM can be implemented. The embodiments of this disclosure can address one or more of these challenges. Summary of the Invention

[0004] According to a first aspect, a silicon photomultiplier tube (SiPM) is provided, comprising: a plurality of microcells coupled to a summing node of the SiPM, each of the plurality of microcells comprising: a single-photon avalanche diode; a passive quenching device coupled in series with the single-photon avalanche diode; and a current mirror configured to generate a microcell output current based on a current from the single-photon avalanche diode.

[0005] According to a second aspect, a silicon photomultiplier tube (SiPM) is provided, comprising: a plurality of microcells, each of the plurality of microcells having a microcell output coupled to a summing node of the SiPM, each of the plurality of microcells comprising: a single-photon avalanche diode; and a passive quenching device coupled in series with the single-photon avalanche diode; and a current mirror coupled to the summing node and configured to generate a SiPM output current based on the sum of microcell output currents received at the summing node.

[0006] According to a third aspect, an imaging system is provided, the imaging system comprising: an image processing circuit; and a semiconductor device communicatively coupled to the image processing circuit and including a plurality of silicon photomultiplier tubes (SiPMs), each SiPM including: a plurality of microcells, each of the plurality of microcells having a microcell output coupled to a summing node of the SiPM, each of the plurality of microcells including: a single-photon avalanche diode; and a passive quenching device coupled in series with the single-photon avalanche diode; and a current mirror coupled to the summing node and configured to generate a SiPM output current based on the sum of microcell output currents received at the summing node. Attached Figure Description

[0007] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0008] Figure 1 A schematic block diagram illustrating an example imaging system with a SPAD-based semiconductor device according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A schematic block diagram of an example positron emission tomography (PET) imaging system with SPAD-based semiconductor devices according to an embodiment of the present disclosure is illustrated.

[0010] Figure 3 A block diagram illustrating a pixel array according to an embodiment of the present disclosure and an associated readout circuit system for reading out image signals in an example SPAD-based semiconductor device is shown.

[0011] Figure 4 A circuit diagram of a silicon photomultiplier tube (SiPM) according to an embodiment of the present disclosure is illustrated.

[0012] Figure 5 A circuit diagram of a silicon photomultiplier tube (SiPM) according to an embodiment of the present disclosure is illustrated.

[0013] Figure 6 A circuit diagram of a silicon photomultiplier tube (SiPM) according to an embodiment of the present disclosure is illustrated.

[0014] Figure 7 A circuit diagram of a silicon photomultiplier tube (SiPM) according to an embodiment of the present disclosure is illustrated.

[0015] Figure 8 Example waveforms of signals within a SPAD-based microcell according to an embodiment of the present disclosure are illustrated. Detailed Implementation

[0016] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0017] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component, and this disclosure is not intended to distinguish between components with different names but the same form and function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including but not limited to". Additionally, the terms "coupled" or "coupled" are intended to mean a direct connection or an indirect connection. Thus, if a first device is coupled to a second device, the connection between the first device and the second device can be made through a direct connection or through an indirect connection via other devices and connections.

[0018] Imaging systems may include image sensors that sense light by converting impacting photons into pairs of electrons and holes collected in pixel photodiodes within a sensor array. After the accumulation cycle is complete, the collected charge can be converted into a voltage, which is supplied to the sensor's output terminals. In complementary metal-oxide-semiconductor (CMOS) image sensors, the charge-to-voltage conversion can be performed directly within the pixel itself, and analog pixel voltages can be passed to the output terminals via various pixel addressing and scanning schemes. Analog pixel voltages can also subsequently be converted into digital equivalents on-chip and processed in various ways in the digital domain.

[0019] On the other hand, the photon detection principle differs in single-photon avalanche diode (SPAD) devices. The photosensitive diode can be biased slightly above its reverse breakdown voltage, and when incident photons generate electron-hole pairs, the electron or hole carriers drift into the multiplication region and can initiate avalanche breakdown with the additional carriers being generated. Avalanche multiplication generates a current signal that can be detected by a readout circuitry system associated with the single-photon avalanche diode. The avalanche process can then be stopped or quenched by reducing the bias to below or equal to the diode's reverse breakdown voltage. Therefore, each single-photon avalanche diode may include passive and / or active quenching circuitry for quenching avalanches by reducing the bias.

[0020] SPAD devices can be used in a variety of ways. For example, in low-light applications, they can be simply used to count arriving photons. Another example is the ability of a SPAD device to measure the time of flight (ToF) of photons from a synchro light source to a scene object and back to the sensor; this time of flight (ToF) can be used to obtain a 3D image of the scene. See below for reference. Figure 1 and Figure 2 In further detail, SPAD-based semiconductor devices can be used in both, for example, LIDAR and PET imaging applications.

[0021] Figure 1 A schematic block diagram of an imaging system 10 having a SPAD-based semiconductor device 14 according to an embodiment of the present disclosure is illustrated. In some embodiments, the imaging system 10 may be an electronic device, such as a digital camera, computer, cellular phone, medical device, or other electronic device. The imaging system 10 may also be an imaging system for a vehicle. In some embodiments, the imaging system 10 may be used for LIDAR applications. The imaging system 10 may include one or more SPAD-based semiconductor devices 14, which may also be referred to as a device, semiconductor device, image sensor, or SPAD-based image sensor. One or more lenses 28 may optionally cover each SPAD-based semiconductor device 14. During operation, the lenses 28 may focus light onto one or more instances of the SPAD-based semiconductor device 14. The SPAD-based semiconductor device 14 may include SPAD-based image pixels that can convert incident light into digital data. The SPAD-based semiconductor device 14 may have any suitable number of SPAD-based image pixels, such as one hundred, one thousand, one million, or more.

[0022] The SPAD-based semiconductor device 14 may optionally include additional circuitry. For example, the SPAD-based semiconductor device 14 may include biasing circuitry such as a source follower load circuit. As other examples, the SPAD-based semiconductor device 14 may also include one or more of the following: sample and hold circuitry, amplifier circuitry, analog-to-digital converter (ADC) circuitry, time-to-digital converter (TDC) circuitry, data output circuitry, addressing circuitry, and / or buffer circuitry and memory.

[0023] The SPAD-based semiconductor device 14 is communicatively coupled to the image processing circuitry 16. Therefore, image data from the SPAD-based semiconductor device 14 can be provided to the image processing circuitry 16. The image processing circuitry 16 can perform image processing functions, including but not limited to autofocus, depth sensing, data formatting, white balance and exposure adjustment, video image stabilization, and / or face detection. For example, during autofocus operation, the image processing circuitry 16 can process data collected from the SPAD-based image pixels to determine the magnitude and direction of movement of one or more lenses 28 required to focus the object of interest. The image processing circuitry 16 can also process data acquired from the SPAD-based image pixels to determine a depth map of the scene.

[0024] Imaging system 10 can provide users with many advanced functions. For example, in a computer or advanced mobile phone, it can provide users with the ability to run user applications. To achieve these functions, imaging system 10 may include input-output devices 22, such as keypads, buttons, input-output ports, joysticks, and / or displays. Additional storage and processing circuitry systems, such as volatile and non-volatile memory, microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits, and / or other processing circuitry, may also be included in imaging system 10.

[0025] Input-output device 22 may include an output device that operates in conjunction with SPAD-based semiconductor device 14. For example, a light-emitting component may be included in an imaging system to emit light, such as infrared light or any other desired type of light. SPAD-based semiconductor device 14 may measure the reflection of light from an object to measure the distance to the object in a light detection and ranging (LIDAR) scheme.

[0026] Figure 2 A schematic block diagram illustrating an example positron emission tomography (PET) imaging system 50 including a SPAD-based semiconductor device 14 according to an embodiment of the present disclosure is shown. In some embodiments, the PET imaging system 50 may be a medical device, such as a PET scanner or other electronic device. The PET imaging system 50 may also be referred to as a SPAD-based imaging system or a SPAD-based PET imaging system.

[0027] The PET imaging system 50 may include one or more detector blocks 52. Each detector block 52 may include one or more detector units 54. Each detector unit 54 may include a corresponding SPAD-based semiconductor device 14 and a crystal 56. The crystal 56 may also be referred to as a scintillator. The crystal 56 may absorb ionizing radiation, such as gamma rays induced by radioactive tracers used, for example, in the PET imaging system. In response to the gamma rays, the crystal 56 may emit light in the visible spectrum. For example, the crystal 56 may emit blue light in response to the absorption of gamma rays. The crystal 56 may be formed using yttrium lutetium silicate (LYSO) or any material suitable for use as a scintillator.

[0028] One or more lenses may optionally cover each SPAD-based semiconductor device 14. During operation, the lenses can focus light from crystal 56 onto the SPAD-based semiconductor device 14. The SPAD-based semiconductor device 14 may include SPAD-based image pixels that can convert light from crystal 56 into digital data. In some embodiments, one or more blue-pass filters may also be used to allow blue light wavelengths to pass through while blocking infrared and other visible light wavelengths. For example, a universal blue-pass filter may be included within detector block 52 of PET imaging system 50 to allow blue light wavelengths to pass through while blocking infrared and other visible light wavelengths from reaching the SPAD-based semiconductor device 14.

[0029] Image data from the SPAD-based semiconductor device 14 can be provided to the image processing circuitry 66. The image processing circuitry 66 can be used to perform image processing functions of the PET imaging system 50. In some cases, some or all of the control circuitry within the PET imaging system 50 may be integrated with the image processing circuitry 66. Additionally, the PET imaging system 50 can provide users with a number of advanced functions. To implement these functions, the PET imaging system 50 may include one or more input-output devices 62, such as keypads, buttons, input-output ports, joysticks, and displays (such as touch-sensitive displays). Additional storage and processing circuitry, such as volatile and non-volatile memory, microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits, and / or other processing circuitry, may also be included in the PET imaging system 50.

[0030] Figure 3 A block diagram illustrating a pixel array according to an embodiment of the present disclosure and an associated readout circuitry system for reading out image signals in an example SPAD-based semiconductor device 14 is shown. Figure 3As shown, the SPAD-based semiconductor device 14 may include an array 120 of SPAD-based image pixels 202 arranged in rows and columns. The array 120 may contain, for example, hundreds or thousands of rows and hundreds or thousands of columns of SPAD-based image pixels 202. In some embodiments, for example, each SPAD-based image pixel 202 may be coupled to an analog pulse counter that generates a corresponding pixel voltage based on received photons. In other embodiments, each SPAD-based image pixel 202 may be coupled to a digital pulse counter whose digital output code corresponds to the number of photons in a defined time window. Each SPAD-based image pixel 202 may additionally or alternatively be coupled to a time-to-voltage converter circuit. In both types of readout circuitry, the voltage may be stored on a pixel capacitor and later scanned line by line, or the digital code may be stored in memory and later scanned line by line. In the case of a SiPM device, both types of readout circuitry may be coupled to the output of an image pixel, which may be formed by multiple SPAD-based microcells and connected together to form a single output pixel. Control and processing circuitry 124 may be coupled to row control circuitry 126 and readout circuitry 128. Readout circuitry 128 may also be referred to as column control circuitry, column decoder circuitry, processing circuitry, or image readout circuitry. Row control circuitry 126 may receive row addresses from control and processing circuitry 124 and supply corresponding row control signals to SPAD-based image pixels 202 via row control path 130. One or more wires (such as column lines 132) may be coupled to each column of SPAD-based image pixels 202 in array 120. Column lines 132 may be used to read out image signals from SPAD-based image pixels 202 and to supply bias signals (such as bias voltage and / or bias current) to SPAD-based image pixels 202. During pixel readout operation, row control circuitry 126 may be used to select a pixel row in array 120, and image signals generated by SPAD-based image pixels 202 in that pixel row may be read out along column lines 132.

[0031] The readout circuitry 128 can receive analog or digital image signals from SPAD-based image pixels 202 via column lines 132. The readout circuitry 128 may include sample-and-hold circuitry, amplifier circuitry, analog-to-digital converter (ADC) circuitry, time-to-digital converter (TDC) circuitry, bias circuitry, column memory, latching circuitry for selectively enabling or disabling column circuitry, or other circuitry coupled to one or more pixel columns in array 120 for operating the SPAD-based image pixels 202 and for reading signals from the SPAD-based image pixels 202. The ADC circuitry in the readout circuitry 128 can convert analog pixel values ​​received from array 120 into corresponding digital pixel values ​​(also referred to as digital image data or digital pixel data). Alternatively, the ADC circuitry may be incorporated into each SPAD-based image pixel 202. The readout circuitry 128 can supply digital pixel data to the control and processing circuitry 124 via path 125 for pixels in one or more pixel columns.

[0032] The example of the SPAD-based semiconductor device 14 that enables the readout circuitry system to read signals from SPAD-based image pixels in a line-by-line manner is merely illustrative. In other embodiments, the readout circuitry system in the image sensor may consist only of digital pulse counting circuitry coupled to each SPAD-based image pixel. Any other desired readout circuitry arrangement may be used.

[0033] In some embodiments, each SPAD-based image pixel 202 in array 120 may be a back-illuminated (BSI) SPAD-based image pixel. In some embodiments, array 120 may be part of a multi-die arrangement, wherein the SPAD-based image pixels 202 may be formed in a first substrate, and some or all of the corresponding control and readout circuitry may be formed in a second and / or third substrate that may be included in a stack with the first substrate.

[0034] Because SPAD devices can detect individual incident photons, they can effectively image scenes with low light levels. Each SPAD device can detect how many photons are received within a given time period. However, whenever a photon is received and an avalanche current begins, the SPAD device must be quenched and reset before it is ready to detect another photon. As the incident light level increases, the dynamic range of the SPAD device may be limited by the reset time. For example, once the incident light level exceeds a given level, the SPAD device may be triggered immediately after reset. Therefore, to increase the dynamic range of SPAD-based semiconductor devices using SPAD-based image pixels, each SPAD-based image pixel can be implemented by a silicon photomultiplier tube (SiPM) with multiple microcells, each of which includes a SPAD device. The readout circuitry system for the SiPM measures the combined output current from all the SPAD-based microcells. In this way, the dynamic range of each SPAD-based image pixel in the imaging system can be increased.

[0035] Figure 4 A circuit diagram of a silicon photomultiplier tube (SiPM) 402 according to an embodiment of the present disclosure is shown. For example... Figure 4 As shown, SiPM 402 may include N SPAD-based microcells, including microcells 410a, 410b to 410n. For the purposes of this disclosure, microcells 410a, 410b to 410n may also be individually referred to as microcell 410 or collectively as microcells 410. A SiPM such as SiPM 402 can be implemented using any suitable N microcells 410. For example, a SiPM such as SiPM 402 can be implemented using tens, hundreds, thousands or more orders of magnitude of microcells 410.

[0036] Microcells 410a, 410b to 410n may each include a single-photon avalanche diode 420 and a quenching device 430. In some embodiments, the quenching device 430 may be a passive quenching device, such as a resistor. Figure 4 As shown, each instance of the microcell 410 can be coupled in parallel with each other between a negative bias power supply - VBIAS and a load resistor 490 coupled to ground GND. The voltage of the negative bias power supply - VBIAS can be a negative voltage sufficient to bias the single-photon avalanche diode 420 to a value exceeding the reverse breakdown voltage of the single-photon avalanche diode 420.

[0037] When the single-photon avalanche diode 420 is biased above its reverse breakdown voltage, the incident photons of light received by the single-photon avalanche diode 420 can generate electron-hole pairs, which in turn can initiate avalanche breakdown and generate additional charge carriers. Avalanche multiplication can generate a current signal. When the current generates a voltage drop across the quenching device 430, the avalanche process can then be stopped or quenched, thereby reducing the bias voltage across the single-photon avalanche diode 420 below its reverse breakdown voltage and quenching the avalanche.

[0038] like Figure 4 As shown, the load resistor 490 can receive the combined current from each microcell 410 in the SiPM 402. Therefore, a single output voltage VOUT can be generated by the SiPM 402 and read by the readout circuit 495. In this way, the dynamic range of SPAD-based image pixels can be improved by utilizing the SiPM to implement SPAD-based image pixels. For example, each individual instance of the microcell 410 in the SiPM 402 can have an associated probability of triggering an avalanche current when an incident photon is received. The probability of triggering an avalanche current depends on a first probability of generating an electron when a photon arrives at the diode and a second probability of an electron triggering an avalanche current. The total probability of an electron triggering an avalanche current can be referred to as the photon detection efficiency based on the microcell. By grouping multiple microcells 410 together in the SiPM 402, a more accurate measurement of the incoming incident light can be provided.

[0039] When grouping multiple instances of microcell 410 together, various routing parasitic effects may occur, such as Figure 4 The parasitic resistance Rp is shown. Since the current signals are generated by one or more instances of microcell 410 at a given time, these current signals may cause voltage drops across various parasitic resistances Rp. The bias voltage of one or more other instances of microcell 410 may therefore be reduced, thereby degrading the uniformity of photon detection efficiency (PDE) on the SiPM 402 and in SPAD-based semiconductor devices that may include multiple instances of SiPM 402.

[0040] The PDE uniformity of SPAD-based semiconductor devices can be improved by using one or more current mirrors to bias the single-photon avalanche diodes of individual SPAD-based microcells within a SiPM, which includes multiple SPAD-based image pixels each implemented in the SiPM. In some embodiments, each microcell of the SiPM may include a single-photon avalanche diode, a quenching device coupled in series with the single-photon avalanche diode, and a current mirror configured to receive a current signal from the single-photon avalanche diode and generate a microcell output current based on the current signal from the single-photon avalanche diode. In such embodiments, the respective microcell output currents can be summed at a common output channel of the SiPM. Including a current mirror in each microcell allows each microcell to be directly biased, thereby reducing the negative impact of any parasitic routing resistance on the PDE uniformity on the SiPM and on the SPAD-based semiconductor device in which the SiPM can be implemented. Furthermore, the current mirror can act as a buffer that decouples the single-photon avalanche diode from the common output channel of the SiPM. In addition, a current mirror can be used to amplify the current signal from the single-photon avalanche diode of each microcell, thereby improving the electrical performance of each microcell and SiPM.

[0041] Figure 5 A circuit diagram of a silicon photomultiplier tube (SiPM) 502 according to an embodiment of the present disclosure is illustrated. In some embodiments, the above references... Figure 3 Each SPAD-based image pixel 202 of the SPAD-based semiconductor device 14 described can be implemented using an instance of SiPM 502.

[0042] like Figure 5 As shown, the SiPM 502 may include multiple microcells. For example, the SiPM 502 may include N SPAD-based microcells, including microcells 510a, 510b to 510n. For the purposes of this disclosure, microcells 510a, 510b to 510n may also be individually referred to as microcell 510 or collectively as microcells 510. The SiPM 502 may be implemented using any suitable N microcells 510. For example, the SiPM 502 may be implemented using tens, hundreds, thousands or more microcells 510.

[0043] like Figure 5As shown, each of the plurality of microcells 510a, 510b to 510n may include a single-photon avalanche diode 520, a quenching device 530, and a current mirror 540. The single-photon avalanche diode 520 may have an anode coupled to a negative voltage bias power supply -VBR and a cathode coupled to the quenching device 530. In some embodiments, the quenching device 530 may be a passive quenching device (such as a resistor) and may be coupled in series with the single-photon avalanche diode 520. Specifically, the quenching device 530 may be coupled in series between the single-photon avalanche diode 520 and the current mirror 540.

[0044] The current mirror 540 may include an input transistor 545 and an output transistor 546. In some embodiments, the input transistor 545 and the output transistor 546 may be p-type metal-oxide-semiconductor field-effect transistors (p-type MOSFETs or PMOS transistors). The input transistor 545 and the output transistor 546 may be configured such that the output transistor 546 generates an output current that mirrors the current received by the input transistor 545. For example, the input transistor 545 may be diode-coupled, wherein the drain of the input transistor 545 is coupled together with its gate. The gate of the output transistor 546 may be coupled to the drain and gate of the input transistor 545. Additionally, the respective sources of both the input transistor 545 and the output transistor 546 may be coupled together and coupled to a positive voltage bias power supply VEX.

[0045] In some implementations, the negative voltage bias supply -VBR can be set to a negative voltage equal to the reverse breakdown voltage of the single-photon avalanche diode 520. Furthermore, the positive voltage bias supply VEX can be set to a positive voltage level sufficient to provide headroom for the current mirror 540 and to provide an excess voltage bias higher than the reverse breakdown voltage of the single-photon avalanche diode 520. Using a large negative voltage to -VBR and a smaller positive voltage to VEX provides the voltage difference required to bias the single-photon avalanche diode 520 above its reverse breakdown point, while also allowing the use of low-voltage transistors to implement the input transistor 545 and output transistor 546 of the current mirror 540.

[0046] When the single-photon avalanche diode 520 is biased above its reverse breakdown point, incident photons of light received by the single-photon avalanche diode 520 can generate electron-hole pairs, which in turn can initiate avalanche breakdown and generate additional charge carriers. Avalanche multiplication can generate a current signal. When the current generates a voltage drop across the quenching device 530, the avalanche process can then be stopped or quenched, thereby reducing the bias voltage across the single-photon avalanche diode 520 below its reverse breakdown voltage to quench the avalanche. The current mirror 540 can receive the current signal generated by the single-photon avalanche diode 520 during avalanche. The current mirror 540 can be configured to generate the microcell output current I based on the current from the single-photon avalanche diode 520. CELL Specifically, the input transistor 545 can be configured to receive a current signal from the single-photon avalanche diode 520, and the output transistor 546 can be mirrored to generate a microcell output current I at the microcell output 580. CELL .

[0047] like Figure 5 As shown, the micro-unit output 580 of each of the multiple micro-units 510a, 510b to 510n can be coupled to the summing node 585. Therefore, the micro-unit output current I of each of the multiple micro-units 510a, 510b to 510n can be coupled at the summing node 585. CELL These are combined to form the output current IOUT of the SiPM 502. In some embodiments, the SiPM 502 may also include a resistor 590 that is coupled to a summing node 585 to receive the microcell output current I from each of the plurality of microcells 510a, 510b to 510n. CELL Resistor 590 can therefore generate the output voltage VOUT based on the sum of the microcell output currents from each of the plurality of microcells 510a, 510b to 510n. In some embodiments, readout circuit 595 can read the output voltage VOUT. In other embodiments, resistor 590 can be omitted, and readout circuit 595 can be configured to directly read the output current IOUT of SiPM 502.

[0048] The design of multiple microcells 510a, 510b to 510n offers several advantages to the SiPM 502. For example, each of the multiple microcells 510a, 510b to 510n can be directly biased by a negative voltage bias supply -VBR and a positive voltage bias supply VEX. The negative parasitic effects that an avalanche current in one of the multiple microcells 510a, 510b to 510n might cause to other microcells can thus be eliminated or reduced. Furthermore, for each of the multiple microcells 510a, 510b to 510n, a current mirror 540 can be used as a buffer that decouples the single-photon avalanche diode 520 from the common output channel of the SiPM 502 at the summing node 585. Therefore, the single-photon avalanche diode 520 can buffer any output capacitance present at the output of the SiPM 502. Additionally, for each of the multiple microcells 510a, 510b to 510n, the current mirror 540 can be configured to amplify the current from the single-photon avalanche diode 520 to generate the microcell output current I. CELL In some implementations, the first aspect ratio of the channel region of the output transistor 546 may be greater than the second aspect ratio of the channel region of the input transistor 545. For example, the output transistor 546 may be configured with a channel region whose aspect ratio is 2, 5, 10, or more times that of the channel region of the input transistor 545. Therefore, the output transistor 546 may generate a microcell output current I that is 2, 5, 10, or more times larger than the current signal received by the input transistor 545 from the single-photon avalanche diode 520. CELL This amplification provides a higher signal-to-noise ratio for the readout circuit 595.

[0049] The performance of the various examples of silicon photomultiplier tubes (SiPMs) disclosed herein can be further improved by including additional control circuitry that can control the enabling and disabling of each microcell of the SiPM. For example, in the various examples disclosed herein, the microcells of the SiPM may include an enable transistor coupled in series with the single-photon avalanche diode of the microcell to enable and disable the current path of the single-photon avalanche diode. The various examples of microcells disclosed herein may also include a disable transistor coupled between ground and the cathode of the single-photon avalanche diode. Thus, the disable transistor reduces the bias voltage at the cathode of the single-photon avalanche diode, and thereby reduces the power consumption of the microcells when certain groups of microcells or the SiPM are disabled or not required by the imaging system.

[0050] Furthermore, various examples of microcells disclosed herein may include precharge transistors. As mentioned above, the dynamic range of SPAD-based devices can be limited in part by the avalanche current that will be quenched and the time required to reset the bias of the SPAD-based device before it is ready to detect another photon. Precharge transistors can improve the dynamic range of a SiPM, which includes microcells, by rapidly charging the parasitic capacitance at the cathode of the single-photon avalanche diode to the desired bias voltage, thereby biasing the single-photon avalanche diode above its reverse breakdown voltage. This is achieved faster than by the current path from the positive voltage bias supply through the current mirror and the quenching device. Therefore, using precharge transistors improves the speed at which each microcell of the SiPM is reset before it is ready to detect another photon.

[0051] Figure 6 A circuit diagram of a silicon photomultiplier tube (SiPM) 602 according to an embodiment of the present disclosure is illustrated. In some embodiments, the above references... Figure 3 Each SPAD-based image pixel 202 of the SPAD-based semiconductor device 14 described can be implemented using an instance of SiPM 602.

[0052] like Figure 6 As shown, SiPM 602 may include multiple microcells. For example, SiPM 602 may include N SPAD-based microcells, including microcells 610a, 610b to 610n. For the purposes of this disclosure, microcells 610a, 610b to 610n may also be individually referred to as microcell 610 or collectively as microcell 610. SiPM 602 may be implemented using any suitable N microcells 610. For example, SiPM 602 may be implemented using tens, hundreds, thousands or more microcells 610.

[0053] like Figure 6 As shown, each of the plurality of microcells 610a, 610b to 610n may include a single-photon avalanche diode 520, a quenching device 530, and a current mirror 540. The single-photon avalanche diode 520, the quenching device 530, and the current mirror 540 may each be located within the plurality of microcells 610a, 610b to 610n as described above. Figure 5 The microcells 510a, 510b to 510n operate in a similar manner to that described below. As described in further detail below, during operation of the microcell, the enable transistor 654 and the quench transistor 652 are typically driven into a conducting state, thereby enabling the current path between the single-photon avalanche diode 520 and the current mirror 540. Therefore, the current mirror 540 can receive the current signal generated by the single-photon avalanche diode 520 during avalanche. The current mirror 540 can generate the microcell output current I based on the current from the single-photon avalanche diode 520.CELL Specifically, the input transistor 545 can be configured to receive a current signal from the single-photon avalanche diode 520, and the output transistor 546 can be mirrored to generate a microcell output current I at the microcell output 680. CELL .

[0054] Similarly, Figure 6 As shown, the plurality of microcells 610a, 610b to 610n may include additional circuitry to enable, disable, precharge, and actively quench the single-photon avalanche diode 520. For example, as described in further detail below, each of the plurality of microcells 610a, 610b to 610n may include one or more of an enable transistor 654, a quench transistor 652, a precharge transistor 664, and a disable transistor 662.

[0055] Enable transistor 654 may be series coupled to single-photon avalanche diode 520 and configured to enable the current path between single-photon avalanche diode 520 and current mirror 540. In some embodiments, enable transistor 654 may be a PMOS transistor. The source of enable transistor 654 may be coupled to current mirror 540, and specifically to the gate and drain of input transistor 545 of current mirror 540. The drain of enable transistor 654 may be coupled to quench transistor 652, which, as described in further detail below, may be series coupled to the current path formed by quenching device 530 and single-photon avalanche diode 520. Although enable transistor 654 in Figure 6 The implementation is shown as indirectly coupled to quenching device 530 and single-photon avalanche diode 520, but enable transistor 654 may be directly or indirectly coupled to and in series with single-photon avalanche diode 520 and / or quenching device 530 to enable the current path between single-photon avalanche diode 520 and current mirror 540. For example, enable transistor 654 may receive a logic low enable signal EN at its gate to put enable transistor 654 into a conducting state, thereby enabling the current path between single-photon avalanche diode 520 and current mirror 540. Conversely, a logic high signal at the gate of enable transistor 654 may disable the current path between single-photon avalanche diode 520 and current mirror 540.

[0056] A quench transistor 652 may be coupled in series between a single-photon avalanche diode 520 and a current mirror 540. In some embodiments, the quench transistor 652 may be a PMOS transistor. The source of the quench transistor 652 may be coupled to the drain of an enable transistor 654, which, as described above, may in turn be coupled to the current mirror 540. The drain of the quench transistor 652 may be coupled to a quenching device 530, which may in turn be coupled in series with the avalanche diode 520. Although the quench transistor 652 is in Figure 6 The embodiment is shown as indirectly coupled to the single-photon avalanche diode 520 via quenching device 530, but quenching transistor 652 may be directly or indirectly coupled to and in series with the single-photon avalanche diode 520. In some embodiments, quenching transistor 652 may be configured to provide active quenching of the single-photon avalanche diode 520. For example, the gate of quenching transistor 652 may typically be held at a logic low level to keep quenching transistor 652 in the on state. Then, after avalanche has been activated and avalanche has been detected in the single-photon avalanche diode 520, a logic high active suppression signal ACT may be applied to the gate of quenching transistor 652 to turn quenching transistor 652 off. By turning quenching transistor 652 off, the voltage bias of single-photon avalanche diode 520 may rapidly drop below the reverse breakdown voltage of single-photon avalanche diode 520, thereby quenching avalanche. After the avalanche has been quenched, the gate of the quench transistor 652 can return to its normal logic low level.

[0057] In some implementations, quenching transistor 652 may be combined with quenching device 530 to quench avalanche of single-photon avalanche diode 520. For example, quenching transistor 652 may provide the active quenching described above, while quenching device 530 may be implemented by a resistor in some implementations, which may provide the active quenching described above. Figure 5 The passive quenching described. In other embodiments, quenching transistor 652 may be used instead of quenching device 530. In such other embodiments, quenching device 530 may be omitted, and quenching transistor 652 may be directly coupled to single-photon avalanche diode 520.

[0058] The precharge transistor 664 can be configured to precharge the single-photon avalanche diode 520 with a bias voltage higher than the reverse breakdown voltage of the single-photon avalanche diode 520. For example, the precharge transistor 664 can be a PMOS transistor with its source coupled to a positive voltage bias supply VEX, its drain coupled to the cathode of the single-photon avalanche diode 520, and its gate coupled to receive a precharge signal PRE. As mentioned above, the dynamic range of a SPAD-based device may be limited in part by the avalanche current that will be quenched and the time required to reset the bias of the SPAD-based device before it is ready to detect another photon. Figure 6 As shown, each instance of microcells 610a, 610b to 610n may include a precharge transistor 664 to improve the reset time, thereby improving the dynamic range of the SiPM 602 and the image sensor in which the SiPM 602 may be implemented. For example, after an avalanche has been detected and quenched, a logic low precharge signal PRE may be applied to the gate of the precharge transistor 664 for a short duration to drive the precharge transistor 664 to be in an on state for a short duration. During the on state of the precharge transistor 664, the cathode of the single-photon avalanche diode 520 may be charged to a bias voltage equal to VEX, thereby biasing the single-photon avalanche diode 520 above the reverse breakdown voltage. The precharge transistor 664 may charge parasitic capacitance and thus increase the bias voltage at the cathode of the single-photon avalanche diode 520 faster than by means of a current path from VEX through a current mirror 540, an enable transistor 654, a quench transistor 652, and a quench device 530. After the cathode of the single-photon avalanche diode 520 is precharged, the precharge transistor 664 can be driven to the off state so as not to interfere with the detection of subsequent avalanche current in the single-photon avalanche diode 520.

[0059] A disable transistor 662 may be coupled to the cathode of a single-photon avalanche diode 520 and may be configured to disable the single-photon avalanche diode 520. For example, the disable transistor 662 may be configured to reduce the bias voltage applied to the single-photon avalanche diode 520, thereby disabling the operation of the microcell. In some embodiments, the disable transistor 662 may be an n-type metal-oxide-semiconductor field-effect transistor (n-type MOSFET or NMOS transistor). And in some embodiments, the disable transistor 662 may have a drain coupled to the cathode of the single-photon avalanche diode 520, a source coupled to ground (GND), and a gate coupled to receive a disable signal DIS. During operation of the SiPM 602 or an imaging system in which the SiPM 602 is implemented, it may be desirable to disable one or more of a group of microcells 610a, 610b to 610n when the imaging system is not needed or is not in use. During these times, a logic high disable signal DIS may be applied to the gate of the disable transistor 662 to drive the disable transistor 662 into an on state. Disabling transistor 662 ensures that the voltage at the cathode of the single-photon avalanche diode 520 does not rise above, for example, ground (GND). More specifically, disabling transistor 662 ensures that the bias voltage across the single-photon avalanche diode 520 does not exceed its reverse breakdown voltage. Therefore, disabling transistor 662 prevents or reduces the likelihood of the single-photon avalanche diode 520 entering an avalanche in response to incident photons of light. Thus, when the imaging system does not require or use the disabling transistor 662 for each microcell 610a, 610b to 610n, the power consumption of one or more of the multiple microcells 610a, 610b to 610n can be reduced.

[0060] like Figure 6 As shown, the micro-unit output 680 of each of the multiple micro-units 610a, 610b to 610n can be coupled to the summing node 685. Therefore, the micro-unit output current I of each of the multiple micro-units 610a, 610b to 610n can be coupled at the summing node 685. CELL These are added together to form the output current IOUT of the SiPM 602. In some embodiments, the SiPM 602 may also include a resistor 690 that is coupled to a summing node 685 to receive the microcell output current I from each of the plurality of microcells 610a, 610b to 610n. CELL Resistor 690 can therefore output current I based on each of the multiple microcells 610a, 610b to 610n. CELLThe sum of these values ​​generates the output voltage VOUT. In some embodiments, the readout circuit 695 reads the output voltage VOUT. In other embodiments, resistor 690 may be omitted, and the readout circuit 695 may be configured to directly read the output current IOUT of the SiPM 602.

[0061] The design of multiple microcells 610a, 610b to 610n offers several advantages to the SiPM 602. For example, each of the multiple microcells 610a, 610b to 610n can be directly biased by a negative voltage bias supply -VBR and a positive voltage bias supply VEX. The negative parasitic effects that an avalanche current in one of the multiple microcells 610a, 610b to 610n might cause to other microcells can thus be eliminated or reduced. Furthermore, for each of the multiple microcells 610a, 610b to 610n, a current mirror 540 can be used as a buffer that decouples the single-photon avalanche diode 520 from the common output channel of the SiPM 602 at the summing node 685. Therefore, the single-photon avalanche diode 520 can buffer any output capacitance present at the output of the SiPM 602. Additionally, for each of the multiple microcells 610a, 610b to 610n, the current mirror 540 can be configured to amplify the current from the single-photon avalanche diode 520 to generate the microcell output current I. CELL In some implementations, the first aspect ratio of the channel region of the output transistor 546 may be greater than the second aspect ratio of the channel region of the input transistor 545. For example, the output transistor 546 may be configured with a channel region whose aspect ratio is 2, 5, 10, or more times that of the channel region of the input transistor 545. Therefore, the output transistor 546 may generate a microcell output current I that is 2, 5, 10, or more times larger than the current signal received by the input transistor 545 from the single-photon avalanche diode 520. CELL This amplification provides a higher signal-to-noise ratio for the readout circuit 695.

[0062] Figure 7 A circuit diagram of a silicon photomultiplier tube (SiPM) 702 according to an embodiment of the present disclosure is illustrated. In some embodiments, the above references... Figure 3 Each SPAD-based image pixel 202 of the SPAD-based semiconductor device 14 described can be implemented using an instance of SiPM 702.

[0063] like Figure 7As shown, the SiPM 702 may include a current mirror 740 and N SPAD-based microcells, including, for example, microcells 710a, 710b to 710n. For the purposes of this disclosure, microcells 710a, 710b to 710n may also be individually referred to as microcell 710 or collectively as microcell 710. The SiPM 702 may be implemented using any suitable N microcells 710. For example, the SiPM 702 may be implemented using tens, hundreds, thousands or more orders of magnitude of microcells 710.

[0064] In some implementations, each of the plurality of microcells 710a, 710b to 710n may have a microcell output 780 coupled to a summing node 785 of the SiPM 702. Each of the plurality of microcells 710a, 710b to 710n may include a single-photon avalanche diode 520, a quenching device 530, and an enable transistor 654, a quenching transistor 652, a precharge transistor 664, and a disable transistor 662. The single-photon avalanche diode 520, the quenching device 530, and the enable transistor 654, the quenching transistor 652, the precharge transistor 664, and the disable transistor 662 may each be referenced above. Figure 5 and Figure 6 The operation is carried out in a similar manner to the description. However, as... Figure 7 As shown, in some embodiments, microcells 710a, 710b, and 710c can output current signals from their single-photon avalanche diodes 520 as the microcell output current I at microcell output 780. CELL Instead of including a current mirror within each microcell, the quenching transistor 652 can be described as being series-coupled between the single-photon avalanche diode 520 and the microcell output 780 for the purposes of this disclosure. Similarly, the enabling transistor 654 can be described as being series-coupled between the single-photon avalanche diode 520 and the microcell output 780. The microcell output 780 of each of the plurality of microcells 710a, 710b to 710n can then be coupled together at the summing node 785. As described in further detail below, the current mirror 740 can mirror the sum of the respective microcell output currents received at the summing node 785.

[0065] A current mirror 740 may be coupled to a summing node 785 and may be configured to generate a SiPM output current IOUT based on the sum of the corresponding microcell output currents received at the summing node 785. For example, the current mirror 740 may include an input transistor 745 and an output transistor 746. In some embodiments, the input transistor 745 and the output transistor 746 may be PMOS transistors. The input transistor 745 and the output transistor 746 may be configured such that the output transistor 746 generates an output current that mirrors the current received by the input transistor 745. For example, the input transistor 745 may be diode-coupled, with its drain coupled to its gate. The gate of the output transistor 746 may be coupled to both the drain and gate of the input transistor 745. Additionally, the respective sources of both the input transistor 745 and the output transistor 746 may be coupled together and coupled to a positive voltage bias supply VEX. Therefore, the current mirror 740 may reflect the corresponding microcell output current IOUT received at the summing node 785. CELL The sum of these two values ​​is used to generate the SiPM output current IOUT.

[0066] Therefore, the current mirror 740 enables the corresponding microcell output current I received at the summing node 785 to be applied. CELL The sum of these values ​​is mirrored to generate the SiPM output current IOUT. In some embodiments, the first aspect ratio of the channel region of the output transistor 746 may be greater than the second aspect ratio of the channel region of the input transistor 745. For example, the output transistor 746 may be configured with a channel region whose aspect ratio is 2, 5, 10, or more times that of the channel region of the input transistor 745. Therefore, the output transistor 746 may generate a SiPM output current IOUT that is 2, 5, 10, or more times larger than the sum of the corresponding microcell output currents received by the input transistor 545 at the summing node 785. This amplification can provide a greater signal-to-noise ratio for the readout circuit 795.

[0067] In some embodiments, the SiPM 702 may further include a resistor 790 coupled to the output of the current mirror 740 to receive the SiPM output current IOUT. The resistor 790 can thus generate an output voltage VOUT based on the SiPM output current IOUT. In some embodiments, a readout circuit 795 can read the output voltage VOUT. In other embodiments, the resistor 790 may be omitted, and the readout circuit 795 may be configured to directly read the SiPM output current IOUT of the SiPM 702.

[0068] In some implementations, the negative voltage bias supply -VBR can be set to a negative voltage equal to the reverse breakdown voltage of the single-photon avalanche diode 520. Furthermore, the positive voltage bias supply VEX can be set to a positive voltage level sufficient to provide headroom for the current mirror 740 and to provide an excess voltage bias higher than the reverse breakdown voltage of the single-photon avalanche diode 520. Using a large negative voltage to -VBR and a smaller positive voltage to VEX provides the voltage difference required to bias the single-photon avalanche diode 520 above its reverse breakdown voltage, while also allowing the use of low-voltage transistors to implement the input transistor 745 and output transistor 746 of the current mirror 740.

[0069] The design of the SiPM 702, including a current mirror 740 and multiple microcells 710a, 710b to 710n, offers several advantages. For example, the current mirror 740 can act as a buffer that decouples the single-photon avalanche diode 520 in each of the multiple microcells 710a, 710b to 710n from the common output channel of the SiPM 702. Therefore, the single-photon avalanche diode 520 of each of the multiple microcells 710a, 710b to 710n can be buffered from any output capacitance present at the output of the SiPM 702. Additionally, as described above, the current mirror 740 can be configured to output current I to each microcell. CELL The sum is amplified to summarize the SiPM output current IOUT. This amplification provides a higher signal-to-noise ratio for the readout circuit 795.

[0070] Additionally, during operation of the SiPM 702 or an imaging system implementing the SiPM 702, it may be desirable to disable one or more microcells from a group of microcells 710a, 710b to 710n when the imaging system is not needed or not in use. During these times, and for any one or more microcells in the selected group, a logic high disable signal DIS can be applied to drive disable transistor 662 to the on state. Disable transistor 662 thus ensures that the voltage at the cathode of the single-photon avalanche diode 520 does not rise above, for example, ground GND. More specifically, disable transistor 662 ensures that the bias voltage across the single-photon avalanche diode 520 does not exceed the reverse breakdown voltage of the single-photon avalanche diode 520. Therefore, disable transistor 662 prevents or reduces the likelihood of the single-photon avalanche diode 520 entering an avalanche in response to incident photons of light. Thus, the disable transistor 662 for each microcell 710a, 710b to 710n can reduce its power consumption when the imaging system does not need or is not using any disabled microcells.

[0071] Figure 8Example waveforms of signals within a SPAD-based microcell according to an embodiment of this disclosure are illustrated. For example, Figure 7 The waveforms show the signals within each of the multiple micro-units 710a, 710b to 710n, as referenced above. Figure 7 As stated above.

[0072] like Figure 8 As shown and especially Figure 8 Within a 1μs timeframe, the disable signal DIS transitions from a logic high to a logic low state, driving the disable transistor 662 to the off state. After the disable transistor 662 transitions to the off state, the single-photon avalanche diode 520 can then be precharged, and the microcell can be enabled for detection. For example, when the disable signal DIS transitions low, the precharge signal PRE can be pulsed low for a short duration, driving the precharge transistor 664 to the on state for a short duration. Therefore, the cathode voltage V of the single-photon avalanche diode 520 can be... CATHODE Rapidly charge to or near the positive bias supply voltage level VEX. With the anode of the single-photon avalanche diode 520 held at the negative bias supply -VBR, the cathode voltage V of the single-photon avalanche diode 520... CATHODE The rapid pre-charge provides fast biasing of the single-photon avalanche diode 520 at voltage levels greater than its reverse breakdown voltage. After pre-charging the cathode of the single-photon avalanche diode 520, the pre-charge transistor 664 can return to the off state so as not to interfere with the detection of subsequent avalanche current in the single-photon avalanche diode 520. Subsequently, the enable signal EN can transition from a logic high state to a logic low state to drive the enable transistor 654 into the on state, thereby enabling the microcell to be detected. Although in Figure 8 It is not explicitly shown, but the quenching transistor 652 can also be driven into the on state, thereby at least in Figure 8 The 1μs timeframe is used to further allow the microcells to operate in the enabled state.

[0073] As shown in the figure, for example in Figure 8 At a time interval of 2 μs, the single-photon avalanche diode 520 can receive photons of light. When the single-photon avalanche diode 520 is biased above its reverse breakdown voltage, the incident photons of light received by the single-photon avalanche diode 520 can generate electron-hole pairs, which can then initiate avalanche breakdown and generate additional charge carriers. Avalanche multiplication can generate a current signal, which can be used as the microcell output current I. CELL Output from the microcell. Generated by a single-photon avalanche diode 520 and used as the microcell output current I. CELLThe output current can then cause a voltage drop across quenching device 530 and / or quenching transistor 652. Therefore, the cathode voltage V of single-photon avalanche diode 520... CATHODE This can be reduced, thereby lowering the bias voltage across the single-photon avalanche diode 520 below its breakdown voltage to quench the avalanche. As the avalanche is quenched, the current generated by the single-photon avalanche diode 520 and used as the microcell output current I... CELL The output current can return to zero, and the cathode voltage V CATHODE It can return to a bias level close to VEX.

[0074] When not used in an imaging system in which the SiPM 702 is implemented, one or more micro-units among the multiple micro-units 710a, 710b to 710n can be disabled. For example, as Figure 8 As shown in the 3μs time interval, the enable signal EN can return to high to drive the enable transistor 654 to the off state, thereby disabling the current path of the single-photon avalanche diode 520. Alternatively, the disable signal DIS can also be forced high to drive the disable transistor 662 to the on state, thereby reducing the cathode voltage V of the single-photon avalanche diode 520. CATHODE Discharge to ground (GND). This is achieved by increasing the cathode voltage V of the single-photon avalanche diode 520. CATHODE Discharging to ground (GND) reduces the total bias applied across the single-photon avalanche diode 520 and decreases the chance of the single-photon avalanche diode 520 entering an avalanche in response to incident photons of light. Therefore, the power consumption of the microcell can be reduced when it is in a disabled state.

[0075] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A silicon photomultiplier tube (SiPM), comprising: Multiple micro-units coupled to the summing node of the SiPM, each of the multiple micro-units comprising: Single-photon avalanche diode; A passive quenching device, wherein the passive quenching device is coupled in series with the single-photon avalanche diode; and A current mirror configured to generate a microcell output current based on the current from the single-photon avalanche diode.

2. The SiPM of claim 1, further comprising a resistor coupled to the summing node to receive the microcell output current from each of the plurality of microcells and generate an output voltage.

3. The SiPM of claim 1, wherein the current mirror is configured to amplify the current from the single-photon avalanche diode to generate the microcell output current.

4. The SiPM of claim 1, wherein each of the plurality of microcells further comprises a precharge transistor configured to precharge the single-photon avalanche diode with a bias voltage higher than the reverse breakdown voltage of the single-photon avalanche diode.

5. The SiPM of claim 1, wherein each of the plurality of microcells further comprises a quenching transistor coupled in series between the single-photon avalanche diode and the current mirror.

6. The SiPM of claim 1, wherein each of the plurality of microcells further comprises a disable transistor coupled to the cathode of the single-photon avalanche diode and configured to disable the single-photon avalanche diode.

7. The SiPM of claim 1, wherein each of the plurality of microcells further comprises an enable transistor, the enable transistor being coupled in series with the single-photon avalanche diode and configured to enable a current path between the single-photon avalanche diode and the current mirror.

8. A silicon photomultiplier tube (SiPM), comprising: A plurality of micro-units, each having a micro-unit output coupled to a summing node of the SiPM, each of the plurality of micro-units comprising: Single-photon avalanche diode; and A passive quenching device, wherein the passive quenching device is coupled in series with the single-photon avalanche diode; and A current mirror is coupled to the summing node and configured to generate a SiPM output current based on the sum of the microcell output currents received at the summing node.

9. The SiPM of claim 8, further comprising a resistor coupled to the current mirror and configured to generate an output voltage based on the output current of the SiPM.

10. The SiPM of claim 8, wherein the current mirror is configured to amplify the sum of the microcell output currents received at the summing node to generate the SiPM output current.

11. The SiPM of claim 8, wherein each of the plurality of microcells further comprises a precharge transistor configured to precharge the single-photon avalanche diode with a bias voltage higher than the reverse breakdown voltage of the single-photon avalanche diode.

12. The SiPM of claim 8, wherein each of the plurality of microcells further comprises a quenching transistor coupled in series between the single-photon avalanche diode and the output of the microcell.

13. The SiPM of claim 8, wherein each of the plurality of microcells further comprises a disable transistor coupled to the cathode of the single-photon avalanche diode and configured to disable the single-photon avalanche diode.

14. The SiPM of claim 8, wherein each of the plurality of microcells further comprises an enable transistor coupled in series with the single-photon avalanche diode and configured to enable a current path between the single-photon avalanche diode and the microcell output.

15. An imaging system, the imaging system comprising: Image processing circuit; and Semiconductor devices, communicatively coupled to the image processing circuit and comprising a plurality of silicon photomultiplier tubes (SiPMs), each SiPM comprising: A plurality of micro-units, each having a micro-unit output coupled to a summing node of the SiPM, each of the plurality of micro-units comprising: Single-photon avalanche diode; and A passive quenching device, wherein the passive quenching device is coupled in series with the single-photon avalanche diode; and A current mirror is coupled to the summing node and configured to generate a SiPM output current based on the sum of the microcell output currents received at the summing node.

16. The imaging system according to claim 15, wherein: The current mirror includes an input transistor and an output transistor; and The first aspect ratio of the channel region of the output transistor is greater than the second aspect ratio of the channel region of the input transistor.

17. The imaging system of claim 15, wherein each of the plurality of microcells further comprises a precharge transistor coupled to the cathode of the single-photon avalanche diode and configured to precharge the single-photon avalanche diode with a bias voltage higher than the reverse breakdown voltage of the single-photon avalanche diode.

18. The imaging system of claim 15, wherein each of the plurality of microcells further comprises a quenching transistor, the quenching transistor being coupled in series between the single-photon avalanche diode and the microcell output and configured to provide active quenching of the single-photon avalanche diode.

19. The imaging system of claim 15, wherein each of the plurality of microcells further comprises a disable transistor coupled to the cathode of the single-photon avalanche diode and configured to reduce the bias voltage applied to the single-photon avalanche diode.

20. The imaging system of claim 15, wherein each of the plurality of microcells further comprises an enable transistor, the enable transistor being coupled in series with the single-photon avalanche diode and configured to enable a current path between the single-photon avalanche diode and the microcell output.

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