Gpu-based quantum-resistant cryptographic algorithm hardware description language acceleration core design method

Abstract

The application relates to the cross field of information security and computer-aided design, and particularly discloses a GPU-based anti-quantum cryptographic algorithm hardware description language acceleration core design method.The method comprises the following steps: constructing a semantic analysis model based on a Transformer to extract key computation logic of an algorithm; establishing a hardware template rule library containing basic, composite and control units; matching algorithm features and templates and planning an interconnection topology through a graph neural network; automatically generating Verilog / VHDL code with pipeline optimization; and simulating and verifying on a GPU acceleration platform and optimizing in a closed loop.The application realizes end-to-end automatic generation from algorithm text to safe and efficient hardware cores, shortens the design cycle, improves performance and anti-side channel attack capability, and supports cross-process node migration.

Description

Technical Field

[0001] This invention belongs to the interdisciplinary field of information security and computer-aided design, specifically involving a GPU-based method for accelerating the design of quantum-resistant cryptographic algorithms using a hardware description language. Background Technology

[0002] With the rapid advancement of quantum computing technology, traditional public-key cryptography faces security threats, and post-quantum cryptography, as a core means of resisting quantum attacks, has become a research hotspot in the global information security field. Quantum-resistant cryptographic algorithms provide security guarantees through complex mathematical structures and play an irreplaceable role in critical scenarios such as financial communications, network infrastructure, and personal privacy protection. The standardization and deployment of such algorithms are not only crucial to the long-term security of data transmission but also affect the cornerstone of future global information system security defenses.

[0003] Designing dedicated hardware-based acceleration cores is a key approach to achieving efficient operation of quantum-resistant cryptographic algorithms. Constructing optimized logic circuit architectures using hardware description languages ​​can fully leverage the parallelism inherent in the algorithms, meeting the demands for high throughput and low latency in real-time processing. Designing highly flexible and rapidly iterative hardware acceleration solutions for evolving cryptographic standards has become a crucial issue in the fields of cryptographic chip design and integrated circuit design automation.

[0004] Current technologies primarily rely on manual coding or high-level synthesis tools for algorithm translation. However, given the frequent updates and iterations of quantum-resistant cryptographic algorithm standards, traditional development models struggle to shorten the design cycle from algorithm definition to hardware implementation. Traditional design flows are inefficient when handling complex parallel operators, resulting in a semantic mapping gap between the algorithm's mathematical characteristics and the underlying hardware architecture, hindering precise resource scheduling and pipeline optimization. The lack of a mechanism that can automatically parse the semantics of the algorithm text and intelligently match hardware modules leads to resource waste and a surge in R&D costs during hardware refactoring.

[0005] There is an urgent need for a GPU-based hardware description language for quantum-resistant cryptographic algorithms to accelerate core design methods. Summary of the Invention

[0006] The purpose of this invention is to provide a GPU-based method for accelerating the design of quantum-resistant cryptographic algorithms using a hardware description language, which can solve the problems mentioned in the background.

[0007] To achieve the above objectives, the technical solution adopted by this invention is as follows: a GPU-based method for accelerating the design of quantum-resistant cryptographic algorithm hardware description language cores, comprising the following specific steps: Step 1: Construct a semantic parsing model for quantum-resistant cryptographic algorithms. Use the Transformer architecture in deep learning to train a neural network with natural language understanding capabilities, so that it can receive mathematical definition text or reference C code of quantum-resistant cryptographic algorithms as input, and extract key computational logic and data flow features through a multi-head attention mechanism. Step 2: Establish a hardware description language generation rule base. This hardware description language generation rule base stores a variety of verified hardware module templates. Each template corresponds to a typical cryptographic operator, including but not limited to number theory transformation, polynomial multiplication, and vector inner product operation. Each template is labeled with its resource consumption characteristics, timing constraints, and configurable parameter interfaces. Step 3: Perform semantic-to-structural mapping operation, match the algorithm features extracted in Step 1 with the hardware module templates in Step 2, select the optimal combination scheme from the rule base based on operator type, data bit width, parallelism requirements and physical constraints under the target process node, and determine the connection topology between modules. Step 4: Generate pipeline-optimized hardware description language code. After completing module selection and interconnection planning, automatically insert necessary register-level pipeline stages to balance the contradiction between critical path latency and throughput, and adjust the pipeline depth of each stage according to the target frequency requirements, outputting complete RTL code in Verilog or VHDL format that conforms to the syntax specification. Step 5: Deploy to the GPU acceleration platform for simulation verification. Load the generated hardware description language code into the GPU environment that supports hardware simulation acceleration, run typical test vector sets to verify the correctness of the function, and count the resource utilization, maximum operating frequency and power consumption estimates. If the preset threshold is not met, return to step 3 to re-optimize the module configuration.

[0008] Preferably, the Transformer architecture used in step 1 includes no less than 12 layers of encoder stack, each layer integrating residual connections and layer normalization units, and is pre-trained using a large-scale quantum-resistant cryptographic algorithm corpus during training, and fine-tuned for specific algorithm families such as lattice-based cryptography systems, thereby improving the accuracy of understanding technical terms such as NTT and polynomial ring operations.

[0009] Preferably, the hardware module template in step 2 is divided into three categories according to functional granularity: basic operation unit, composite processing unit, and control and scheduling unit. The basic operation unit covers basic logic components such as adders, multipliers, and modulo reducers. The composite processing unit encapsulates a complete NTT engine or polynomial multiplication array. The control and scheduling unit is responsible for coordinating data transfer, state switching, and exception handling processes.

[0010] Preferably, the matching process in step 3 introduces a similarity evaluation mechanism based on graph neural networks, which represents the algorithm features as a directed acyclic graph structure, abstracts the hardware module template as a subgraph pattern with attribute labels, finds the best embedding method through a subgraph isomorphism detection algorithm, and combines a heuristic search strategy to quickly converge to an approximate optimal solution in the feasible solution space.

[0011] Preferably, the number of pipeline stages inserted in step 4 is calculated in real time by a dynamic analysis tool. This tool traverses all signal propagation paths and identifies the longest combinational logic chain. Based on the target clock cycle length, it determines the number of register layers to be inserted, ensuring that the logic delay of each stage does not exceed a preset threshold and that the original data dependencies remain unchanged.

[0012] Preferably, the GPU acceleration platform used in step 5 is equipped with a dedicated hardware simulation kernel, which can concurrently execute multiple test stimulus sequences in a single run and read internal signal waveforms through a memory mapping interface, thereby shortening the regression test time. It also supports online modification of some configuration parameters to achieve closed-loop feedback optimization.

[0013] Preferably, the method further includes building a version management and difference comparison mechanism, which automatically records the current algorithm input version number, model weight snapshot and generated configuration parameters after each generation of new hardware description language code, and performs a structural comparison with historical versions, marking the added, deleted or modified module nodes and their impact range, so as to facilitate tracking the design change trajectory.

[0014] Preferably, the method further integrates a security enhancement module, embedding side-channel attack protection logic into the generated RTL code, including but not limited to randomly inserting invalid operation instructions, dynamically adjusting power gating strategies, and obfuscating critical path timing characteristics, thereby improving the final chip product's resistance to physical attacks in actual deployment environments.

[0015] Preferably, the method also supports cross-process node migration capability. By decoupling the hardware module template from its physical implementation details through parametric modeling technology, the same set of semantic parsing results can automatically generate adapted RTL code under different process technologies, and a smooth transition from advanced nanotechnology to mature microtechnology can be completed without manual intervention.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. The invention integrates natural language processing and architecture description technologies to construct a semantic-driven heterogeneous accelerated kernel automatic generation framework, breaking down the disciplinary barriers between computer linguistics and integrated circuit design.

[0017] 2. This method abandons the traditional design paradigm that relies on manual coding or high-level synthesis tools. Instead, it uses GPUs to run specially trained large-scale neural network models to "read" the original definition text or reference implementation code of quantum-resistant cryptographic algorithms, accurately identify the computationally intensive core operators, and intelligently match pre-built hardware IP module libraries, realizing end-to-end automated mapping from algorithm semantics to hardware structure.

[0018] 3. It shortens the hardware redesign cycle caused by frequent updates to quantum-resistant cryptography standards and bridges the semantic gap between algorithm definition and hardware implementation.

[0019] 4. The present invention incorporates a pipeline optimization mechanism and security enhancement logic during the production process, which not only ensures the achievement of high performance indicators, but also improves the physical security of the final product.

[0020] 5. This method improves the efficiency and flexibility of developing quantum-resistant cryptographic hardware acceleration cores, providing solid technical support for the rapid deployment of future quantum-safe infrastructure. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention; Figure 2 This is a schematic diagram of the core principle framework of the quantum-resistant cryptographic algorithm semantic parsing and feature extraction based on the Transformer architecture in this invention; Figure 3 This is a flowchart illustrating the semantic-to-structure mapping logic framework based on graph neural networks according to the present invention. Figure 4 This is a flowchart illustrating the logical flow framework of automated pipeline insertion and hardware description language code generation according to the present invention. Figure 5 This is a schematic diagram of the multi-level interaction relationship and data flow in which the generated code is deployed to the GPU acceleration platform for simulation verification and closed-loop optimization in this invention. Detailed Implementation

[0022] Example 1: Please refer to the appendix Figure 1 To be continued Figure 5 To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0023] In the GPU-based hardware description language acceleration kernel design method for quantum-resistant cryptographic algorithms, step 1 involves constructing a semantic parsing model for quantum-resistant cryptographic algorithms. This model utilizes the Transformer architecture in deep learning to train a neural network with natural language understanding capabilities, enabling it to receive mathematical definition text or reference C code for quantum-resistant cryptographic algorithms as input, and extract key computational logic and data flow features through a multi-head attention mechanism. In step 1, the Transformer architecture is configured to contain a stack of 12 encoder layers. Each encoder layer integrates residual connection units and layer normalization units. This structure ensures that feature signals can be propagated backwards when processing extremely deep network layers, avoiding the vanishing gradient phenomenon.

[0024] During the model training phase, a large-scale corpus of quantum-resistant cryptographic algorithms is constructed. This corpus includes algorithm documentation, pseudocode descriptions, and highly optimized reference implementations from various technical schools, such as lattice-based cryptography, code-based cryptography, multivariate cryptography, and spectral cryptography. During pre-training, the model learns the fundamental semantics of quantum-resistant cryptography through large-scale text data. Targeted fine-tuning is performed for specific algorithm families, such as lattice-based cryptography. This fine-tuning focuses on improving the model's understanding of terminology and its associated computational logic, including number theory transformations, polynomial ring operations, modulo reduction, and Gaussian sampling.

[0025] The specific semantic extraction process is as follows: After receiving the input text from the quantum-resistant cryptographic algorithm, the model transforms it into a sequence composed of word embedding vectors. These word embedding vectors not only contain semantic information but also carry the order information of the operators in the algorithm description through a positional encoding mechanism. Upon entering the multi-head attention layer, the model computes the degree of association between words in the sequence in parallel across multiple different representation subspaces. For example, when a polynomial multiplication operator is identified, the attention mechanism automatically locks onto its associated loop variable, operand array, and parameter values ​​for coefficient modulo operation. Through layer-by-layer abstraction by the 12-layer encoder, a high-dimensional feature vector matrix is ​​output at the highest layer. This matrix comprehensively characterizes the computationally intensive operator distribution, the data dependencies of the operands, and the overall data flow topology.

[0026] In the above method, step 2 involves establishing a hardware description language (HDL) generation rule base. This HDL generation rule base serves as a structured knowledge storage system, storing various verified hardware module templates. Each template corresponds to a typical cryptographic operator, including but not limited to number theory transformations, polynomial multiplication, and vector inner product operations. These hardware module templates are divided into three categories according to functional granularity: basic operation units, composite processing units, and control and scheduling units. Basic operation units encompass basic logic components such as adders, multipliers, modulo reducers, shifters, and multiplexers; composite processing units encapsulate more advanced functional entities, such as complete number theory transformation engines, parallel polynomial multiplication arrays, and hash operation accelerators; and control and scheduling units are specifically responsible for coordinating data transfer instructions, finite state machine state switching logic, and exception handling procedures in case of overflow or illegal operations.

[0027] For each hardware module template in the rule base, its multi-dimensional technical characteristics are detailed. Resource consumption characteristics indicate the number of lookup tables, registers, and embedded multiplier blocks the module is expected to occupy under the target chip architecture. Timing constraints specify the minimum hold time and maximum propagation delay between the module's input and output. Configurable parameter interfaces define the module's versatility, allowing users to dynamically adjust the data bit width, the number of parallel computing paths, and the pipeline depth during subsequent mapping. The rule base's storage format employs parametric modeling technology, enabling constant values ​​in the hardware description language code to be dynamically replaced based on input parameters.

[0028] In the above method, step 3 performs a semantic-to-structural mapping operation. The algorithmic features extracted in step 1 are matched with the hardware module templates in step 2. During the matching process, the system introduces a similarity evaluation mechanism based on graph neural networks. The algorithmic logic features extracted in step 1 are represented as a directed acyclic graph structure, where nodes represent specific computational operators and edges represent data flow directions. The module templates in the hardware description language generation rule base are abstracted into subgraph patterns with attribute labels.

[0029] The matching process uses a subgraph isomorphism detection algorithm to find the segment in the directed acyclic graph that is most similar to the hardware template subgraph. The evaluation mechanism considers not only the matching degree of operator types, but also constraints such as operator type, data bit width, parallelism requirements, and physical limitations under the target process node. The optimal embedding method is determined by calculating the vector space similarity between the algorithm node features and the hardware template features. To handle the complex combinatorial search space, this step incorporates a heuristic search strategy to quickly converge to a near-optimal solution that balances performance and area within the vast candidate hardware architecture solution space. Once the module selection is determined, the system immediately determines the connection topology between the modules and generates a logical-level hardware interconnection netlist. This netlist records in detail the flow paths of signal lines between different operational units and the cache allocation scheme.

[0030] In the above method, step 4 involves generating pipelined hardware description language code. After completing module selection and interconnect planning, to balance the trade-off between critical path latency and throughput, the system automatically inserts necessary register-level pipeline stages into the generated paths. The number of pipeline stages is calculated in real time by a dynamic analysis tool. This tool traverses all signal propagation paths in the netlist and identifies the combinational logic chain with the longest latency from the input register to the output register.

[0031] The tool calculates the length of the current clock cycle based on a pre-set target clock frequency. If the delay time of the longest identified logic path exceeds a preset proportion of the clock cycle, a flip-flop is automatically inserted between the midpoint or logic node of that path. During register insertion, the system preserves the logical dependencies between the original data, ensuring consistent timestamps at the convergence point by synchronously inserting bubble cycles or delay alignment modules on parallel paths. The generated RTL code is ultimately formatted into Verilog or VHDL code that conforms to syntax specifications, containing complete module declarations, port definitions, parameter passing logic, and specific circuit connection logic.

[0032] To enhance the security of the final hardware acceleration core, this step also integrates a security enhancement module into the generated code. This module embeds side-channel attack protection logic around critical computational logic. Specific measures include randomly inserting invalid instruction sequences to obfuscate power consumption waveforms, dynamically adjusting the power gating strategies of each module to eliminate the regularity of electromagnetic radiation, and obfuscating the execution characteristics of critical paths by adding redundant timing jitter. This security logic is generated synchronously with the core computational logic and seamlessly integrated into the RTL layer.

[0033] In the above method, step 5 deploys the generated hardware description language code to a GPU-accelerated platform for simulation verification. This GPU-accelerated platform is not a traditional general-purpose computing platform, but rather equipped with a dedicated hardware simulation kernel capable of executing tens of thousands of test stimulus sequences in parallel in a single run. The system loads the generated Verilog or VHDL code into the simulation environment and interacts with the GPU's memory through a memory-mapped interface. The simulation environment runs a typical set of test vectors containing input data for quantum-resistant cryptographic algorithms under various boundary conditions.

[0034] During simulation, the monitoring program reads the signal waveforms inside the hardware acceleration core in real time and compares them bit by bit with the calculation results of the algorithm's software reference model to verify the complete correctness of the function. The simulation tool automatically calculates the logic resource utilization, maximum operating frequency, and estimated dynamic and static power consumption of the acceleration core under operating conditions. If any performance indicator fails to meet the preset performance threshold, or if there is a logical deviation in the simulation results, the system will trigger an automatic feedback mechanism. This mechanism will return the current performance problem information to step 3 for reconfiguration by adjusting the mapping strategy, replacing the template with one of higher parallelism, or increasing the number of pipeline stages.

[0035] This method further incorporates a version management and difference comparison mechanism. After each generation of new hardware description language code, the system automatically records the version number of the current algorithm input, the model's weight snapshot at that moment, and the specific generation configuration parameters. The system performs a structural-level difference comparison, accurately identifying newly added module nodes, deleted paths, and modified configuration parameters compared to previous versions. This mechanism can track the evolution of the design, providing data support for subsequent rapid iterations.

[0036] This method also supports cross-process node migration capabilities. By employing parametric modeling techniques in the rule base, hardware module templates are logically decoupled from their specific physical implementation details. When the target process switches from advanced nanometer technology to mature micrometer technology, the system only needs to update the underlying resource library's physical feature parameters, and the semantic parsing results can automatically generate hardware code adapted to the new process, achieving a smooth transition across processes.

[0037] Example 2: In another preferred embodiment, the present invention provides a detailed description of the implementation process of automatic generation of hardware cores for the Kyber quantum-resistant encryption algorithm.

[0038] In the specific application of step 1, the input text is the official specification document of the Kyber algorithm and its referenced C language source code. The semantic parsing model identifies that the core of the Kyber algorithm lies in the learning error problem on the rings. The multi-head attention mechanism locates a core mathematical transformation during the parsing process, namely the number-theoretic transformation, which is marked as the task with the highest computational intensity. The feature extraction unit transforms the mathematical expression of this transformation into a nested computation graph containing three layers of loops. The outer loop controls the hierarchy of the transformation, the middle loop controls the data block division within each layer, and the inner loop performs basic butterfly operations. The model accurately extracts the data flow of modular multiplication, modular addition, and modular subtraction operations in the butterfly operation and records the modulus as 3329.

[0039] In step 2, the rule base provides a specially optimized number-theory transformation composite processing unit for the extracted features. This unit not only includes a parallel butterfly operation matrix but also incorporates a highly optimized Barrett reducer to quickly complete the modulo operation without division. The template is labeled as having a logic unit consumption of 4500 gates and a latency of 1.2 nanoseconds when the parallelism is set to 8 using a 28nm process.

[0040] In the mapping process of step 3, the graph neural network analyzed the data parallelism of the Kyber algorithm when handling polynomial matrix multiplication. Due to different security levels of Kyber, the matrix dimensions vary between 2×2 and 4×4. The mapping logic automatically selects an appropriate parallelism scheme from the rule base based on the input security parameters. For the version with the highest security level, the mapping algorithm decides to use a 16-way parallel number theory transformation engine and configures a corresponding multi-port memory interface to meet the high-concurrency data read / write requirements. The subgraph isomorphism algorithm successfully identified the random number generation requirement in the algorithm and automatically matched a deterministic random number generator module based on hash functions.

[0041] In the code generation phase of step 4, the dynamic analysis tool detected a long combinational logic path in the modular multiplier of the number-theory transformation engine. To ensure stable operation at 500 MHz, the tool automatically inserted two stages of pipelined registers after the multiplication array of the modular multiplier and before the accumulator. The generated Verilog code not only includes the definitions of these registers but also generates a complex handshake protocol through a logic generator to manage data validity and backpressure signals between the multi-stage pipelines. To enhance security, the generated code applies address scrambling logic to the address bus of the static random access memory storing polynomial coefficients, making it difficult for attackers to obtain the intermediate state of internal computation through external probes.

[0042] In the verification phase of step 5, the GPU acceleration platform generated millions of random plaintext vectors in parallel using its thousands of cores. These vectors were transmitted via the PCIe interface to a hardware acceleration core model deployed in the GPU memory. The simulation system completed the full simulation of the Kyber encryption, decryption, and key encapsulation process in a very short time. Statistical results showed that the generated acceleration core achieved 50,000 key encapsulation operations per second at the target frequency. The resource statistics module reported that the lookup table occupancy rate reached 65%, meeting the preset threshold requirements. The system then automatically saved this design version and recorded all parameter configurations, completing the full automatic generation cycle.

[0043] In the implementation of the Kyber algorithm described above, the semantic parsing model specifically identifies the low-order bit discarding operation in lattice-based ciphers. This operation mathematically corresponds to a specific interval truncation operation. The model maps it to a combination of bit offsetters and adders in the hardware rule base. To optimize this path, step 4 utilizes carry chain resources in the target FPGA or ASIC during code generation, specifying low-level primitive calls through structured description statements, enabling this seemingly simple operation to achieve optimal performance in actual circuits.

[0044] For the SHA-3 hash operator frequently used in Kyber, the rule base provides a sponge-like construction model with configurable throughput. The mapping algorithm dynamically determines the internal state bit width and iteration rounds of the hash unit based on static statistics of hash call frequency within the algorithm. When generating the pipeline, the system automatically creates an asynchronous first-in-first-out queue between the two modules, taking into account the asynchronous nature of hash operations and polynomial operations. The depth of this queue is determined by simulating the worst-case data burst size, ensuring that data flow is not lost when crossing modules with different clock domains or inconsistent processing speeds.

[0045] Example 3: In the example of automatic generation involving the Dilithium digital signature algorithm, the present invention demonstrates a technical approach for handling algorithms with more complex control flow and larger memory requirements.

[0046] In step 1, the model identifies numerous rejection sampling logic operations based on rounding in the Dilithium algorithm. This involves dynamically deciding whether to re-execute the step based on the computation result within a loop structure. A multi-head attention mechanism recognizes the high uncertainty of this control logic and introduces the concept of branch prediction weights in feature extraction, describing this nondeterministic data flow as a directed graph with feedback loops. The model focuses on extracting frequent access patterns to the private key matrix and noise vector during signature generation.

[0047] In step 2, to address Dilithium's large-scale coefficient storage requirements, the rule base is configured to include multiple hierarchical memory management templates. These include internal cache units supporting ping-pong operations and an external storage controller interface with prefetch logic. For control flow, the rule base provides a programmable finite state machine template that supports dynamic configuration of branch jumps and loop counts, enabling flexible handling of rejection sampling logic in the algorithm.

[0048] In the mapping phase of step 3, the similarity evaluation mechanism found that traditional parallel processing architectures were inefficient in handling rejection sampling. The mapping algorithm adopted a more flexible task distribution architecture, splitting Dilithium's signature task into multiple independent pipeline segments. These segments are managed by a global scheduling unit. The scheduling unit dynamically allocates new rounds of sampling tasks to available computing units based on the current idle state of the processors. The graph neural network, through deep analysis of algorithm dependencies, determined the optimal layout of the coefficient matrix in memory to reduce the probability of collisions during polynomial operations.

[0049] In step 4, when generating RTL code, a multi-layered nested control plane is generated to handle the complex control logic of Dilithium. The lower-level control logic is responsible for operator-level timing triggering, while the higher-level control logic handles branch judgments at the algorithm logic level. Since the Dilithium algorithm has low requirements for clock cycle consistency but extremely high requirements for single-signature response time, the dynamic analysis tool employs a non-uniform pipeline strategy here. Deeper pipelines are used in the critical hash and polynomial multiplication parts, while lower latency is maintained in the logic judgment parts to shorten the time consumed by feedback loops. To prevent side-channel attacks, a time constant technique is introduced when performing sampling operations in the generated code. By padding invalid clock cycles, the execution time remains consistent regardless of whether sampling is successful.

[0050] In the simulation verification in step 5, the GPU platform ran stimuli with extremely high coverage for Dilithium's signature and verification processes. Specifically, for edge cases of rejected sampling, the system automatically constructed special inputs capable of triggering multiple resampling operations. During the verification process, the monitoring unit detected a deadlock risk in a particular module when handling consecutive sampling failures. This feedback was immediately sent back to step 3, and the mapping engine adjusted the state machine's timeout reset logic accordingly. After two rounds of iteration, the generated code achieved an optimal balance between resource utilization and throughput.

[0051] To enhance security, this embodiment incorporates redundant verification logic during code generation in step 4, addressing potential fault injection attacks in the Dilithium algorithm. The system automatically adds parity bits to critical data paths and applies triple redundancy to important state machine registers. If an anomaly caused by external interference is detected during operation, the hardware acceleration core immediately initiates a secure self-destruct procedure, clearing internally stored private key information and issuing an alarm signal. This automatically embedded security logic during the generation phase enhances the survivability of quantum cryptography algorithms in malicious environments.

[0052] This embodiment demonstrates how to smoothly migrate a design optimized for a 7nm process to a 55nm embedded flash memory process when handling the cross-process migration of Dilithium. In the 7nm process, the system uses a large-scale SRAM array to store intermediate variables in pursuit of maximum computational speed. However, when migrating to the 55nm process, the area constraint parameters in the rule base change. The mapping engine in step 3 automatically recognizes that the area overhead of the large-capacity SRAM is unacceptable, and therefore automatically switches to a strategy of trading logic resources for storage space. The system generates an on-chip storage scheme based on a compression algorithm, performing real-time compression before data is stored in the cache and real-time decompression upon retrieval. This process-aware automatic mapping adjustment enables the same set of Dilithium semantic parsing results to achieve optimal deployment results on drastically different physical platforms.

[0053] Example 4: In another example of a hybrid deployment of multiple quantum-resistant algorithms, the method of the present invention demonstrates its ability to build heterogeneous multi-core accelerated systems.

[0054] In step 1, the model receives definitions for multiple algorithms, including Kyber, Dilithium, and SPHINCS+. Through a multi-head attention mechanism, the semantic parsing model not only extracts features from individual algorithms but also identifies underlying operators shared among them. For example, the model discovers that multiple algorithms use similar SHAKE extended output functions. This cross-algorithm semantic recognition lays the foundation for subsequent hardware resource reuse.

[0055] In the rule base management step 2, the system creates multi-functional reconfiguration module templates for these shared operators. These templates have the ability to be dynamically reconfigured, and can switch the functions they perform in different clock cycles, such as switching from performing ordinary hash operations to performing tree-structured hash chain operations.

[0056] In step 3, the mapping operation performs a multi-tasking-oriented global resource scheduling. Instead of simply generating independent kernels for each algorithm, it constructs a shared resource pool. The graph neural network determines the number of various modules in the resource pool by analyzing the concurrency probability of different algorithms in real-world application scenarios. For example, if the system predicts frequent concurrent execution of key encapsulation and signature verification, it increases the number of shared number-theory transformation engines. The mapping logic generates a complex interconnect network, connecting these shared engines to the dedicated controllers of each algorithm via crossbar switches or on-chip networks.

[0057] In step 4, the generated code includes a global configuration register set, allowing the host software to dynamically allocate hardware resources at runtime. Pipeline optimization tools face more complex challenges here, as they must ensure that signal path delays meet timing requirements across different configuration modes. The system extensively utilizes asynchronous handshake protocols and adjustable delay units in the interconnect network.

[0058] In step 5, the GPU simulation platform simulated a complex scenario of concurrent execution of multiple algorithms. It not only verified the correctness of each algorithm's function but also focused on monitoring the performance of shared resources under contention conditions. By statistically analyzing the interference delays between different tasks, the feedback mechanism fine-tuned the arbitration priority algorithm of the interconnection network, ensuring the real-time performance of high-priority tasks. This leap from a single algorithm to multi-algorithm collaboration fully demonstrates the flexibility and efficiency of this invention in handling complex system designs.

[0059] To address the massive hash operations in the SPHINCS+ algorithm, this embodiment specifically generates a multi-threaded hash acceleration architecture based on a task queue in step 4. Each hash engine is equipped with a small instruction queue, enabling it to execute complete hash chain calculations independently of the main controller. The generation engine automatically adjusts the distribution logic of the hash engines on the chip layout based on the routing congestion level of the target chip, guiding subsequent synthesis tools to perform reasonable placement and routing by adding physical constraint suggestions to the code.

[0060] In terms of security, memory isolation becomes crucial in hybrid deployment environments. This invention automatically allocates an independent physical address space for each algorithm core when generating the hardware interconnection table and embeds mandatory permission verification logic in the memory access control unit. Any attempt to access the private memory region of another algorithm without authorization will trigger a hardware exception and immediately sever the data path. This hardware firewall, automatically generated at the RTL level, provides underlying hardware protection for quantum-safe computing in multi-tenant or multi-tasking environments.

[0061] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A method for designing accelerated cores based on a graphics processor-based hardware description language for quantum-resistant cryptographic algorithms, characterized in that, The specific steps include the following: Construct a semantic parsing model for quantum-resistant cryptographic algorithms, and use a neural network with a multi-head attention mechanism to extract key computational logic and data flow features from the mathematical definition text or reference code of quantum-resistant cryptographic algorithms; A hardware description language generation rule base is established, which stores a variety of verified hardware module templates. Each hardware module template corresponds to a type of cryptographic operator, and each hardware module template is labeled with resource consumption characteristics, timing constraints, and configurable parameter interfaces. Perform semantic-to-structural mapping operation, match the extracted algorithm features with the hardware module templates in the hardware description language generation rule base, select a combination scheme from the hardware description language generation rule base based on operator type, data bit width, parallelism requirements and physical constraints under the target process node, and determine the connection topology between each hardware module. Generate pipeline-optimized hardware description language code. After completing the selection and interconnection planning of the hardware module template, insert a register-level pipeline stage to balance critical path latency and throughput, and output hardware description language code that conforms to the syntax specification. The system is deployed to a graphics processor platform with a hardware simulation kernel for simulation verification. Test vector sets are run to verify the correctness of the function, and resource utilization, maximum operating frequency and power consumption estimates are statistically analyzed. The mapping operation is then optimized based on the statistical results. The semantic-to-structure mapping operation specifically includes: A similarity evaluation mechanism based on graph neural networks is introduced, and the extracted algorithm features are represented as a directed acyclic graph structure, where nodes represent computation operators and edges represent data flow directions. The hardware module templates in the hardware description language generation rule base are abstracted into subgraph patterns with attribute tags; The subgraph isomorphism detection algorithm is used to find segments in the directed acyclic graph structure that match the subgraph pattern; during the matching process, operator type matching degree, data bit width, parallelism requirements, and physical constraints under the target process node are introduced as constraints. Calculate the vector space similarity between algorithm node features and hardware template features to determine the embedding method; use a heuristic search strategy to search in the candidate hardware architecture solution space and converge to a solution that balances performance and area. After determining the hardware module template selection, the connection topology between each hardware module is determined, and a hardware interconnection table at the logic level is generated. The hardware interconnection table records the flow path of signal lines between different processing units and the cache allocation scheme.

2. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 1, is characterized in that... The construction of the semantic parsing model for quantum-resistant cryptography algorithms specifically includes: The neural network is configured as a stacked encoder structure with a preset number of layers, and each encoder layer integrates a residual connection unit and a layer normalization unit. The neural network is pre-trained using a quantum-resistant cryptographic algorithm corpus, which includes algorithm documentation, pseudocode descriptions, and reference implementation code for lattice-based cryptography, code-based cryptography, multivariate cryptography, and spectral cryptography. The algorithm family is used to fine-tune the pre-trained neural network to improve the neural network's understanding of number theory transformations, polynomial ring operations, modulo reduction, and Gaussian sampling terms and their associated computational logic. The received input text of the quantum-resistant cryptography algorithm is converted into a sequence of word embedding vectors, and the order information of the operators in the algorithm description is added to the word embedding vectors using a positional encoding mechanism; The correlation between words in the sequence is computed in parallel in multiple different representation subspaces. When a target operator is identified, the associated loop variable, operand array, and parameter value of the coefficient modulo are locked through an attention mechanism. Through the layer-by-layer abstraction of the encoder stack structure, a high-dimensional feature vector matrix is ​​output at the highest layer. The high-dimensional feature vector matrix describes the distribution of computationally intensive operators, the data dependencies of operands, and the overall data flow topology of the quantum-resistant cryptographic algorithm.

3. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 2, is characterized in that... The process of establishing and configuring the hardware description language rule base specifically includes: The hardware module template is divided into basic arithmetic units, composite processing units, and control and scheduling units according to functional granularity; the basic arithmetic units include adders, multipliers, modulo reducers, shifters, and multiplexers. The composite processing unit encapsulates a number theory transformation engine, a parallel polynomial multiplication array, and a hash operation accelerator; the control and scheduling unit is responsible for coordinating data transfer instructions, the state switching logic of the finite state machine, and the exception handling process. In the hardware description language generation rule base, resource consumption characteristics are marked for each hardware module template. The resource consumption characteristics include the number of lookup tables, the number of registers, and the number of embedded multiplier blocks expected to be occupied under the target chip architecture. In the hardware description language generation rule base, timing constraints are marked for each hardware module template. The timing constraints specify the minimum hold time and maximum propagation delay of the hardware module template from input to output. In the hardware description language generation rule base, each hardware module template is marked with a configurable parameter interface, which is used to dynamically adjust the data bit width, the number of parallel computing paths, and the pipeline depth. Parametric modeling technology is used to store the hardware description language generation rule base, so that the constant values ​​in the hardware description language code are dynamically replaced according to the input parameters.

4. The method for designing a GPU-based hardware description language-accelerated core for quantum-resistant cryptographic algorithms according to claim 3, characterized in that, The generated pipeline-optimized hardware description language code specifically includes: Using dynamic analysis tools, the signal propagation paths in the hardware interconnection table are traversed to identify the combinational logic chain with the longest delay between the input register and the output register. The length of the clock cycle is calculated based on the preset target clock frequency. When the delay time of the combinational logic chain exceeds a preset proportion of the clock cycle, a flip-flop is inserted between the midpoint or logic node of the combinational logic chain. During the insertion of triggers, the logical dependencies between the original data are preserved, and bubble cycle or delayed alignment modules are inserted synchronously on the parallel path to ensure that the data has a consistent timestamp at the convergence point. The generated circuit logic is formatted into hardware description language code that conforms to the syntax specifications. The hardware description language code includes module declarations, port definitions, parameter passing logic, and specific circuit connection logic.

5. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 4, is characterized in that... The deployment to a graphics processor platform with a hardware emulation kernel for simulation verification specifically includes: A hardware simulation kernel is configured in the graphics processor platform to execute multiple test stimulus sequences concurrently in a single run; The generated hardware description language code is loaded into the simulation environment and interacts with the memory of the graphics processor through a memory mapping interface; a test vector set is run, which contains input data of the quantum-resistant cryptography algorithm under different boundary conditions; The signal waveform inside the hardware acceleration core is read in real time and compared bit by bit with the calculation result of the algorithm's software reference model; The logic resource utilization, maximum operating frequency, and estimated dynamic and static power consumption values ​​of the hardware acceleration core in its working state are statistically analyzed. When the statistically obtained performance indicators fail to reach the preset performance threshold or when the simulation results show logical deviations, an automatic feedback mechanism is triggered to return the performance bottleneck information to the mapping operation step. The optimization configuration is then performed by adjusting the mapping strategy, replacing the template with one of higher parallelism, or increasing the number of pipeline stages.

6. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 5, is characterized in that... The quantum-resistant cryptographic algorithm hardware description language accelerated core design method also includes the construction of a version management and difference comparison mechanism: After each new hardware description language code is generated, the version number of the current algorithm input, the weight snapshot of the neural network at this time, and the specific generation configuration parameters are automatically recorded. Perform structural-level comparisons to identify newly added module nodes, deleted paths, and modified configuration parameters in historical versions, tracing the evolution of the design.

7. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 6, is characterized in that... The quantum-resistant cryptographic algorithm hardware description language acceleration core design method further includes integrating a security enhancement module into the generated hardware description language code: Side-channel attack protection logic is embedded around the critical operational logic, and the power consumption waveform is obfuscated by randomly inserting invalid operation instruction sequences into the code; The power gating strategy of each hardware module template is dynamically adjusted to eliminate the regularity of electromagnetic radiation; the execution characteristics of the critical path are obfuscated by adding redundant timing jitter. Address scrambling logic is applied to the address bus of the static random access memory that stores polynomial coefficients, making it difficult for external probes to obtain the intermediate state of internal calculations. Add check bits to critical data paths and apply a 3x redundancy design to the state machine register. When an abnormal state is detected, a secure self-destruct program is initiated to clear the internally stored private key information.

8. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 7, is characterized in that... The quantum-resistant cryptographic algorithm hardware description language accelerated core design method also supports cross-process node migration capability: The hardware module template is logically decoupled from its specific physical implementation details; when the target process is switched, the physical feature parameters of the underlying resource library in the hardware description language generation rule base are updated, and hardware description language code adapted to the new process is automatically generated based on the parsing results of the semantic parsing model. Based on the changes in the area constraint parameters of the target process, the mapping strategy is automatically adjusted. When the area overhead exceeds the preset threshold, the strategy of exchanging logical resources for storage space is switched to generate an on-chip storage solution based on compression algorithm. Data is compressed in real time before being stored in the cache and decompressed in real time when it is retrieved.

9. The method for designing a GPU-based accelerated core for quantum-resistant cryptographic algorithms using a hardware description language, as described in claim 8, is characterized in that... The quantum-resistant cryptographic algorithm hardware description language accelerated core design method also includes constructing a heterogeneous multi-core accelerated system: Simultaneously receive definition texts of multiple quantum-resistant cryptographic algorithms and use a multi-head attention mechanism to identify the underlying operators shared between different algorithms; In the hardware description language generation rule base, a multi-functional reconfiguration module template is created for the shared operator. The multi-functional reconfiguration module template has the ability to switch execution functions in different clock cycles. Perform global resource scheduling for multi-task scenarios, build a shared resource pool, and determine the number of various hardware modules in the shared resource pool by analyzing the concurrency probability of different algorithms in concurrent scenarios. An interconnection network is generated to connect the shared engine to the controllers of each algorithm via cross switches or on-chip networks, and an asynchronous handshake protocol and adjustable delay units are applied in the interconnection network. The generated code includes a global configuration register set, which is dynamically allocated by the host software at runtime; Each algorithm core is allocated an independent physical address space, and permission verification logic is embedded in the memory access control unit to cut off the data path when unauthorized access occurs.

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