FPGA-based intelligent conference system flow control optimization algorithm

Abstract

This invention relates to the field of network communication technology, specifically to a flow control optimization algorithm for an FPGA-based intelligent conferencing system. It constructs a central control unit (CCU) with the FPGA as its core, and uses a cascaded CAM to segment the 48-bit MAC address into six 8-bit sub-keys for parallel searching, outputting the matching result in one clock cycle. A system cycle of 1-5ms is set, and data is transmitted in time slots according to the order of SOC frames, real-time data frames, SOA frames, non-real-time data frames, and TAIL frames, isolating real-time and non-real-time data. A dynamically maintained MAC address table based on an aging mechanism is established to achieve adaptive topology changes for slave devices. Dynamic priority polling arbitration is used to fairly allocate shared storage resources across multiple PHY interfaces. This invention achieves zero-conflict, high-bandwidth utilization network data transmission at a rate of 1000Mbit / s, significantly reducing FPGA resource consumption, improving the real-time performance and reliability of the conferencing system, and is suitable for multi-slave distributed intelligent conferencing scenarios.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and more specifically to an FPGA-based intelligent conferencing system flow control optimization algorithm. Background Technology

[0002] The development of automation technology increasingly relies on information technology and industry standards. Industrial automation is evolving towards high-speed, high-precision, and distributed control. Traditional fieldbuses suffer from bandwidth bottlenecks and poor compatibility due to limitations of dedicated protocols and hardware interfaces. Ethernet technology has become the mainstream solution to this problem and is widely used in industrial control, smart conferencing, and other scenarios.

[0003] However, traditional Ethernet is prone to data transmission delays when the network load is high, which leads to a decrease in network throughput and transmission latency stability, making it difficult to meet the requirements of determinism and real-time communication in industrial control and intelligent conferencing scenarios.

[0004] Currently, network packet processing mostly adopts a "matching + action" model structure. The matching table, as a core component, supports functions such as packet classification, routing decision, and forwarding. The matching table implementation based on application-specific integrated circuits (ASICs) suffers from long development cycles and insufficient flexibility in functional iteration. In contrast, field-programmable gate arrays (FPGAs), with their parallel processing performance and hardware programmability, have become the mainstream hardware platform in the field of network acceleration.

[0005] In intelligent conferencing scenarios where a central control unit controls a large number of slave devices, existing technical solutions suffer from the following drawbacks: First, MAC address lookup often relies on traditional RAM serial access or a single CAM. The former is slow, while the latter consumes hardware resources exponentially when processing 48-bit MAC addresses. Second, data frame transmission lacks a clear time-slot scheduling mechanism, leading to severe conflicts between real-time and non-real-time data frames and low bus bandwidth utilization. Third, the forwarding of non-real-time data frames lacks precise flow control, and the storage resource access arbitration mechanism is unreasonable, easily resulting in situations where some port requests remain unresponsive for extended periods. Fourth, MAC address tables are mostly statically maintained and cannot be dynamically updated based on the slave device's access status, resulting in a high error rate in non-real-time data frame forwarding.

[0006] Therefore, there is an urgent need for an efficient and deterministic data flow control method implemented at the hardware level. Summary of the Invention

[0007] To address the aforementioned technical issues, this invention provides an FPGA-based intelligent conference system flow control optimization algorithm, which enables efficient data processing at gigabit transmission rates, improves bus bandwidth utilization, and enhances the real-time performance and reliability of system communication.

[0008] An FPGA-based intelligent conference system flow control optimization algorithm includes the following steps:

[0009] S1. Generate the system cycle and transmit real-time data frames and non-real-time data frames in time slots.

[0010] S2. Receive non-real-time data frames, determine whether the destination MAC address is a broadcast address, and if so, cache it to the broadcast buffer space; otherwise, cache it to the shared SRAM.

[0011] S3. Extract the destination MAC address of the non-real-time data frame, segment the MAC address and input it into multiple parallel storage units for synchronous lookup, merge the matching results of each storage unit, and decode the destination port through a priority encoder.

[0012] S4. If the search is successful, forward the non-real-time data frame precisely to the matching tributary port; if the search fails, forward the non-real-time data frame to all tributary ports except the source port.

[0013] S5. Record the mapping relationship between the source MAC address and the source port, write it into the MAC address table, and maintain the aging and updating of the table entries;

[0014] S6. Perform dynamic priority round-robin arbitration on storage access requests for multiple PHY interfaces.

[0015] Preferably, step S3, which involves segmenting the MAC address and inputting it into multiple parallel storage units for synchronous lookup, specifically involves: segmenting the 48-bit MAC address into six 8-bit sub-keywords, and inputting them into six parallel small-capacity RAMs for synchronous lookup; performing a bitwise AND operation on the six matching line vectors output from each RAM to obtain the overall matching line vector; and inputting the overall matching line vector into the priority encoder to output the matching address.

[0016] Preferably, the parallel storage unit implements cascaded CAM based on the BRAM transposed storage structure: the address port of the BRAM serves as the data input port of the CAM table entry, and the data port of the BRAM serves as the output matching line; during the storage phase, the CAM table entry content is written to the BRAM as the write address, and the matching line vector is written in the corresponding storage unit; during the query phase, the query data is input to the BRAM address port, and the matching line vector is directly output.

[0017] Preferably, the time-slot transmission in step S1 specifically involves sending data frames in the following order within each system cycle: SOC frame, real-time data frame, SOA frame, non-real-time data frame, and TAIL frame. The SOC frame indicates the start of the real-time time slot, the SOA frame indicates the start of the non-real-time time slot, and the TAIL frame indicates the end of the cycle.

[0018] Preferably, the duration of the system cycle is 1ms to 5ms.

[0019] Preferably, the maintenance entry aging update in step S5 specifically includes:

[0020] Start an aging timer for newly written entries, with an aging time of 10 to 60 seconds;

[0021] If a table entry is not queried within the aging period, the entry will be automatically deleted.

[0022] If the table entry exists and the associated port is the same as the current source port, reset the aging timer;

[0023] If a table entry is found but the associated port is inconsistent with the current source port, update the table entry port information and reset the aging timer.

[0024] Preferably, the dynamic priority polling arbitration in step S6 specifically refers to:

[0025] The authorization granularity is 1 clock cycle, and only one channel storage access request is authorized per clock cycle;

[0026] A complete polling cycle consists of N clock cycles, where N is the number of PHY interfaces in the shared buffer.

[0027] Once a channel is authorized, its priority is dynamically adjusted to the lowest level within the current polling cycle.

[0028] The remaining channels are prioritized in a pre-defined order.

[0029] Preferably, N is 6, and the PHY interface includes one uplink interface and five or six downlink tributary interfaces.

[0030] Preferably, the FPGA integrates a NIOS soft core, which communicates with the MCU via a serial port to process real-time conference command interactions.

[0031] The technical effects and advantages of this invention are as follows:

[0032] Coordinated optimization of search speed and resource consumption: By segmenting the 48-bit MAC address into parallel segments through cascaded CAM, the search speed is increased to 1 clock cycle, while the storage overhead is reduced from the exponential growth of traditional CAM to a linear combination, and FPGA resource consumption is reduced by more than 60%.

[0033] Dual improvement in real-time performance and bandwidth utilization: The system adopts a 2ms-level system cycle time-slot transmission, real-time data and non-real-time data are physically isolated, the probability of bus collision is reduced to near zero, the bandwidth utilization is increased from 65% in the traditional solution to more than 92%, and the real-time audio command transmission latency is stably below 10ms.

[0034] Adaptive topology change capability: Dynamic maintenance of MAC address table based on aging mechanism, supporting hot-swapping and location migration of slave devices in daisy chain, table update latency of less than 5ms, and non-real-time data frame forwarding success rate improved to over 99.9%.

[0035] Fair access to storage resources: Dynamic priority round-robin arbitration ensures no request starvation when multiple PHY interfaces share the cache, and the write latency variance of each port is less than 3 clock cycles under extreme load.

[0036] Domestically produced and controllable: The hardware platform can be built on domestically produced FPGA chips, eliminating dependence on imported components and reducing costs by more than 40% for the same performance, making it suitable for critical infrastructure conferencing systems. Attached Figure Description

[0037] Figure 1 This is a hardware architecture diagram of the central control unit (CCU) of this invention.

[0038] Figure 2 This is a diagram showing the data frame transmission sequence of the system of the present invention in a cyclical manner.

[0039] Figure 3 This is a schematic diagram of the structure of the bus protocol frame of the present invention.

[0040] Figure 4 This is a diagram illustrating the overall architecture of the flow direction control optimization algorithm of this invention.

[0041] Figure 5 This is an interface block diagram of the transceiver module of the present invention.

[0042] Figure 6 This is the overall flow diagram of the non-real-time network data frames of this invention.

[0043] Figure 7 This is a schematic diagram of the hardware structure of the CAM of the present invention.

[0044] Figure 8 This is a schematic diagram of the implementation structure of the CAM of the present invention.

[0045] Figure 9 This is a schematic diagram of the BRAM-based CAM of the present invention.

[0046] Figure 10 This is a schematic diagram of the cascaded CAM scheme of the present invention.

[0047] Figure 11 This is a processing block diagram for non-real-time network data frame flow control according to the present invention.

[0048] Figure 12 This is a structural diagram illustrating the implementation of the polling arbitration method in this invention. Detailed Implementation

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and design various embodiments with various modifications suitable for a particular purpose.

[0050] Example 1: A flow control optimization algorithm for an FPGA-based intelligent conference system, comprising the following steps:

[0051] S1 generates a system cycle, transmitting real-time data frames and non-real-time data frames in time slots.

[0052] The central control unit (CCU) uses an FPGA as its core hardware platform to generate periodic timing signals, dividing the bus transmission time into equal-length system cycles.

[0053] Within each cycle, data frames are sent in the following order: SOC frame - cycle start frame → real-time data frame - command frame, audio frame → SOA frame - non-real-time data flag frame → non-real-time data frame - video frame, file frame → TAIL frame - cycle end frame.

[0054] The SOC frame indicates the start of a real-time time slot, the SOA frame indicates the start of a non-real-time time slot, and the TAIL frame indicates the end of a cycle.

[0055] This time-sharing isolation mechanism effectively avoids conflicts between real-time and non-real-time data on the physical link.

[0056] S2. Receive non-real-time data frames, determine whether the destination MAC address is a broadcast address, if so, cache it to the broadcast buffer space, otherwise cache it to the shared SRAM.

[0057] The CCU's multiple PHY interfaces receive non-real-time data frames from servers or slave devices.

[0058] First, check the destination MAC address: if it is a broadcast address (FF:FF:FF:FF:FF:FF:FF), then store the data frame in the dedicated broadcast buffer Buffer_FF corresponding to that port; if it is a unicast address, then store it in the independent buffer of that port.

[0059] Subsequently, all data in Buffer_FF is aggregated into the global broadcast buffer space for unified forwarding; all data in the buffer is written to the shared SRAM, which is managed with fixed partitions, allocating independent storage space for each network frame to ensure data frame integrity.

[0060] S3. Extract the destination MAC address of the non-real-time data frame, segment the MAC address and input it into multiple parallel storage units for synchronous lookup, merge the matching results of each storage unit, and decode the destination port through a priority encoder.

[0061] This step is the core of the invention to achieve low-resource, high-speed lookup; for a standard 48-bit MAC address, it is split into 6 8-bit sub-keys, which are then sent to 6 parallel small-capacity RAMs or CAMs for synchronous lookup.

[0062] Each small RAM pre-stores the table entry matching information for the corresponding address segment, and the output is a matching line vector with a depth equal to the number of table entries.

[0063] The six matching line vectors are merged using bitwise AND logic to obtain the overall matching result vector. This vector is then decoded by a priority encoder to output the index address of the matched entry. This address directly corresponds to the branch port number of the destination slave device. The entire search process can be completed within one clock cycle.

[0064] As a preferred implementation, the parallel storage unit adopts a cascaded CAM implementation based on a BRAM transposed storage structure: the address port of the BRAM is used as the data input port of the CAM table entry, and the data port of the BRAM is used as the output matching line; during the storage phase, the content of the CAM table entry is written to the BRAM as the write address, and the matching line vector is written in the corresponding storage unit; during the query phase, the query data is input to the BRAM address port, and the matching line vector is directly output.

[0065] This architecture utilizes the abundant BRAM resources within the FPGA to replace the exponential overhead of traditional CAMs with linearly increasing memory overhead.

[0066] S4. If the search is successful, forward the non-real-time data frame precisely to the matching tributary port; if the search fails, forward the non-real-time data frame to all tributary ports except the source port.

[0067] When step S3 successfully matches the tributary port corresponding to the destination MAC address, the FPGA's transceiver module will accurately forward the data frame from that port; if no entry is matched, the data frame will be copied and forwarded to all tributary ports except the source port that received the frame, in order to ensure that the unknown unicast frame can reach the destination slave.

[0068] S5. Record the mapping relationship between the source MAC address and the source port, write it into the MAC address table, and maintain the aging and updating of the table entries.

[0069] After each non-real-time data frame is forwarded, its source MAC address and the source port information that received the frame are extracted, a mapping relationship is established, and the information is written to the MAC address table. An independent aging timer is started for each table entry, with a configurable duration—preferably 10 to 60 seconds.

[0070] Further processing in progress:

[0071] If a table entry is not matched by any query within the aging period, it will be automatically deleted;

[0072] If the query hits and the port recorded in the table entry matches the source port of the current data frame, then reset the aging timer.

[0073] If the query hits but the port recorded in the table entry is inconsistent with the source port of the current data frame, the table entry is updated with the latest source port, and the aging timer is reset.

[0074] This dynamic maintenance mechanism can adapt to changes in the position of slave devices in the daisy-chain topology, avoiding erroneous forwarding.

[0075] S6. Perform dynamic priority round-robin arbitration on storage access requests for multiple PHY interfaces.

[0076] The CCU's multiple PHY interfaces share SRAM and broadcast cache space.

[0077] To avoid conflicts caused by concurrent access from multiple ports, a dynamic priority round-robin arbitration mechanism is adopted: authorization is based on a granularity of 1 clock cycle, and only one channel's storage access request is authorized per clock cycle; a complete round-robin cycle consists of N clock cycles, where N is the number of PHY interfaces in the shared cache - typically 6; when a channel is authorized, its priority is dynamically adjusted to the lowest level within the current round-robin cycle, and the priorities of the remaining channels are increased in a preset order, thereby ensuring that each channel obtains storage resources fairly in the long term and avoiding starvation.

[0078] The control device for implementing the above algorithm includes:

[0079] The central control unit (CCU) is built with an FPGA as its core hardware platform and is configured with multiple PHY interfaces to connect to slave devices. The FPGA is preferably a domestically produced chip with sufficient logic units and DSP resources, and the development environment is independent and controllable.

[0080] The transceiver module, integrated in the FPGA, is used to implement data transmission and reception between the standard Ethernet physical layer and MAC layer; each I / O port is configured with an independent receive FIFO with a depth of 2048×8bit and a transmit FIFO with a depth of 256×8bit, supporting 1000Mbit / s line-speed processing;

[0081] The flow control module, integrated into the FPGA, includes:

[0082] Time-slot transmission control unit: Executes step S1 to generate system cycle and various frame synchronization signals;

[0083] Cascaded CAM lookup unit: Executes steps S2~S3 to achieve parallel lookup of MAC address segments;

[0084] MAC address table maintenance unit: Execute step S5 to maintain table entries and aging timer;

[0085] Storage resource polling arbitration unit: Execute step S6 to implement dynamic priority polling arbitration.

[0086] When using this invention

[0087] Hardware platform setup

[0088] A specific hardware implementation scheme is applied to a distributed intelligent conferencing system.

[0089] The system consists of one central control unit (CCU) and six slave devices. Each slave device is interconnected in a daisy-chain topology, and a single slave device can connect up to 10 terminal devices. All devices are interconnected via standard Ethernet IEEE 802.3u, and a gigabit transmission rate of 1000 Mbit / s is required.

[0090] Core FPGA chip: The core FPGA chip is the PH1A100SFG676 model from Anlu Technology. This chip provides 127K equivalent LUT4 logic units and 212 DSP48E1 units. The development environment is TangDynasty IDE, equipped with a license-free basic IP library. The FPGA internally implements a NIOS II soft core processor, which communicates with an external MCU via a serial port to handle real-time conference command interaction.

[0091] PHY layer transceiver: Employs Realtek RTL8211 physical layer transceiver, supports RGMII interface, operates at a clock frequency of 125MHz, and interfaces with the FPGA's gigabit MAC layer; each I / O port is configured with an independent FIFO: the receive FIFO depth is 2048×8bit, capable of buffering a complete maximum Ethernet frame of 1526 bytes; the transmit FIFO depth is 256×8bit, meeting line-speed forwarding requirements.

[0092] CCU Interface Configuration: The CCU is configured with a total of 6 PHY interfaces; PHY1 interface serves as the uplink port, receiving non-real-time data packets from the server - video conference streams and shared files; PHY3~PHY8 interfaces serve as 6 downlink tributary ports, each port being an independent local area network segment, connecting a group of daisy-chain slave devices; the audio interface collects conference audio data, which is forwarded by the FPGA to the DSP chip for mixing processing, and the processed audio is distributed by the FPGA as real-time data frames to each slave device.

[0093] Algorithm execution flow

[0094] The complete execution flow of the algorithm of the present invention on the above-mentioned hardware platform is described in detail.

[0095] Step 1: System Cycle Initialization

[0096] The FPGA's internal timer generates a 2ms periodic signal, which is sent to six slave devices for system clock synchronization; within each 2ms period, the CCU follows... Figure 2 Downlink data frames are sent in the order shown:

[0097] SOC Frame - Period Start Frame: Frame type 0x88EE, subtype FA00, indicates the start of the real-time slot;

[0098] Real-time data frames: contain conference commands, mixed audio, etc., requiring low-latency transmission;

[0099] SOA Frame - Non-real-time Data Flag Frame: Frame type 0x88EE, subtype FA03, identifies the start of a non-real-time time slot;

[0100] Non-real-time data frames: contain video streams, file data, etc., and allow for a certain delay;

[0101] TAIL Frame - End of Period Frame: Frame type 0x88EE, subtype FA01, indicates the end of the period.

[0102] The CCU simultaneously receives all types of data frames from all slave devices and stores them into the corresponding buffers according to frame type.

[0103] Step 2: Non-real-time data frame reception and classification buffering

[0104] The PHY1 interface receives non-real-time data frames from the server, while PHY3 through PHY8 interfaces receive non-real-time data frames from the slave device. For each non-real-time data frame, the FPGA logic determines the destination MAC address.

[0105] If it is a broadcast address (FF:FF:FF:FF:FF:FF:FF), the frame will be stored in the Buffer_FF of the corresponding port;

[0106] If it is a unicast address, the frame will be stored in the buffer of the corresponding port.

[0107] A cache summary is performed every 1ms: all data frames in Buffer_FF are merged into the global broadcast buffer space; unicast frames in each port buffer are written to the shared SRAM, which is managed with fixed partitions, and each network frame is allocated an independent storage block, with address pointers dynamically allocated by the free list.

[0108] Step 3: MAC address lookup for cascaded CAM

[0109] The 48-bit destination MAC address of the non-real-time data frame to be forwarded is read from SRAM and sent to the cascaded CAM lookup unit; for example... Figure 10 As shown, the 48-bit address is split into six 8-bit subkeys, which are input into six parallel small RAMs with a depth of 256×N, where N is the entry depth. Each small RAM pre-stores the matching information for the corresponding address segment and outputs a matching line vector. The six vectors are merged bit by bit by an AND gate to obtain the overall matching vector, which is input to the priority encoder for decoding and outputs the index address of the hit entry. This address is directly mapped to one of the branch port numbers of the destination slave device, PHY3 to PHY8.

[0110] In this example, the MAC address table supports a maximum of 1024 entries, the cascaded CAM occupies 6 BRAM blocks, and the lookup time is 1 clock cycle.

[0111] Step 4: Non-real-time data frame forwarding decision

[0112] If the search is successful, the data frame is pushed from the FPGA's transmit FIFO to the matching tributary port PHY_n; if the search fails, the data frame is copied and flooded to all other tributary ports except the source port.

[0113] For broadcast frames in the broadcast buffer, broadcast them directly to all 6 tributary ports.

[0114] Step 5: Dynamic maintenance of the MAC address table

[0115] After each non-real-time data frame is forwarded, its source MAC address and the source port that received the frame are extracted and a mapping is established. If the source address does not exist in the MAC address table, a new entry is created, the address and port are written, and a 30-second aging timer is started. If the address already exists, the port is checked to see if it is consistent. If it is consistent, the aging timer is reset. If it is inconsistent, the port is updated to the latest value and the timer is reset.

[0116] All entries are scanned every second, and entries that are not found within 30 seconds are deleted.

[0117] In this embodiment, a slave device switches from the PHY3 interface to the PHY4 interface due to wiring adjustments. After the CCU receives the first non-real-time data frame sent by the slave device, it completes the MAC address table port update within 5ms. Subsequent data frames sent to the slave device are accurately forwarded to the PHY4 interface without packet loss.

[0118] Step 6: Storage Resource Round Robin Arbitration

[0119] The six PHY interfaces share the SRAM write bandwidth.

[0120] The arbitration module maintains a 6-bit priority vector. The initial priority order is: PHY1→PHY3→PHY4→PHY5→PHY6→PHY7→PHY8, with a total of 6. The actual numbering is used here.

[0121] Each clock cycle, the arbiter authorizes the channel with the highest current priority to perform an SRAM write operation. After authorization, the priority of that channel drops to the lowest within the current polling cycle, and the priorities of the remaining channels are increased in a cyclical order.

[0122] A complete polling cycle consists of 6 clock cycles. In this example, under full load concurrent writing on all 6 ports, the interval between grants to each port is uniform, the maximum number of waiting clock cycles does not exceed 12, and there are no request timeouts.

[0123] Performance test results

[0124] This example solution was deployed in a real smart conference room environment and run continuously for 30 days. The test results are as follows:

[0125] index Traditional solution Invention Solution Increase Real-time audio end-to-end latency 18.5ms 6.2ms 66.5% Non-real-time data frame forwarding success rate 98.2% 99.96% 1.8% MAC address lookup time 32ns (Serial RAM) 8ns 75% Bus bandwidth utilization 65% 92% 27% MAC address table update convergence time Static table / Manual 4.8ms - Maximum wait time for storage access requests >100 cycles 12 cycles 88% FPGA logic unit consumption (equivalent LUT) 86K (Traditional CAM) 49K 43%

[0126] Test results show that the algorithm of this invention is significantly superior to existing technical solutions in terms of real-time performance, reliability, and resource efficiency, and can meet the high standard requirements of intelligent conference systems for gigabit network communication.

[0127] Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art and related fields based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described and explained in the present invention, unless otherwise specified or limited, shall be implemented according to conventional means in the art.

Claims

1. A flow control optimization algorithm for an FPGA-based intelligent conference system, characterized in that, Includes the following steps: S1. Generate the system cycle and transmit real-time data frames and non-real-time data frames in time slots. S2. Receive non-real-time data frames, determine whether the destination MAC address is a broadcast address, and if so, cache it to the broadcast buffer space; otherwise, cache it to the shared SRAM. S3. Extract the destination MAC address of the non-real-time data frame, segment the MAC address and input it into multiple parallel storage units for synchronous lookup, merge the matching results of each storage unit, and decode the destination port through a priority encoder. S4. If the search is successful, forward the non-real-time data frame precisely to the matching tributary port. If the search fails, the non-real-time data frame will be forwarded to all tributary ports except the source port. S5. Record the mapping relationship between the source MAC address and the source port, write it into the MAC address table, and maintain the aging and updating of the table entries; S6. Perform dynamic priority round-robin arbitration on storage access requests for multiple PHY interfaces.

2. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 1, characterized in that, The step S3, which involves segmenting the MAC address and inputting it into multiple parallel storage units for synchronous lookup, specifically involves: segmenting the 48-bit MAC address into six 8-bit sub-keywords, and inputting them into six parallel small-capacity RAMs for synchronous lookup; performing a bitwise AND operation on the six matching line vectors output from each RAM to obtain the overall matching line vector; and inputting the overall matching line vector into the priority encoder to output the matching address.

3. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 2, characterized in that, The parallel storage unit implements cascaded CAM based on the BRAM transposed storage structure: the address port of the BRAM serves as the data input port of the CAM table entry, and the data port of the BRAM serves as the output matching line; during the storage phase, the CAM table entry content is written to the BRAM as the write address, and the matching line vector is written to the corresponding storage unit; during the query phase, the query data is input to the BRAM address port, and the matching line vector is directly output.

4. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 1, characterized in that, The time-slot transmission described in step S1 specifically involves sending data frames in the following order within each system cycle: SOC frame, real-time data frame, SOA frame, non-real-time data frame, and TAIL frame. The SOC frame indicates the start of the real-time time slot, the SOA frame indicates the start of the non-real-time time slot, and the TAIL frame indicates the end of the cycle.

5. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 4, characterized in that, The duration of the system's cycle is 1ms to 5ms.

6. The FPGA-based intelligent conference system flow control optimization algorithm of claim 1, wherein, The maintenance entry aging update mentioned in step S5 specifically refers to: Start an aging timer for newly written entries, with an aging time of 10 to 60 seconds; If a table entry is not queried within the aging period, the entry will be automatically deleted. If the table entry exists and the associated port is the same as the current source port, reset the aging timer; If a table entry is found but the associated port is inconsistent with the current source port, update the table entry port information and reset the aging timer.

7. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 1, characterized in that, The dynamic priority round-robin arbitration mentioned in step S6 specifically refers to: The authorization granularity is 1 clock cycle, and only one channel storage access request is authorized per clock cycle; A complete polling cycle consists of N clock cycles, where N is the number of PHY interfaces in the shared buffer. Once a channel is authorized, its priority is dynamically adjusted to the lowest level within the current polling cycle. The remaining channels are prioritized in a pre-defined order.

8. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 7, wherein N is 6, and the PHY interface includes one uplink interface and five or six downlink tributary interfaces.

9. The flow control optimization algorithm for an FPGA-based intelligent conference system according to claim 1, characterized in that, The FPGA integrates a NIOS soft core, which communicates with the MCU via a serial port to handle real-time conference command interactions.

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