Radio frequency front-end circuit and radio frequency transceiver front-end system

Abstract

The radio frequency front-end circuit comprises: a balun with one end of the primary side connected with the output end of the transmitting amplifier circuit, the other end of the primary side connected with the output end of the receiving amplifier circuit, and one end of the secondary side connected with the antenna interface and grounded; an inductive circuit connected between the input end of the receiving amplifier circuit and the antenna interface; a first capacitor with one end connected between the output end of the transmitting amplifier circuit and one end of the primary side of the balun; a first switch connected between the other end of the first capacitor and the ground; a second capacitor connected between the antenna interface and one end of the secondary side of the balun; a second switch connected between the other end of the second capacitor and the ground; a third capacitor with one end connected between the output end of the transmitting amplifier circuit and the other end of the primary side of the balun; a third switch connected between the other end of the third capacitor and the ground; and a fourth switch with one end connected between the input end of the receiving amplifier circuit and the inductive circuit and the other end grounded.

Description

Technical Field

[0001] This invention relates to the field of wireless communication integrated circuit technology, and in particular to a radio frequency front-end circuit and a radio frequency transceiver front-end system integrated into a system-on-a-chip (SoC). Background Technology

[0002] With the rapid iteration of wireless communication technology, wireless System-on-Chip (SoC) is rapidly developing towards high integration, miniaturization, and high performance. As a core module of wireless SoC, the RF transceiver front-end (RF transceiver front-end) undertakes core functions such as RF signal transmission and amplification, weak signal reception, signal transmission / reception switching, impedance matching, and chip electrostatic discharge (ESD) protection. In modern highly integrated wireless SoCs, the RF transceiver front-end needs to integrate power amplifiers (PAs), low-noise amplifiers (LNAs), transmit / receive switches, impedance matching networks, and ESD protection circuits within the same chip. This completely eliminates the drawbacks of traditional discrete device solutions, such as large size and poor consistency, significantly improving the integration and adaptability of wireless terminal devices. It is widely used in various scenarios such as the Internet of Things (IoT), consumer electronics, and short-range wireless transmission. However, with the continuous evolution of semiconductor processes and the constant iteration of process nodes, the physical characteristics of chip devices have changed significantly. Device breakdown voltage has continued to decrease, substrate conductivity has continuously increased, and parasitic effects and signal coupling interference problems have become increasingly prominent. This presents multiple challenges to the design of the RF front-end, severely restricting its overall performance and chip reliability. Summary of the Invention

[0003] The technical problem that the invention aims to solve

[0004] First, existing integrated RF front-ends generally adopt a single-antenna interface transmit-receive multiplexing architecture. The high-power RF signal in the transmit path and the weak induced signal in the receive path share the same antenna interface. In other words, the transmit and receive paths share the same antenna interface, which makes it very easy for the high-power transmit signal to crosstalk to the high-sensitivity receive link through the chip substrate, metal traces and parasitic parameters. This interferes with the normal pickup of weak signals at the receiver, greatly deteriorates the noise performance of the receive link, and leads to a decrease in the overall receiver sensitivity and a decrease in the communication anti-interference capability.

[0005] Secondly, to ensure the chip's operational stability in complex electromagnetic environments, the RF input port must be equipped with ESD protection devices to release static electricity and prevent surge voltage from damaging the chip. However, traditional on-chip ESD protection devices have a simple structure and introduce large parasitic capacitances. These parasitic capacitances are located in the RF signal input path and directly degrade the noise figure and input return loss of the receiving link, causing attenuation of weak received signals and impedance mismatch. This seriously affects the core performance of the RF receiving front end, resulting in on-chip inductors being limited by the number of metal layers and substrate losses, making it difficult to improve the quality factor (Q value) and restricting matching efficiency and bandwidth. Finally, to balance RF front-end performance and chip reliability, existing technologies typically require the addition of dedicated matching compensation components, independent ESD protection units, and isolation structures to compensate for crosstalk interference, parasitic parameters, and insufficient matching accuracy. However, these additional functional components significantly reduce chip layout area, leading to decreased chip integration and increased hardware costs. Furthermore, the added parasitic parameters introduced by these redundant components further exacerbate RF signal loss, creating a trade-off between performance, reliability, and integration. While some solutions have attempted to partially integrate baluns, switches, and ESD protection, no technology has yet been able to simultaneously achieve high-efficiency power delivery, low-noise input matching, and high-reliability electrostatic protection in a single architecture without sacrificing integration. Technical shortcomings persist, including incomplete performance optimization, limited integration, and trade-offs between performance and reliability. A unified RF front-end architecture that balances high integration, low noise, high efficiency, and high reliability has yet to be established.

[0006] In summary, current highly integrated wireless SoC RF front-ends generally suffer from numerous technical problems, such as severe crosstalk between transmit and receive devices, low Q-value of on-chip inductors, ESD parasitic parameters degrading RF performance, and high chip area and cost. There is an urgent need for a new integrated RF front-end structure to break through existing technical bottlenecks and simultaneously achieve synergistic optimization of performance, reliability, and integration.

[0007] Purpose of the invention

[0008] This invention was made to solve the above-mentioned problems, and its purpose is to provide an RF front-end circuit that can simultaneously achieve high-efficiency power transmission, low-noise input matching and high-reliability electrostatic protection in a single architecture, without sacrificing integration.

[0009] Technical solutions to solve technical problems

[0010] A first aspect of the present invention provides a radio frequency front-end circuit, comprising: Antenna interface, which connects to the antenna; Transmitter amplifier circuit; Receiver amplifier circuit; The balun has one end of its primary side connected to the output of the transmitting amplifier circuit, the other end of its secondary side connected to the antenna interface, and the other end grounded. An inductor circuit is connected between the input terminal of the receiving amplifier circuit and the antenna interface; A first capacitor, one end of which is connected between the output of the transmitting amplifier circuit and one end of the primary side of the balun; A first switch is connected between the other end of the first capacitor and ground. A second capacitor, one end of which is connected between the antenna interface and one end of the secondary side of the balun; A second switch is connected between the other end of the second capacitor and ground; A third capacitor, one end of which is connected between the output of the transmitting amplifier circuit and the other end of the primary side of the balun; A third switch is connected between the other end of the third capacitor and ground. A fourth switch, one end of which is connected between the input terminal of the receiving amplifier circuit and the inductor circuit, and the other end is grounded. In transmit mode, the first switch, the second switch, the third switch, and the fourth switch are all closed. In receive mode, the first switch, the second switch, the third switch, and the fourth switch are all off.

[0011] In the radio frequency front-end circuit of the second aspect of the present invention, Includes: a DC blocking capacitor, one end of which is connected to the inductor circuit and the fourth switch respectively; A first diode, one end of which is connected between the other end of the DC blocking capacitor and the input terminal of the receiving amplifier circuit, and the other end is grounded; The second diode has one end connected between the other end of the DC blocking capacitor and the input terminal of the receiving amplifier circuit, and the other end grounded.

[0012] In the radio frequency front-end circuit of the third aspect of the present invention, The first diode is composed of a P+ diffusion region and an N-type well, and the second diode is composed of an N+ diffusion region and a P-type substrate.

[0013] In the radio frequency front-end circuit of the fourth aspect of the present invention, The inductor circuit has a first coil and a second coil, the second coil surrounding the first coil, the first coil and the second coil sharing the same central axis and having the same winding direction.

[0014] In the radio frequency front-end circuit of the fifth aspect of the present invention, A shielding layer is provided directly below the inductor circuit, and this shielding layer is grounded.

[0015] In the radio frequency front-end circuit of the sixth aspect of the present invention, The shielding layer is composed of an underlying metal.

[0016] In the radio frequency front-end circuit of the seventh aspect of the present invention, The shielding layer has multiple parallel slits along the main flow direction of the inductor current in the inductor circuit.

[0017] In the radio frequency front-end circuit of the eighth aspect of the present invention, A continuous P+ type diffusion protection ring is provided around the inductor circuit, and the P+ type diffusion protection ring is connected to the analog ground.

[0018] In the radio frequency front-end circuit of the ninth aspect of the present invention, The fourth switch adopts a low on-resistance switching structure.

[0019] The tenth aspect of the present invention provides a radio frequency transceiver front-end system. This includes the aforementioned radio frequency front-end circuit.

[0020] Invention Effects

[0021] The RF front-end circuit of the present invention can simultaneously achieve high-efficiency power transmission, low-noise input matching and high-reliability electrostatic protection in a single architecture without sacrificing integration.

[0022] The RF front-end circuit of this invention achieves high isolation transmit / receive switching, high Q-value input matching, and meets industrial-grade ESD reliability requirements within a limited chip area through the deep collaborative design of passive devices, dynamic switching networks, and low parasitic ESD clamping paths. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the radio frequency front-end circuit involved in Embodiment 1 of the present invention.

[0024] Figure 2 This is a schematic diagram of the transmitting circuit involved in Embodiment 1 of the present invention.

[0025] Figure 3 This is a schematic diagram of the receiving circuit according to Embodiment 1 of the present invention.

[0026] Figure 4 This is a schematic diagram of the ESD protection structure at the input end of the receiving amplifier circuit involved in Embodiment 2 of the present invention.

[0027] Figure 5 This is a schematic diagram illustrating the working principle of the radio frequency front-end circuit under the ESD protection structure involved in Embodiment 2 of the present invention.

[0028] Figure 6 This is a schematic diagram of the structure of the inductor involved in Embodiment 3 of the present invention.

[0029] Figure 7 This is a schematic diagram of the structure of the first coil of the inductor involved in Embodiment 3 of the present invention.

[0030] Figure 8This is a schematic diagram of the structure of the second coil of the inductor involved in Embodiment 3 of the present invention.

[0031] Figure 9 This is a schematic diagram of the structure of the metal shielding layer of the inductor involved in Embodiment 3 of the present invention.

[0032] Label Explanation

[0033] 10 Antenna Interface

[0034] 20 antennas

[0035] 30 Transmitter Amplifier Circuit

[0036] 40 Receiver Amplifier Circuit

[0037] 410 Amplification Module

[0038] 50 Barron

[0039] 60 Inductor Circuit

[0040] 70 First Capacitor Regulation Circuit

[0041] 710 First Capacitor

[0042] 720 First Switch

[0043] 80 Second capacitor adjustment circuit

[0044] 810 Second Capacitor

[0045] 820 Second Switch

[0046] 90 Third capacitor adjustment circuit

[0047] 910 Third Capacitor

[0048] 920 Third Switch

[0049] 610 First coil

[0050] 620 Second Coil

[0051] 103 P+ type diffusion protection ring

[0052] 110 Fourth Switch

[0053] 120 shielding layer

[0054] 130 Second-stage discharge circuit

[0055] 131 DC blocking capacitor

[0056] 132 First Diode

[0057] 133 Second Diode

[0058] 611 First Port

[0059] 612 Second Port

[0060] 621 Third Port

[0061] 622 Fourth port. Detailed Implementation

[0062] <Structure of the radio frequency front-end circuit of the present invention>

[0063] The technical solution of the present invention will be described in detail below with reference to preferred embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Those skilled in the art can make equivalent substitutions to the circuit structure, device type, or control logic without departing from the core idea of ​​the present invention, and these substitutions should all be considered to fall within the scope of protection of the present invention.

[0064] Example 1

[0065] Reference Figures 1 to 3 The radio frequency front-end circuit of the present invention will be described.

[0066] Figure 1 This is a schematic diagram of the radio frequency front-end circuit involved in Embodiment 1 of the present invention.

[0067] Figure 2 This is a schematic diagram of the transmitting circuit involved in Embodiment 1 of the present invention.

[0068] Figure 3 This is a schematic diagram of the receiving circuit according to Embodiment 1 of the present invention.

[0069] like Figure 1 , Figure 2 , Figure 3 As shown, the radio frequency front-end circuit involved in Embodiment 1 of the present invention includes: an antenna interface 10; a transmitting circuit; and a receiving circuit.

[0070] Antenna interface 10 is connected to antenna 20. The output terminal of the transmitting circuit and the input terminal of the receiving circuit are both connected to antenna interface 10.

[0071] The transmitting circuit includes: a transmitting amplifier circuit 30; a balun 50; a first capacitor adjustment circuit 70; a second capacitor adjustment circuit 80; and a third capacitor adjustment circuit 90.

[0072] One end of the primary side of the balun 50 is connected to the output of the transmitting amplifier circuit 30, and one end of the secondary side of the balun 50 is connected to the antenna interface 10, while the other end of the secondary side is grounded.

[0073] A first capacitor regulation circuit 70 is connected between one end of the primary side of the balun 50 and the output of the transmitter amplifier circuit 30.

[0074] The first capacitor regulation circuit 70 has: A first capacitor 710, one end of which is connected between the output of the transmitting amplifier circuit 30 and one end of the primary side of the balun 50. A first switch 720 is connected between the other end of the first capacitor 710 and ground.

[0075] A second capacitor regulation circuit 80 is connected between one end of the secondary side of the balun 50 and the antenna interface 10.

[0076] The second capacitor regulation circuit 80 has: A second capacitor 810, one end of which is connected between the antenna interface 10 and one end of the secondary side of the balun 50. The second switch 820 is connected between the other end of the second capacitor 810 and ground.

[0077] A third capacitor regulation circuit 90 is connected between the other end of the primary side of the balun 50 and the output of the transmitter amplifier circuit 30.

[0078] The third capacitor regulation circuit 90 has the following features: The third capacitor 910 has one end connected between the output of the transmitting amplifier circuit 30 and the other end of the primary side of the balun 50. The third switch 920 is connected between the other end of the third capacitor 910 and ground. This forms an unbalanced-to-balanced switching structure and participates in the impedance matching network construction of the transmit path. The balun 50 constitutes the first-stage discharge circuit.

[0079] Reference Figure 3 The receiving circuit includes: an inductor circuit 60 with inductance L; a fourth switch 110; and a receiving amplifier circuit 40.

[0080] The inductor circuit 60 is connected between the input terminal of the receiving amplifier circuit 40 and the antenna interface 10, that is, one end of the inductor circuit 60 is connected to the antenna interface 10 and the other end is connected to the input terminal of the receiving amplifier circuit 40.

[0081] The receiving amplifier circuit 40 has an amplification module 410.

[0082] One end of the fourth switch 110 is connected between the input terminal of the receiving amplifier circuit 40 and the inductor circuit 60, and the other end is grounded.

[0083] In the transmission mode, the first switch 720, the second switch 820, the third switch 920, and the fourth switch 110 are all closed.

[0084] At this time, the second capacitor adjustment circuit 80 is grounded through the second switch 820, and the inductor circuit 60 is grounded through the fourth switch 110. The two respectively form parallel resonant branches to ground. As a result, the equivalent resonant resistance of the LC parallel resonant network can be increased, which can effectively isolate the receiving path when transmitting large signals, prevent strong signal crosstalk to the input terminal of the receiving amplifier circuit 40, and at the same time, it does not affect the output matching performance of the transmitting path.

[0085] By ensuring a high quality factor for the inductor L in the inductor circuit and employing a low on-resistance switching structure for the fourth switch 110, the equivalent resonant resistance of the LC parallel resonant network can be further increased. This allows for more effective isolation of the receiving path during large signal transmission, preventing strong signal crosstalk to the input of the receiving amplifier circuit 40, without affecting the output matching performance of the transmitting path.

[0086] like Figure 1 , Figure 2 As shown, in receive mode, the first switch 720, the second switch 820, the third switch 920, and the fourth switch 110 are all in the off state. In particular, the opening of the first switch 720 causes the output of the transmitting amplifier circuit 30 to present a high impedance state in the receiving frequency band, which greatly reduces the thermal noise and signal reflection path introduced from the transmitting path, and helps to maintain the low noise figure and good input matching characteristics of the receiving amplifier circuit 40.

[0087] Therefore, this invention provides an RF front-end circuit that integrates transceiver switching functionality and electrostatic discharge (ESD) protection. This RF front-end circuit constitutes an unbalanced-to-balanced converter and impedance matching network, suitable for system-on-chips (SoCs) manufactured using standard semiconductor processes, and particularly suitable for wireless transceiver systems supporting time-division duplex (TDD) communication. By controlling the on / off states of the first switch 720, the second switch 820, the third switch 920, and the fourth switch 110, time-division multiplexing of transmit (TX) and receive (RX) modes is achieved, allowing adjustment of the transmit and receive modes according to different transmit and receive requirements of the digital module.

[0088] Example 2

[0089] Figure 4 This is a schematic diagram of the ESD protection structure at the input end of the receiving amplifier circuit involved in Embodiment 2 of the present invention. Figure 5 This is a schematic diagram illustrating the working principle of the radio frequency front-end circuit under the ESD protection structure involved in Embodiment 2 of the present invention.

[0090] like Figure 4 , Figure 5 As shown, the difference between this embodiment 2 and embodiment 1 is that it also includes a second-stage discharge circuit 130, which works in conjunction with the switching circuit described above as an ESD protection structure.

[0091] Reference Figure 4 and Figure 5 The second-stage bleeder circuit 130 is located between the other end of the inductor circuit 60 and the common node of the fourth switch 110 and the input terminal of the receiving amplifier circuit 40. The second-stage bleeder circuit 130 includes a DC blocking capacitor 131 and a pair of complementary PN junction diodes.

[0092] One end of the DC blocking capacitor 131 is connected to both the inductor circuit 60 and the fourth switch 110. One end of the first diode 132 is connected between the other end of the DC blocking capacitor 131 and the input terminal of the receiving amplifier circuit 40, and the other end is grounded. One end of the second diode 133 is connected between the other end of the DC blocking capacitor 131 and the input terminal of the receiving amplifier circuit 40, and the other end is grounded.

[0093] Therefore, the DC blocking capacitor 131 is connected in series between the inductor circuit 60 and the receiving amplifier circuit 40 to block the DC path. The complementary PN junction diodes include a first diode 132 and a second diode 133. The first diode 132 can be composed of a P+ diffusion region and an N-type well. The second diode 133 can be composed of an N+ diffusion region and a P-type substrate. The first diode 132 and the second diode 133 are connected in parallel with opposite directions between the input node of the receiving amplifier circuit 40 and the common node of the DC blocking capacitor 131 and ground, for bidirectional clamping and secondary fine discharge of residual ESD overshoot voltage that has not been completely discharged by the first-stage discharge circuit.

[0094] Reference Figure 5 The first-stage discharge path utilizes a first-stage discharge circuit formed by the symmetrical port structure of the balun 50 to guide the electrostatic discharge main current (ESD main current) injected from the antenna interface 10 to the chip ground network, completing the large-current main discharge. The second-stage discharge path clamps the residual voltage through the aforementioned second-stage discharge circuit 130 composed of a diode network. The geometry of the first diode 132 and the second diode 133 has been optimized to meet industrial-grade ESD protection levels (such as HBM ±2 kV) while keeping their parasitic junction capacitance at a low level, avoiding significant degradation of the small-signal performance of the receiving circuit.

[0095] The radio frequency front-end circuit involved in Embodiment 2 of the present invention has an ESD protection circuit that works in conjunction with the switching circuit, and adopts a two-stage bleeder architecture. The first-stage bleeder path utilizes the symmetrical port structure of the balun 50 to guide the electrostatic discharge main current (ESD main current) injected from the antenna interface 10 to the chip ground network to complete the large current main bleeder.

[0096] Therefore, Embodiment 2 of the present invention provides an RF front-end circuit that integrates transceiver switching functionality and electrostatic discharge (ESD) protection. Through system-level coordination of passive components, switching networks, and ESD clamping paths, the RF front-end circuit simultaneously achieves high-isolation transceiver switching, high-Q input matching, and meets industrial-grade ESD reliability requirements within a limited chip area, effectively resolving the inherent contradiction between performance, reliability, and area in traditional solutions.

[0097] The radio frequency front-end circuit involved in Embodiment 2 of the present invention achieves a unified transmission efficiency, receiving sensitivity and electrostatic reliability in a single radio frequency front-end architecture through system-level collaboration of inductor structure, dynamic switch control strategy and graded ESD protection mechanism, without the need to introduce additional dedicated matching components or independent ESD units, which significantly improves the integration and cost-effectiveness of SoC and is suitable for high-performance and high-reliability wireless communication application scenarios.

[0098] Example 3

[0099] Figure 6 This is a schematic diagram of the structure of the inductor involved in Embodiment 3 of the present invention.

[0100] Figure 7 This is a schematic diagram of the structure of the first coil of the inductor involved in Embodiment 3 of the present invention.

[0101] Figure 8 This is a schematic diagram of the structure of the second coil of the inductor involved in Embodiment 3 of the present invention.

[0102] Figure 9 This is a schematic diagram of the structure of the metal shielding layer of the inductor involved in Embodiment 3 of the present invention.

[0103] Embodiment 3 of the present invention relates to a radio frequency front-end circuit. The difference between Embodiment 3 and Embodiments 1 and 2 is that, as... Figure 6 , Figure 7 , Figure 8 As shown, the inductor circuit 60 in Embodiment 3 adopts an inner and outer spiral structure. The inductor circuit 60 has a first coil 610, which is formed by winding a top metal layer as an inner loop coil, and a second coil 620, which is formed by winding a top metal layer as an outer loop coil. The second coil 620 surrounds the first coil 610. The first coil 610 and the second coil 620 share the same central axis and have the same winding direction.

[0104] In the RF front-end circuit, there are such Figure 1In the case of the structure of Embodiment 1 shown, the first port 611 and the second port 612 of the first coil 610, which is the inner loop coil, are respectively connected to the inside of the receiving amplifier circuit 40. The third port 621 of the second coil 620, which is the outer loop coil, is connected to the antenna interface 10, and the fourth port 622 is connected to the connection point between the fourth switch 110 and the input port of the receiving amplifier circuit 40.

[0105] In the RF front-end circuit, there are such Figure 5 In the case of the structure of Embodiment 2 shown, the first port 611 and the second port 612 of the first coil 610, which is the inner loop coil, are respectively connected to the inside of the receiving amplifier circuit 40, the third port 621 of the second coil 620, which is the outer loop coil, is connected to the antenna interface 10, and the fourth port 622 is connected to the connection point of the fourth switch 110 and the DC blocking capacitor 131.

[0106] In this embodiment, the inductor circuit 60 adopts an inner and outer spiral structure, including a first coil 610 as the inner loop coil and a second coil 620 as the outer loop coil, which are coaxially arranged and wound in the same direction. By configuring the inductor circuit 60 such that the second coil 620 surrounds the first coil 610, the overall layout area can be effectively reduced while maintaining the inductance value required by the RF front-end circuit, saving chip area. Furthermore, the inductance performance is enhanced through magnetic field coupling, thereby improving high-frequency performance within a limited chip area.

[0107] In addition, such as Figure 6 As shown, a continuous P+ type diffusion protection ring 103 is also provided around the inductor circuit 60. The P+ type diffusion protection ring 103 surrounds the entire inductor region and is connected to analog ground. Its function is to collect noise carriers propagating in the substrate and suppress interference coupling from other functional modules of the chip, such as digital logic or power circuits, thereby improving the signal integrity and anti-interference capability of the receiving front end.

[0108] like Figure 9 As shown, a shielding layer 120 is disposed directly below the inductor circuit 60. This shielding layer 120 may be made of an underlying metal. By disposing of a shielding layer directly below the inductor circuit 60, high-frequency eddy current losses can be suppressed, and leakage of radio frequency energy to the highly conductive substrate can be reduced.

[0109] The shielding layer is preferably a slotted grounded metal shielding layer. Specifically, multiple parallel slits are formed along the main flow direction of the inductor current in the inductor circuit 60. As shown in Table 1 below, by setting it as a slotted grounded metal shielding layer, the closed path of high-frequency induced eddy currents can be effectively interrupted, eddy current losses can be significantly suppressed, and at the same time, the leakage of radio frequency electromagnetic energy to the substrate can be further blocked, thereby improving the quality factor of the inductor.

[0110] Table 1

[0111] In the transmit mode, the first, second, third, and fourth switches of the RF front-end circuit in Example 3 are all closed. At this time, the second capacitor adjustment circuit is grounded through the second switch, and the inductor circuit is grounded through the fourth switch. The two form parallel resonant branches to ground. Since the inductor circuit has a high Q value due to the use of slotted shielding and guard ring structure, and the fourth switch adopts a low on-resistance switching structure, the LC parallel resonant network exhibits high impedance characteristics. This effectively isolates the receiving path when transmitting (TX) large signals, preventing interference with the matching network of the transmitting (TX).

[0112] In receive mode, the first switch, the second switch, the third switch and the fourth switch are all open; in particular, the opening of the first switch causes the output of the transmit amplifier circuit to present a high impedance state in the receive (RX) band, which significantly reduces the noise and reflection path introduced from the transmit (TX) path, which is beneficial to maintaining the low noise figure and good input matching of the receive amplifier circuit 40.

[0113] The preferred geometry of the aforementioned diode is an optimized design that balances ESD capability and parasitic effects, so that the total parasitic junction capacitance under normal operating bias conditions is kept at a low level. This satisfies industrial-grade electrostatic discharge protection standards while avoiding significant degradation of small-signal performance such as noise figure and input return loss, as well as input matching performance of the receiving circuit.

[0114] In summary, through the system-level synergy of the aforementioned switching control strategy, high-Q inductor structure, and two-stage ESD protection mechanism, this invention achieves three major technical effects in a single RF front-end architecture: Achieve efficient power transmission and strong isolation of the receive (RX) path in transmit (TX) mode; Achieve low noise figure and high input matching performance in receive (RX) mode; Provides highly reliable ESD protection in all operating modes; Furthermore, it eliminates the need for additional dedicated matching components or independent ESD units, significantly improving the integration and cost-effectiveness of the SoC, making it suitable for high-performance, high-reliability wireless communication SoC applications.

[0115] By employing an inner and outer spiral structure for the inductor circuit 60 and placing a slotted grounded metal shielding layer directly below it, eddy current losses can be suppressed and leakage of radio frequency energy to the substrate can be reduced.

[0116] By providing a continuous P+ type diffusion protection ring 103 around the inductor circuit and connecting it to the analog ground, in the transmission mode, the first, second, third, and fourth switches are all closed, so that the second capacitor adjustment circuit and the inductor circuit form parallel resonant branches to ground respectively. Because the inductor circuit has a high Q value and the fourth switch has a low on-resistance, the parallel resonant network exhibits high impedance characteristics, effectively isolating the receiving path.

[0117] In receive mode, the first switch, second switch, third switch and fourth switch are all open, and the first switch is open so that the output of the transmitting amplifier circuit presents a high impedance state in the receiving frequency band, so as to reduce the impact on the receiving noise figure.

[0118] Example 4

[0119] Embodiment 4 of the present invention relates to a radio frequency transceiver front-end system, which includes the radio frequency front-end circuits of Embodiments 1 to 3 above.

[0120] This RF transceiver front-end system employs a dynamic switching control strategy to achieve high-power transmission efficiency in transmit mode with strong isolation from the receive path, and low noise figure and good input matching in receive mode, eliminating the need for additional dedicated matching components.

[0121] This RF transceiver front-end system achieves high-reliability electrostatic discharge protection in all operating modes within a single front-end architecture by enabling two-stage ESD discharge paths to work together, without the need to introduce additional independent ESD units.

[0122] This RF transceiver front-end system effectively isolates the receiving path through a high-Q inductor circuit, a fourth switch with low on-resistance, and a parallel resonant network exhibiting high impedance characteristics, thus achieving a balance between transmission efficiency, receiving sensitivity, and electrostatic reliability in a single RF front-end architecture.

[0123] Summarize

[0124] This invention discloses a radio frequency (RF) front-end circuit suitable for system-on-a-chip (SoC). The RF front-end circuit includes a transmit path and a receive path with a shared antenna interface, and integrates transmit / receive switching and electrostatic discharge (ESD) protection functions. The transmit path includes a transmit amplifier circuit, a two-stage capacitor adjustment network, and a balun, with impedance matching achieved through grounding via a first switch, a second switch, and a third switch. The receive path employs an inductor circuit, a fourth switch, and a receive amplifier circuit. In transmit mode, all four switches are closed, forming a high-impedance resonant branch to isolate the receive path. In receive mode, all four switches are open, resulting in a high impedance at the transmit output, reducing noise impact.

[0125] Furthermore, the RF front-end circuit of this invention also employs a two-stage ESD protection architecture: the first stage utilizes a balun symmetrical port to discharge the main current, and the second stage uses a DC blocking capacitor and a complementary PN junction diode to bidirectionally clamp the residual voltage. Thus, this invention achieves high transmit efficiency, low receive noise, and high-reliability electrostatic protection simultaneously within a limited area without the need for additional matching components or a separate ESD unit.

[0126] Furthermore, the RF front-end circuit of the present invention also obtains a high-Q inductor circuit by adopting an inner and outer spiral structure for the inductor circuit in the receiving path and integrating a slotted ground shielding layer and a P+ type diffusion protection ring, thereby suppressing eddy current loss, collecting noise carriers propagating in the substrate, and suppressing interference coupling from other functional modules of the chip (such as digital logic or power circuits), thereby improving the signal integrity and anti-interference capability of the receiving front-end.

[0127] This invention discloses a radio frequency (RF) transceiver front-end system, which includes the aforementioned RF front-end circuit. This RF transceiver front-end system, through a dynamic switching control strategy, achieves high-power transmission efficiency in transmit mode with strong isolation from the receive path, and low noise figure and good input matching in receive mode, eliminating the need for additional dedicated matching components.

[0128] Furthermore, this RF transceiver front-end system achieves high-reliability electrostatic discharge protection in full operating mode within a single front-end architecture by enabling the two-stage ESD discharge paths to work together, without the need to introduce additional independent ESD units.

[0129] Furthermore, this RF transceiver front-end system effectively isolates the receiving path by using a high-Q inductor circuit, a fourth switch with low on-resistance, and a parallel resonant network exhibiting high impedance characteristics, thus achieving a balance between transmission efficiency, receiving sensitivity, and electrostatic reliability in a single RF front-end architecture.

[0130] This concludes the description of a radio frequency front-end circuit according to an embodiment of the present disclosure.

[0131] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of the various embodiments of this disclosure without departing from the scope of this disclosure. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of this disclosure, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A radio frequency front-end circuit, applied to a system-on-a-chip, characterized in that, include: Antenna interface, which connects to the antenna; Transmitter amplifier circuit; Receiver amplifier circuit; The balun has one end of its primary side connected to the output of the transmitting amplifier circuit, the other end of its secondary side connected to the antenna interface, and the other end grounded. An inductor circuit is connected between the input terminal of the receiving amplifier circuit and the antenna interface; A first capacitor, one end of which is connected between the output of the transmitting amplifier circuit and one end of the primary side of the balun; A first switch is connected between the other end of the first capacitor and ground. A second capacitor, one end of which is connected between the antenna interface and one end of the secondary side of the balun; A second switch is connected between the other end of the second capacitor and ground; A third capacitor, one end of which is connected between the output of the transmitting amplifier circuit and the other end of the primary side of the balun; A third switch is connected between the other end of the third capacitor and ground. A fourth switch, one end of which is connected between the input terminal of the receiving amplifier circuit and the inductor circuit, and the other end is grounded. In transmit mode, the first switch, the second switch, the third switch, and the fourth switch are all closed. In receive mode, the first switch, the second switch, the third switch, and the fourth switch are all off.

2. The radio frequency front-end circuit as described in claim 1, Its features are, Includes: a DC blocking capacitor, one end of which is connected to the inductor circuit and the fourth switch respectively; A first diode, one end of which is connected between the other end of the DC blocking capacitor and the input terminal of the receiving amplifier circuit, and the other end grounded; and The second diode has one end connected between the other end of the DC blocking capacitor and the input terminal of the receiving amplifier circuit, and the other end grounded.

3. The radio frequency front-end circuit as described in claim 2, characterized in that, The first diode is composed of a P+ diffusion region and an N-type well, and the second diode is composed of an N+ diffusion region and a P-type substrate.

4. The radio frequency front-end circuit as described in claim 1, characterized in that, The inductor circuit has a first coil and a second coil, the second coil surrounding the first coil, the first coil and the second coil sharing the same central axis and having the same winding direction.

5. The radio frequency front-end circuit as described in claim 1, characterized in that, A shielding layer is provided directly below the inductor circuit, and this shielding layer is grounded.

6. The radio frequency front-end circuit as described in claim 5, characterized in that, The shielding layer is composed of an underlying metal.

7. The radio frequency front-end circuit as described in claim 5, characterized in that, The shielding layer has multiple parallel slits along the main flow direction of the inductor current in the inductor circuit.

8. The radio frequency front-end circuit as described in claim 1, characterized in that, A continuous P+ type diffusion protection ring is provided around the inductor circuit, and the P+ type diffusion protection ring is connected to the analog ground.

9. The radio frequency front-end circuit as described in claim 1, characterized in that, The fourth switch adopts a low on-resistance switching structure.

10. A radio frequency transceiver front-end system, characterized in that, include: The radio frequency front-end circuit as described in any one of claims 1 to 9.

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