Heterojunction power device

Abstract

The embodiment of the utility model relates to a heterojunction power device. A heterojunction power device, comprising: a substrate comprising a semiconductor material; a first active region and a second active region symmetrically and oppositely disposed on the substrate with respect to the axis of symmetry and housing a corresponding heterostructure; and a separation region extending between the first active region and the second active region along the axis of symmetry. The power device further includes a first conductive bus configured to distribute a first potential of the power device in parallel to the first active region and the second active region; and a second conductive bus configured to distribute a second potential, different from the first potential, of the power device in parallel to the first active region and the second active region. The first conductive bus and the second conductive bus extend over the separation region along the axis of symmetry, and the second conductive bus overlaps over the first conductive bus.

Description

Technical Field

[0001] The utility model relates to a "high electron mobility transistor" (HEMT) power device with reduced gate oscillation. Background Art

[0002] HEMT devices, also often referred to as "heterostructure field effect transistors" (HFETs), have properties that make them increasingly suitable and widespread in high power and fast switching applications; these properties include their ability to operate at high voltages and their high breakdown voltages, with values ​​up to several hundred volts, as well as high density and mobility of charge carriers.

[0003] In a HEMT device, a semiconductor heterostructure (usually based on AlGaN / GaN layers, and therefore the device is also referred to as a "GaN power device") allows the spontaneous generation of a so-called two-dimensional electron gas (2DEG) in the device, effectively forming a conductive channel for the charges. In use, the spontaneous channel can be modulated by applying an appropriate voltage to the gate region of the device (usually referred to as the "gate").

[0004] GaN power devices used in fast switching applications (such as, for example, electric traction and energy conversion, with a typical "half-bridge" circuit configuration) are subject to high gradients of the voltage between the drain and source terminals (commonly referred to as the drain and source terminals) and of the current flowing between these terminals. In this type of device, the rapid changes in the drain-source voltage and its current over time may be combined with a relatively low threshold voltage level (i.e., the turn-on voltage level of the device) at the gate terminal (on the order of a few volts).

[0005] For safe operation of power devices, it is beneficial to protect the gate terminal from voltage peaks that may exceed the threshold voltage; these peaks may be triggered by, for example, the Miller effect or by oscillations caused by resonance phenomena involving the inductance of the conductive path of the gate signal and the capacitance of the device substrate. If the gate signal path is not designed correctly in terms of parasitic components (resistance and inductance), the oscillations on the gate terminal may be of the continuous type (i.e., lasting for a period of time) or of the "ringing" type (i.e., of limited duration), which may lead to malfunction of the device or even to damage of the gate region.

[0006] In order to mitigate the oscillation phenomenon on the gate terminal of GaN power devices, different topologies of the distribution grid of the gate signal have been analyzed in the literature. It was found that the temporal stability of the gate signal waveform during the switching of the device may be unsatisfactory, depending on the relevant application. Utility Model Content

[0007] Embodiments of the present disclosure overcome or at least mitigate the disadvantages and limitations of the prior art.

[0008] In one embodiment, a heterojunction power device includes: a substrate including a semiconductor material, and a first active region and a second active region, the first active region and the second active region are symmetrically arranged on the substrate relative to a symmetry axis and accommodate corresponding heterostructures. The device includes: a separation region extending between the first active region and the second active region along the symmetry axis; a first conductive bus configured to distribute a first potential of the heterojunction power device to the first active region and the second active region in parallel; and a second conductive bus configured to distribute a second potential of the heterojunction power device that is different from the first potential to the first active region and the second active region in parallel. The first conductive bus and the second conductive bus extend along the symmetry axis above the separation region, and the second conductive bus is superimposed on the first conductive bus.

[0009] In one embodiment, the first conductive bus is a gate bus, and the first potential is a control signal of the heterojunction power device.

[0010] In one embodiment, the second conductive bus is a source bus, and the second potential is a source potential of the heterojunction power device.

[0011] In one embodiment, the heterojunction power device also includes a first metallization level, wherein the first conductive bus is part of the first metallization level; the first metallization level also includes: a first-level drain electrode and a first-level source electrode associated with the first active region, extending laterally to the first conductive bus and superimposed on the first active region; and a first-level drain electrode and a first-level source electrode associated with the second active region, extending laterally to the first conductive bus, superimposed on the second active region, and separated from the first-level drain electrode and the first-level source electrode associated with the first active region at a separation region.

[0012] In one embodiment, a first-level drain electrode and a first-level source electrode associated with a first active region are arranged in a symmetrical manner to a corresponding first-level drain electrode and a first-level source electrode associated with a second active region relative to an axis of symmetry; and in the first active region and in the second active region, the first-level drain electrodes are arranged alternately with the first-level source electrodes along the axis of symmetry.

[0013] In one embodiment, the heterojunction power device also includes a second metallization level superimposed on the first metallization level, and the second conductive bus is part of the second metallization level; the second metallization level also includes: a second-level drain electrode and a second-level source electrode associated with the first active area, extending transversely to the second conductive bus and superimposed on the first active area; a second-level drain electrode and a second-level source electrode associated with the second active area, extending transversely to the second conductive bus and superimposed on the second active area; the second-level source electrode extends from the second conductive bus in an opposite direction relative to the axis of symmetry; and the second-level drain electrode associated with the first active area is separated from the second-level drain electrode associated with the second active area at a separation area.

[0014] In one embodiment, the second-level drain electrode and the second-level source electrode associated with the first active region are arranged in a symmetrical manner to the second-level drain electrode and the second-level source electrode associated with the second active region relative to the axis of symmetry; and the second-level drain electrode is arranged alternately with the second-level source electrode along the axis of symmetry.

[0015] In one embodiment, the heterojunction power device also includes a third metallization level superimposed on the second metallization level, and the third metallization level is provided with: a drain metallization region superimposed on the first active region; a source metallization region superimposed on the second active region; a third-level drain electrode and a third-level source electrode, extending transversely to the symmetry axis starting from the drain metallization region and the source metallization region, respectively; and the third-level drain electrode is arranged alternately with the third-level source electrode along the symmetry axis.

[0016] In one embodiment, the heterojunction power device further includes a second level conductive via between the first metallization level and the second metallization level and a third level conductive via between the second metallization level and the third metallization level.

[0017] In one embodiment, the first active region and the second active region each include: a corresponding channel layer and a corresponding barrier layer defining a corresponding heterojunction; a plurality of corresponding active elements extending transversely to the axis of symmetry and periodically arranged along the axis of symmetry, wherein the active elements include corresponding portions of the channel layer and corresponding portions of the barrier layer and corresponding gate regions, the gate regions being contact-superimposed on the barrier layers of the corresponding active regions; the active elements each also include a drain terminal, a source terminal and a gate terminal; and the gate terminal includes a gate electrode, the gate electrode being contact-superimposed on the corresponding gate region and extending transversely to the axis of symmetry.

[0018] In one embodiment, the third-level drain electrode, the second-level drain electrode, the first-level drain electrode and the drain terminal of the active element are superimposed on each other and are all electrically connected to each other in a direct manner; the third-level source electrode, the second-level source electrode, the second conductive bus, the first-level source electrode and the source terminal of the active element are superimposed on each other and are all electrically connected to each other in a direct manner; and the first-level drain electrode and the first-level source electrode have corresponding contact portions, which extend transversely to the axis of symmetry and form a drain terminal and a source terminal.

[0019] In one embodiment, the first conductive bus, the gate electrode, and the gate terminal are all electrically connected to each other in a direct manner.

[0020] In one embodiment, the active elements are HEMT type transistors electrically connected in parallel to each other and formed using gallium nitride technology.

[0021] The heterojunction power device provided according to the present disclosure has the technical effect of reduced gate oscillation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] For a better understanding of the present disclosure, preferred embodiments are provided by way of non-limiting examples with reference to the accompanying drawings, in which:

[0023] Figure 1 is a top view of a power device according to an embodiment of the present disclosure;

[0024] Figure 2 According to the embodiment of the present disclosure Figure 1 A perspective view of an internal portion of a power device;

[0025] Figure 3 According to the embodiment of the present disclosure Figure 1 A cross section of an internal portion of a power device;

[0026] Figure 4 According to the embodiment of the present disclosure Figure 1 Electrical diagrams related to the power devices; and

[0027] Figure 5-Figure 7 According to the embodiment of the present disclosure Figure 1 A top view of a power device during a subsequent step in its manufacturing process. DETAILED DESCRIPTION

[0028] refer to Figure 1, a power device according to an embodiment of the utility model is indicated as a whole by the number 1, and comprises a bare die or chip 2 and a frame 3 in which the bare die 2 is accommodated. The power device 1 also includes: a first terminal 4, a second terminal 6 and a third terminal 8, which respectively define an external drain terminal, an external source terminal and an external gate terminal (also referred to as a "control terminal") of the power device 1 in use; a fourth terminal 10, also referred to as a "sense terminal" or "Kelvin terminal", which defines a reference for a control signal applied to the external gate terminal 8, and is therefore used to switch the power device 1, and is usually at the same potential as the external source terminal 6.

[0029] The terminals 4 , 6 , 8 , 10 of the power device 1 may be mechanically coupled to the frame 3 and electrically connected to corresponding pads of the die 2 by bonding wires 12 (see below).

[0030] The power device 1 may also include an insulator (not shown in the drawings) of resin or other polymer material, from which the terminals 4, 6, 8, 10 may protrude, through a plurality of protrusions (at least one) for the respective terminals, which remain exposed so as to be accessible from the outside.

[0031] Figure 2 The diagram shows an inner portion of the die 2 in a three-axis reference system of mutually orthogonal axes X, Y, and Z. The die 2 includes an active region 20 extending in a planar manner in the X-axis and Y-axis directions over a substrate 21 and divided into first and second active regions 20a and 20b that are identical to each other along the Y-axis.

[0032] The first active area 20a and the second active area 20b extend in the same manner as each other inside the die 2, i.e., they have the same size along the X-axis and the Y-axis and are arranged symmetrically relative to each other with respect to the symmetry axis H parallel to the X-axis. The first active area 20a and the second active area 20b are also separated by a separation area 23 of the same semiconductor material as the substrate 21, which is arranged in the center of the die 2 and extends parallel to the symmetry axis H. Therefore, the first active area 20a and the second active area 20b are at a certain distance from each other, and the separation area 23 is interposed between the two. The first active area 20a and the second active area 20b define two identical and independent power modules of the power device 1.

[0033] The substrate 21 may include, for example, a silicon (Si) layer or a silicon carbide (SiC) layer and a gallium nitride (GaN) buffer layer, which are not separately shown in the drawings.

[0034] The first active region 20a and the second active region 20b include a plurality of active elements 22, which are identical to each other and are distributed in a mirror manner. Figure 3As shown in FIG. 1 , the active elements 22 are equal to each other, arranged side by side in a periodic manner along the X-axis and extending parallel to the Y-axis.

[0035] The active element 22 may be a transistor of the HEMT type. In this case, the first active area 20a and the second active area 20b each include a channel layer 25 and a barrier layer 27. The channel layers 25 of the first active area 20a and the second active area 20b extend on the substrate 21 and are formed of a first semiconductor material, such as gallium nitride (GaN). The barrier layers 27 are each superimposed in contact on the corresponding channel layer 25 and are formed of a second semiconductor material, such as aluminum gallium nitride (AlGaN), which is different from the first semiconductor material. The channel layer 25 and the barrier layer 27 may have, for example, N-type conductivity and define a heterostructure. The interface between the channel layer 25 and the barrier layer 27 defines a heterojunction 31.

[0036] The active element 22 is provided with respective drain terminals 24 , source terminals 26 and gate terminals 28 and comprises respective portions of a channel layer 25 and a barrier layer 27 and a respective gate region 29 .

[0037] Each gate region 29 extends over and contacts the corresponding barrier layer 27 and serves as a control region of each active element 22, in particular as a channel modulation region; the gate region 29 is formed of a conductive material, usually a third doped semiconductor material, such as, for example, p-type conductive gallium nitride (pGaN). As is well known, the gate region 29 operates according to the voltage applied thereto so as to adjust the thickness of the conductive channel formed at the interface between the channel layer 25 and the barrier layer 27; in addition, the gate region 29 ensures the operation of the HEMT type active element 22 in the so-called "normally off" mode.

[0038] Thus, the power device 1 of the present embodiment may be a GaN type HEMT power device, which utilizes a plurality of elementary cells (i.e. active elements 22) electrically connected in parallel, typical in the field, in order to increase its conductive properties (in terms of the maximum current that can be supplied) to the external drain and source terminals 4, 6. The die 2 of the power device 1 may have a maximum dimension equal to 7 mm along the X axis and 2÷3 mm along the Y axis, for example, and each power module defined by the first active area 20a and the second active area 20b may contain, for example, 50÷200 active elements 22. The first active area 20a and the second active area 20b may extend along the Y axis, with a typical length equal to 0.5÷1.5 mm, and the associated separation area 23 may extend along the Y axis, for example, 20÷60 μm.

[0039] The drain, source and gate terminals 24, 26, 28 of each active element 22 are substantially strip-shaped and are arranged according to Figure 2 The topology shown in FIG extends parallel to the Y axis.

[0040] In detail, the gate terminal 28 (e.g., a conductive multilayer of TiN / AlCu / TiN) of each active element 22 extends over and is in direct electrical contact with the corresponding gate region 29 and is formed by a common metallization step for all active elements 22 of both the first active area 20a and the second active area 20b. Specifically, the gate terminal 28 is defined by a corresponding gate electrode or "fingers" 30, which extend uninterruptedly along the Y axis through all active areas 20 (including the separation area 23) and symmetrically connect the gate regions 29 relative to the symmetry axis H.

[0041] In other words, the gate electrode 30 extends parallel to the Y axis through the entire length of the die 2 and also extends over the separation region 23. The gate electrode 30 is obtained after deposition and lithographic definition steps using typical techniques in the art ("etching").

[0042] For the first active area 20a, the drain terminal 24 and the source terminal 26 of each active element 22 are defined by the corresponding drain electrode 40a and by the corresponding source electrode 50a, while for the second active area 20b, they are defined by the corresponding drain electrode 40b and the corresponding source electrode 50b. The drain electrodes 40a, 40b have equal extension along the Y axis, and the source electrodes 50a, 50b have equal extension along the Y axis. The positions of the drain electrode 40a and the source electrode 50a are symmetrical with respect to the H axis and the positions of the drain electrode 40b and the source electrode 50b, respectively. In addition, the drain electrodes 40a, 40b are separated from each other at the separation area 23, and the same is true for the source electrodes 50a, 50b. The drain electrodes 40a, 40b and the source electrodes 50a, 50b are formed starting from the same first metallization level M1, over and through a first intermediate insulating layer 100 of dielectric material, which covers the active region 20. The drain electrodes 40a, 40b and the source electrodes 50a, 50b are referred to hereinafter as first-layer drain electrodes and first-layer source electrodes.

[0043] Consider the first active region 20a (but the same considerations apply to the second active region 20b) and see Figure 2 and Figure 3, the first-level drain electrode 40a and the first-level source electrode 50a extend alternately with each other over the first active region 20a along the X-axis to form a repeating pattern. The first-level drain electrode 40a and the first-level source electrode 50a are in direct contact with the heterostructure of the first active region 20a, defining the corresponding drain terminal 24 and source terminal 26 of the associated active element 22. More precisely, the first-level drain electrode 40a and the first-level source electrode 50a have corresponding contact portions 45a, 46a (the contact portions 45b, 46b refer to the second active region 20b in the same manner), and the corresponding contact portions 45a, 46a extend through the first intermediate insulating layer 100 and extend along the Y-axis to form the drain terminal 24 and the source terminal 26.

[0044] In detail, the first level source electrode 50a is shared by two adjacent active elements 22, so they share the same source terminal 26. The first level source electrode 50a extends over a pair of consecutive gate electrodes 30 and contacts the first active region 20a at a position midway between these consecutive gate electrodes 30.

[0045] The alternating pattern of the first-level drain electrodes 40a and the first-level source electrodes 50a makes it possible to observe two adjacent active elements 22 ( Figure 3 ), the two first-level drain electrodes 40a placed laterally and symmetrically relative to the first-level source electrode 50a correspond to the central first-level source electrode 50a. In addition, the first-level source electrode 50a extends above the corresponding gate electrode 30 pair, so that the projection of these gate electrodes 30 along the Z axis is completely contained in these source electrodes 50a; this type of arrangement generally ensures the electrical shielding function of the corresponding gate region 29.

[0046] The first metallization level M1 also comprises a main electrode or gate "bus" 35, which extends in a transverse manner to the gate electrode 30, i.e. along the X axis. In detail, the gate bus 35 extends above the gate electrode 30 and is located in the center of the die 2: the gate bus 35 is actually between the first active area 20a and the second active area 20b at the separation area 23, on which the gate bus 35 is superimposed; the H axis is therefore the symmetry axis of the gate bus 35. In other words, the gate bus 35 extends above the area of ​​the die 2 where there are no active elements 22.

[0047] The gate bus 35 is electrically connected to the gate electrode 30 by a conductive material through hole (not shown in the drawings) extending along the Z axis, and distributes the external control signal to the gate electrode 30 and thus to the active element 22. The central arrangement of the gate bus 35 allows the control signal to be distributed symmetrically and balanced in terms of the parasitic components of the electrical path to the two power modules defined by the first active area 20a and the second active area 20b: therefore, the relative gate area 29 is switched in parallel for all active elements 22 almost simultaneously and in a balanced manner; therefore, the driving of the two power modules is consistent.

[0048] The gate bus 35 may have a length close to the length along the X-axis of the die 2 and a width (along the Y-axis) typically between 10 and 50 μm.

[0049] The first metallization level M1 is separated from the active area 20 along the Z-axis direction by a first intermediate insulating layer 100. The electrical connection between the first level drain and source electrodes 40a, 40b, 50a, 50b and the drain and source terminals 24, 26 of the active element 22 is ensured by contact portions 45a, 46a, 45b, 46b through the first intermediate insulating layer 100.

[0050] The first level drain and source electrodes 40a, 40b, 50a, 50b and the gate bus 35 are all obtained starting from the same deposition and definition process of the first metallization level M1 and may be formed, for example, with a multilayer of TiN / AlCu / TiN.

[0051] The power device 20 also includes a second insulating layer 101 on the first intermediate insulating layer 100 and a second metallization level M2 of the power device 20 on the second intermediate insulating layer 101. The second metallization level M2 is stacked on the first metallization level M1 and includes: a source main electrode ("bus") 55; a second level drain electrode 60a and a second level source electrode 70a on the first active area 20a; a second level drain electrode 60b and a second level source electrode 70b on the second active area 20b. The source bus 55 extends along the X-axis, while the second level drain electrodes 60a, 60b and the second level source electrodes 70a, 70b extend in a manner transverse to the source bus 55, that is, along the Y-axis. The second level source electrodes 70a, 70b are directly electrically and structurally connected to the source bus 55. More precisely, the second-level source electrodes 70 a , 70 b integrally extend from the source bus line 55 toward the respective first and second active regions 20 a and 20 b in opposite directions with respect to the H-axis, and represent “fingers” of the source bus line 55 .

[0052] In detail, the source bus 55 extends along the H axis, which is also its axis of symmetry, and completely superposes the gate bus 35, electrically shielding it: the shielding function given by the structure of the source connection of the second metallization level M2 will be explained in more detail below.

[0053] The source bus 55 may have a length close to the dimension of the die 2 along the X-axis, and a width at least equal to the width of the gate bus 35 along the Y-axis, and typically has a value between 10 and 50 μm.

[0054] Consider the first active region 20a (but the same considerations apply to the second active region 20b) and see Figure 2 and Figure 3 , the second-level drain electrodes 60a and the second-level source electrodes 70a are alternately arranged with each other along the X-axis to form a repeating pattern. Specifically, the second-level drain electrodes 60a are "staggered" between two consecutive second-level source electrodes 70a. In addition, the second-level drain electrodes 60a and the second-level source electrodes 70a are at least partially superimposed on the corresponding first-level drain electrodes 40a and the first-level source electrodes 50a. The second-level drain electrodes 60a and the second-level source electrodes 70a are electrically connected to the corresponding first-level drain electrodes 40a and the first-level source electrodes 50a through the second-level through holes 65 of the conductive material extending along the Z-axis.

[0055] Therefore, the structure of the source connection of the second metallization level M2 is such that the second level source electrode pair 70a, 70b extends from the source bus 55 toward the first active area 20a and the second active area 20b respectively in a symmetrically opposite manner relative to the H axis, and is respectively superimposed on the first level source electrode pair 50a, 50b.

[0056] The second-level drain electrodes 60 a , 60 b are separated from each other at the separation region 23 .

[0057] The second metallization level M2 is separated from the first metallization level M1 along the Z axis by a second intermediate insulating layer 101. The electrical connection between the second level drain and source electrodes 60a, 60b, 70a, 70b and the first level drain and source electrodes 40a, 40b, 50a, 50b is ensured by second level vias 65 passing through the second intermediate insulating layer 101.

[0058] The second level drain and source electrodes 60a, 60b, 70a, 70b and the source bus 55 are all obtained starting from the same deposition and definition process of the second metallization level M2 and may be formed, for example, with a multilayer of TiN / AlCu / TiN.

[0059] The power device 20 includes a third intermediate insulating layer 102 on the second intermediate insulating layer 101 and a third metallization level M3 on the third intermediate insulating layer 102. The third metallization level M3 is stacked on the second metallization level M2 and includes: a drain metallization region 85 and a source metallization region 95, which are identical and symmetrical about the H axis, a third layer of drain electrode 80 extending from the drain metallization region 85, and a third layer of source electrode 90 extending from the source metallization region 95. The drain and source regions 85, 95 are stacked on the first active area 20a and the second active area 20b, respectively. The third layer of drain and source electrodes 80, 90 extends from the corresponding drain and source regions 85, 95 as a whole along the Y axis. The third level drain electrode 80 and the source electrode 90 extend above the second metallization level M2 starting from the drain region 85 and the source region 95, respectively, so that along the X-axis, the third level drain electrodes 80 alternate with the third level source electrodes 90, i.e., they are "staggered" with each other (see Figure 7 ).

[0060] As a result, the third level drain and source electrodes 80, 90 form "fingers" of respective drain and source regions 85, 95. In addition, each third level drain electrode 80 is (at least partially) superimposed on and electrically connected to the second level drain electrode pair 60a, 60b symmetrically opposed with respect to the H axis. Similarly, each third level source electrode 90 is (at least partially) superimposed on and electrically connected to the second level source electrode pair 70a, 70b symmetrically opposed with respect to the H axis. These electrical connections between the third metallization level M3 and the second metallization level M2 are formed by third layer vias 75 of conductive material that extend through the third intermediate insulating layer 102 along the Z axis.

[0061] The third-layer drain and source electrodes 80 , 90 and the drain and source regions 85 , 95 are all obtained starting from the same deposition and definition process of the third metallization level M3 and may be formed, for example, with a multilayer of TiN / AlCu / TiN.

[0062] In a power device of this type, the third metallization level M3 may also be provided with pads allowing electrical connection to the different external potential layers described above.

[0063] Specifically, see Figure 1 , Figure 2 and Figure 7, the drain pad 86 extends over the drain metallization region 85, and it is directly electrically connected to the drain metallization region 85, while the source pad 96 extends over the source metallization region 95, and it is directly electrically connected to the source metallization region 95. In addition, the third metallization level M3 includes a gate pad 36, which is usually placed at a corner of the die 2 and arranged side by side with the source metallization region 95, and it is electrically insulated from the source metallization region 95. The gate pad 36 is electrically connected to the gate bus 35 through at least one through hole of a conductive material, and the through hole extends along the Z axis (not shown in the drawings) through the intermediate insulating layer 100, 101, 102 until the first metallization level M1; then the gate pad 36 provides an external control signal to the gate bus 35 to be distributed to the active element 22.

[0064] The drain, source and gate pads 86, 96, 36 are available for coupling with bond wires 12 in the "lead frame" definition of the power device 1. Specifically, the drain pad 86 is connected to the external drain terminal 4, the source pad 96 is connected to the external source terminal 6, and the gate pad 36 is connected to the external gate terminal 8. Thus, the sense terminal 10, which is generally at the same potential as the external source terminal 6, is connected to the source pad 96.

[0065] Thus, in the presented embodiment, the first, second and third metallization levels M1, M2 and M3 ensure that the drain, source and gate electrical paths reach the respective correct potentials in relation to the externally applied voltage, thereby allowing current to flow through the structure of the power device 1 .

[0066] It should be noted that Figure 2 In the figure, for ease of understanding, the first metallization level M1 , the second metallization level M2 , the third metallization level M3 and the portion of the gate electrode 30 are intentionally omitted.

[0067] The same dimensions of the first active area 20a and the second active area 20b allow to maintain a balance in terms of the conduction path of the current flowing between the external drain terminal 4 and the source terminal 6; in fact, these terminals and the corresponding drain and source pads 86, 96 of the present topology are shared by the first active area 20a and the second active area 20b. At the same time, the arrangement of the gate bus 35 above the separation area 23 allows to isolate the distribution grid of the control signal from the potential difference between the drain and source electrodes of the power device 1 in use, which potential difference can assume, for example, a value two orders of magnitude greater than the voltage level of the control signal.

[0068] The first and second metallization levels M1, M2 of the power device 1 are configured to minimize inductive parasitic components of the electrical path of the control signal; any unwanted oscillations of the control signal during the switching steps are thus reduced, thereby reducing the likelihood of damage to the gate region 29.

[0069] In detail, the cancellation phenomenon of the control signal currents flowing in opposite directions helps to minimize the inductive parasitic components. This cancellation is achieved by the above topology and in more detail by the gate loop created by the arrangement of the first metallization level M1 and the second metallization level M2.

[0070] refer to Figure 2 and Figure 4 When a control signal T is applied between the external gate terminal 8 and the sensing terminal 10, the forward current I GG flows in the negative direction of the X direction in the gate bus line 35, and the corresponding return current I SK The positive current I flows in the X direction in the source bus line 55, that is, in the positive direction with the positive current I GG The return current I SK In effect sharing the same conductive path as the source metallization, since sense terminal 10 is connected to source pad 96 as described; thus, source bus 55 represents the return path for the control signal loop, sense terminal 10 being the reference terminal for the voltage applied to external gate terminal 8 .

[0071] The superposition of the source bus 55 described above on the gate bus 35 ultimately allows the forward current I GG and return current I SK The inductive effects of the currents are cancelled out because they flow in opposite directions; therefore, the source bus 55 has an electrical shielding function for the gate bus 35. Furthermore, since the source bus 55 and the gate bus 35 run along the symmetry axis H in the central region of the power device 1, switching synchronization of the active elements 22 is ensured.

[0072] Figure 4 The mechanism for counteracting the current flow of the control signal is shown in the circuit diagram. In detail, the circuit diagram has two above-mentioned HEMT type active elements 22 connected in parallel with each other. Through the external gate terminal 8 and the sense terminal 10, the control signal (graphically represented by a square wave generator T) is applied between the gate terminal 28 and the source terminal 26 of the active element 22, generating a forward and return current I GG ,I SK Inductance L GG and L SK They represent the parasitic components of the power device 1 in the gate loop (in the forward and return paths); the inductor L DBOND and L SBOND The capacitance C represents the inductance loss generated by the bonding wire 12 (referred to as "bonding inductance"). DB and C SB They exist between the drain terminal 24 and the substrate 21 and between the source terminal 26 and the substrate 21 , respectively.

[0073] Therefore, due to the cancellation of current flow, the inductor parasitic component L GG and L SK The minimization of the substrate capacitance C DB and C SB The possibility of “LC” type resonant circuits; these resonant circuits are in fact one of the causes of uncontrolled oscillations and peaks at the gate terminal 28 during the switching phase.

[0074] The power device 1 described can be obtained by the following simplified manufacturing method, according to which, Figure 5-Figure 7 As shown in FIG. 4 , a first metallization level M1 , a second metallization level M2 and a third metallization level M3 of the die 2 are deposited and defined.

[0075] Specifically, the die 2 is provided as part of a semiconductor wafer (not shown) and is provided with a substrate 21, an active region 20 and a gate electrode 30; the substrate 21, the active region 20 and the gate electrode 30 are protected by a first intermediate insulating layer 100 of dielectric material. The first deposition of the metal layer ( Figure 5 ) and subsequent photolithographic definition (using etching methods typical of the art) produce a first metallization level M1. In detail, a first level drain and source electrode 40a, 40b, 50a, 50b and a gate bus 35 are formed. Figure 5 As can be observed in FIG. 1 , the gate bus 35 is “L” shaped outside the active area 20 so that it can be connected to the gate pad 36 of the subsequent third metallization level M3 through an associated through hole (not shown in the drawings) of a conductive material.

[0076] Contact portions 45a, 46a, 45b, 46b are also defined at the associated openings already formed in the first intermediate insulating layer 100 in order to ensure electrical connection between the first metallization level M1 and the underlying gate electrode 30 and the active region 20 (cf. Figure 3 ).

[0077] A second intermediate insulating layer 101 is then formed, which covers the first metallization level M1. Subsequently, (using possibly the same technique as the first deposition) a metal layer ( Figure 6 ) and subsequent photolithographic definition produce a second metallization level M2. In detail, the second drain and source electrodes 60a, 60b, 70a, 70b and the source bus 55 are formed. Figure 6 As can be observed in FIG. 1 , the source bus line 55 is also shaped (“L”) so as to shield the underlying gate bus line 35 throughout its entire extension.

[0078] Second level vias 65 are also defined at the associated openings formed in the second intermediate insulating layer 101 in order to ensure electrical connection between the second metallization level M2 and the first metallization level M1 (for Figure 3 for reference).

[0079] A third intermediate insulating layer 102 is then formed, which covers the second metallization level M2. Subsequently, a third deposition of a metal layer (possibly using the same technique as the first and second depositions) is performed. Figure 7 ) and subsequent photolithographic definition produce a third metallization level M3. In detail, a third level drain electrode and source electrode 80, 90 and drain and source regions 85, 95 are formed; subsequently, drain pads, source pads and gate pads 86, 96, 36 are also defined.

[0080] A third level through hole 75 is also defined at the associated opening formed in the third intermediate insulating layer 102 in order to ensure electrical connection between the third metallization level M3 and the second metallization level M2 (for Figure 3 for reference).

[0081] Finally, in a manner not shown in the figures, the last step of the present manufacturing method is as follows, comprising: depositing any dielectric passivation layer above the third metallization level M3, dicing the wafer to obtain the die 2, positioning the die 2 in the frame 3 and coupling the pads of the die 2 to the relevant external terminals by wire bonding 12, and thus co-molding the insulator, so as to obtain Figure 1 Power device 1.

[0082] Finally, it is evident that modifications and variations may be made to what is herein described and illustrated, without thereby departing from the scope of the present disclosure, as defined in the appended claims.

[0083] For example, the active element 22 may be of a type other than the GaN HEMT type, such as a MOSFET (“Metal Oxide Semiconductor Field Effect Transistor”) transistor, a superjunction MOSFET, an IGBT (“Insulated Gate Bipolar Transistor”), etc., capable of operating at high voltages (up to several hundred volts) and currents with fast switching time trends.

[0084] The active region 20 may include, for example, in addition to the above-mentioned channel layer 25, barrier layer 27 and gate region 29, other layers within the associated heterostructure defined by the first and second active regions 20a, 20b.

[0085] In addition to the above-mentioned first metallization level M1 , second metallization level M2 and third metallization level M3 , the die 2 may for example also be provided with further metallization levels and associated intermediate insulating layers.

[0086] A heterojunction power device can be summarized as comprising: a substrate (21) comprising a semiconductor material; a first active region (20a) and a second active region (20b) which are arranged symmetrically relative to a symmetry axis (H) on the substrate (21) and accommodate corresponding heterostructures (25, 27, 29); a separation region (23) which extends along the symmetry axis (H) between the first active region (20a) and the second active region (20b); a first conductive bus (35) which is configured to connect a first potential (V G ) are distributed in parallel to the first active area and the second active area (20a, 20b); and a second conductive bus (55) configured to connect the power device (1) to the first potential (V G ) Different second potential (V S ) are distributed in parallel to the first active area and the second active area (20a, 20b), wherein the first conductive bus and the second conductive bus (35, 55) extend above the separation area (23) along the symmetry axis (H), and the second conductive bus (55) is superimposed on the first conductive bus (35).

[0087] The first conductive bus (35) may be a gate bus, the first potential (V G ) can be a control signal of the power device (1).

[0088] The second conductive bus (55) may be a source bus, and the second potential (V S ) can be the source potential of the power device (1).

[0089] The power device may include a first metallization level (M1), wherein the first conductive bus (35) may be a part of the first metallization level (M1); the first metallization level (M1) further includes: a first-level drain electrode (40a) and a first-level source electrode (50a) associated with the first active region (20a), which extend transversely to the first conductive bus (35) and are superimposed on the first active region (20a); and a first-level drain electrode (40b) and a first-level source electrode (50b) associated with the second active region (20b), which extend transversely to the first conductive bus (35), are superimposed on the second active region (20b), and are separated from the first-level drain electrode (40a) and the first-level source electrode (50a) associated with the first active region (20a) at a separation region (23).

[0090] A first-level drain electrode (40a) and a first-level source electrode (50a) associated with a first active region (20a) can be arranged in a symmetrical manner to a corresponding first-level drain electrode (40b) and a first-level source electrode (50b) associated with a second active region (20b) relative to an axis of symmetry (H); and wherein in the first active region (20a) and in the second active region (20b), the first-level drain electrodes (40a, 40b) can be arranged alternately with the first-level source electrodes (50a, 50b) along the axis of symmetry (H).

[0091] The power device may include a second metallization level (M2) superimposed on the first metallization level (M1), wherein the second conductive bus (55) may be a part of the second metallization level (M2); the second metallization level (M2) further includes: a second level drain electrode (60a) and a second level source electrode (70a) associated with the first active area (20a), which extend transversely to the second conductive bus (55) and are superimposed on the first active area (20a); a second level associated with the second active area (20b); A first-level drain electrode (60b) and a second-level source electrode (70b) extend transversely to the second conductive bus (55) and are superimposed on the second active area (20b); the second-level source electrodes (70a, 70b) extend from the second conductive bus (55) in opposite directions relative to the symmetry axis (H); and the second-level drain electrode (60a) associated with the first active area (20a) is separated from the second-level drain electrode (60b) associated with the second active area (20b) at a separation area (23).

[0092] The second-level drain electrode (60a) and the second-level source electrode (70a) associated with the first active region (20a) can be arranged in a symmetrical manner to the second-level drain electrode (60b) and the second-level source electrode (70b) associated with the second active region (20b) relative to the symmetry axis (H); and the second-level drain electrodes (60a, 60b) can be arranged alternately with the second-level source electrodes (70a, 70b) along the symmetry axis (H).

[0093] The power device may include a third metallization level (M3) superimposed on the second metallization level (M2) and provided with: a drain metallization region (85) superimposed on the first active region (20a); a source metallization region (95) superimposed on the second active region (20b); a third-level drain electrode (80) and a third-level source electrode (90), extending transversely to the symmetry axis (H) starting from the drain metallization region (85) and the source metallization region (95), respectively; and the third-level drain electrode (80) is arranged alternately with the third-level source electrode (90) along the symmetry axis (H).

[0094] The power device may include a second level conductive via (65) between a first metallization level (M1) and a second metallization level (M2) and a third level conductive via (75) between the second metallization level (M2) and a third metallization level (M3).

[0095] The first active region and the second active region (20a, 20b) may each include: a corresponding channel layer (25) and a corresponding barrier layer (27) defining a corresponding heterojunction (31); a plurality of corresponding active elements (22) extending transversely to the symmetry axis (H) and being periodically arranged along the symmetry axis (H), wherein the active elements (22) include corresponding portions of the channel layer (25) and the barrier layer (27) and a corresponding gate region (29), the gate region (29) being contact-superimposed on the barrier layer (27) of the corresponding active region (20a, 20b); the active elements (22) each also include a drain terminal (24), a source terminal (26) and a gate terminal (28); and the gate terminal (28) includes a gate electrode (30), the gate electrode (30) being contact-superimposed on the corresponding gate region (29) and extending transversely to the symmetry axis (H).

[0096] The third-level drain electrode (80), the second-level drain electrode (60a, 60b), the first-level drain electrode (40a, 40b) and the drain terminal (24) of the active element (22) can be superimposed on each other and all electrically connected to each other in a direct manner; the third-level source electrode (90), the second-level source electrode (70a, 70b), the second conductive bus (55), the first-level source electrode (50a, 50b) and the source terminal (26) of the active element (22) can be superimposed on each other and all electrically connected to each other in a direct manner; and the first-level drain electrode (40a, 40b) and the first-level source electrode (50a, 50b) can have corresponding contact portions (45a, 46a, 45b, 46b) which extend transversely to the symmetry axis (H) and form the drain terminal (24) and the source terminal (26).

[0097] The first conductive bus (35), the gate electrode (30) and the gate terminal (28) may all be electrically connected to each other in a direct manner.

[0098] The active elements (22) may be HEMT type transistors electrically connected in parallel to each other and formed using gallium nitride technology.

[0099] A method for manufacturing a heterojunction power device can be summarized as comprising: forming a first active region (20a) and a second active region (20b) symmetrically opposite to each other with respect to a symmetry axis (H) on a substrate (21) comprising a semiconductor material, the first active region (20a) and the second active region (20b) accommodating corresponding heterostructures (25, 27, 29) and separated by a separation region (23) extending along the symmetry axis (H); forming a first conductive bus (35) on the separation region (23), the first conductive bus (35) being configured to connect a first potential (V G ) are distributed in parallel to the first active area and the second active area (20a, 20b); and a second conductive bus (55) is formed on the separation area (23), the second conductive bus (55) being configured to connect the power device (1) to a potential different from the first potential (V G )'s second potential (V S ) are distributed in parallel to the first active area and the second active area (20a, 20b), wherein the first conductive bus and the second conductive bus (35, 55) extend along the symmetry axis (H), and the second conductive bus (55) is superimposed on the first conductive bus (35).

[0100] The manufacturing method may include: forming a first metallization level (M1); and forming from the first metallization level (M1): a first conductive bus (35); first level drain and source electrodes (40a, 40b, 50a, 50b) extending transversely to the first conductive bus (35) and configured to provide a drain potential and a source potential of the power device (1) to the first active area (20a) and the second active area (20b), respectively; forming a second metallization level (M2) above the first metallization level (M1); And from the second metallization level (M2) are formed: a second conductive bus (55); a second layer of source electrodes (70a, 70b), which extend from the second conductive bus (55) in an opposite direction relative to the symmetry axis (H) and extend transversely to the second conductive bus (55), and are electrically connected to the first layer of source electrodes (50a, 50b); and a second layer of drain electrodes (60a, 60b), which extend transversely to the second conductive bus (55) and are electrically connected to the first layer of drain electrodes (40a, 40b).

[0101] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A heterojunction power device, characterized in that: include: a substrate comprising a semiconductor material; A first active region and a second active region, wherein the first active region and the second active region are symmetrically arranged on the substrate relative to a symmetry axis and accommodate corresponding heterostructures; a separation region extending along the symmetry axis between the first active region and the second active region; a first conductive bus configured to distribute a first potential of the heterojunction power device to the first active region and the second active region in parallel; as well as a second conductive bus configured to distribute a second potential of the heterojunction power device, which is different from the first potential, to the first active region and the second active region in parallel, The first conductive bus and the second conductive bus extend above the separation area along the symmetry axis, and the second conductive bus is stacked on the first conductive bus.

2. The heterojunction power device according to claim 1, characterized in that: The first conductive bus is a gate bus, and the first potential is a control signal of the heterojunction power device.

3. The heterojunction power device according to claim 1, characterized in that: The second conductive bus is a source bus, and the second potential is a source potential of the heterojunction power device.

4. The heterojunction power device according to claim 1, characterized in that: Also included is a first metallization level, wherein the first conductive bus is a part of the first metallization level; The first metallization level also includes: a first level drain electrode and a first level source electrode associated with the first active region, extending transversely to the first conductive bus and superimposed on the first active region; as well as A first-level drain electrode and a first-level source electrode associated with the second active region extend transversely to the first conductive bus, overlie the second active region, and are separated from the first-level drain electrode and the first-level source electrode associated with the first active region at the separation region.

5. The heterojunction power device according to claim 4, characterized in that: the first level drain electrode and the first level source electrode associated with the first active region are arranged in a symmetrical manner with respect to the axis of symmetry to the corresponding first level drain electrode and first level source electrode associated with the second active region; And wherein in the first active area and in the second active area, the first-level drain electrodes are arranged alternately with the first-level source electrodes along the symmetry axis.

6. The heterojunction power device according to claim 5, characterized in that: Also comprising a second metallization level overlying the first metallization level, wherein the second conductive bus is a part of the second metallization level; The second metallization level further comprises: a second level drain electrode and a second level source electrode associated with the first active region, extending transversely to the second conductive bus and superimposed on the first active region; a second level drain electrode and a second level source electrode associated with the second active region, extending transversely to the second conductive bus and superimposing on the second active region; The second level source electrode extends from the second conductive bus in an opposite direction relative to the axis of symmetry; and The second-level drain electrode associated with the first active region is separated from the second-level drain electrode associated with the second active region at the separation region.

7. The heterojunction power device according to claim 6, characterized in that: the second-level drain electrode and the second-level source electrode associated with the first active region are arranged in a symmetrical manner to the second-level drain electrode and the second-level source electrode associated with the second active region with respect to the symmetry axis; as well as The second-level drain electrodes are arranged alternately with the second-level source electrodes along the symmetry axis.

8. The heterojunction power device according to claim 7, characterized in that: Also included is a third metallization level superimposed on the second metallization level, the third metallization level being provided with: a drain metallization region superimposed on the first active region; a source metallization region superimposed on the second active region; A third level drain electrode and a third level source electrode, extending transversely to the symmetry axis from the drain metallization region and the source metallization region, respectively; as well as The third-level drain electrodes are arranged alternately with the third-level source electrodes along the symmetry axis.

9. The heterojunction power device according to claim 8, characterized in that: Also included are second-level conductive vias between the first metallization level and the second metallization level and third-level conductive vias between the second metallization level and the third metallization level.

10. The heterojunction power device according to claim 8, characterized in that: The first active region and the second active region each include: defining a respective channel layer and a respective barrier layer of a respective heterojunction; a plurality of corresponding active elements extending transversely to the axis of symmetry and arranged periodically along the axis of symmetry, wherein the active elements include a corresponding portion of the channel layer and a corresponding portion of the barrier layer and a corresponding gate region, the gate region being contactingly superimposed on the barrier layer of the corresponding active region; the active elements each further include a drain terminal, a source terminal and a gate terminal; and The gate terminal comprises a gate electrode which is superposed in contact with the respective gate region and extends transversely to the symmetry axis.

11. The heterojunction power device according to claim 10, characterized in that: The third level drain electrode, the second level drain electrode, the first level drain electrode and the drain terminal of the active element are superimposed on each other and are all electrically connected to each other in a direct manner; The third level source electrode, the second level source electrode, the second conductive bus, the first level source electrode and the source terminal of the active element are superimposed on each other and are all electrically connected to each other in a direct manner; as well as The first level drain electrode and the first level source electrode have respective contact portions extending transversely to the axis of symmetry and forming the drain terminal and the source terminal.

12. The heterojunction power device according to claim 10, characterized in that: The first conductive bus, the gate electrode, and the gate terminal are all electrically connected to each other in a direct manner.

13. The heterojunction power device according to claim 10, characterized in that: The active elements are high electron mobility transistor type transistors electrically connected in parallel to each other and formed using gallium nitride technology.

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