Display panel and display device

Abstract

Embodiments of the present disclosure provide a display panel and a display device, and relate to the technical field of display, and are used for improving the display effect of the display panel. The display panel comprises a substrate and a plurality of sub-pixels. The sub-pixel comprises a pixel circuit, and the pixel circuit comprises a driving sub-circuit, a coupling sub-circuit, a data writing sub-circuit and a first control sub-circuit. The coupling sub-circuit is connected with the driving sub-circuit. The data writing sub-circuit is connected with the coupling sub-circuit. The first control sub-circuit is connected with a first control signal line, a first reference voltage signal line and the coupling sub-circuit respectively. Wherein, the plurality of sub-pixels comprise a first color sub-pixel and a second color sub-pixel, the first reference voltage signal line comprises a first sub-signal line and a second sub-signal line, the first sub-signal line is connected with the first control sub-circuit of the pixel circuit in the first color sub-pixel, and the second sub-signal line is connected with the first control sub-circuit of the pixel circuit in the second color sub-pixel. The display panel is used for displaying an image.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diode (OLED) display panels are widely used in display devices such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, and high contrast. Utility Model Content

[0003] The purpose of the embodiments of this disclosure is to provide a display panel and a display device for improving the display effect of the display panel and reducing the power consumption of the display panel.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: On one hand, a display panel is provided. The display panel includes a substrate and a plurality of sub-pixels. The sub-pixels are located on one side of the substrate along a direction perpendicular to the substrate. Each sub-pixel includes a pixel circuit, which includes a driving sub-circuit, a coupling sub-circuit, a data writing sub-circuit, and a first control sub-circuit. The driving sub-circuit is connected to a first voltage signal line and a second voltage signal line, respectively. The coupling sub-circuit is connected to the driving sub-circuit. The data writing sub-circuit is connected to a first scan signal line, a data signal line, and the coupling sub-circuit, respectively. The first control sub-circuit is connected to a first control signal line, a first reference voltage signal line, and the coupling sub-circuit, respectively.

[0005] The plurality of sub-pixels include a first color sub-pixel and a second color sub-pixel. The first reference voltage signal line includes a first sub-signal line and a second sub-signal line. The first sub-signal line is connected to the first control sub-circuit of the pixel circuit in the first color sub-pixel, and the second sub-signal line is connected to the first control sub-circuit of the pixel circuit in the second color sub-pixel.

[0006] In the aforementioned display panel, the first reference voltage signal line includes a first sub-signal line and a second sub-signal line. The first sub-signal line is connected to the first control sub-circuit of the pixel circuit within the first color sub-pixel, and the second sub-signal line is connected to the first control sub-circuit of the pixel circuit within the second color sub-pixel. On one hand, the connection between the first color sub-pixel and the first sub-signal line within the first reference voltage signal line, and the connection between the second color sub-pixel and the second sub-signal line within the first reference voltage signal line, enables independent driving of the first color sub-pixel and the second color sub-pixel. This is beneficial for improving the driving capability of the first reference voltage signal line and for improving the stability of the first reference voltage signal transmitted within the first reference voltage signal line. Consequently, it helps to reduce the probability of flickering in the displayed image due to voltage fluctuations in the first reference voltage signal, thereby improving the display effect of the display panel.

[0007] On the other hand, when the pixel circuit includes a driving sub-circuit, and the driving sub-circuit includes a third transistor, the saturation current of the third transistor is I = 1 / 2 * μ * Cox * W / L * (Vref1 - Vdata)^2, where μ represents the carrier mobility in the third transistor, Cox represents the capacitance per unit area of ​​the oxide layer, W / L represents the ratio of the width to the length of the channel region in the third transistor, and (Vref1 - Vdata) represents the difference between the voltage of the first reference voltage signal transmitted in the first reference voltage signal line and the voltage of the data signal transmitted in the data signal line.

[0008] As can be seen from the above formula, the saturation current of the third transistor is related to (Vref1-Vdata). Since the first color sub-pixel is connected to the first sub-signal line in the first reference voltage signal line, and the second color sub-pixel is connected to the second sub-signal line in the first reference voltage signal line, the voltage of the first sub-signal transmitted in the first sub-signal line and the voltage of the second sub-signal transmitted in the second sub-signal line can be adjusted respectively. This reduces or approaches the difference between the voltage of the data signal transmitted in the data signal line connected to the first color sub-pixel and the voltage of the data signal transmitted in the data signal line connected to the second color sub-pixel. This reduces the effective driving voltage range of the source driver chip, thereby reducing the power consumption of the source driver chip and thus helping to reduce the driving power consumption of the display panel.

[0009] When the effective driving voltage range of the source driver chip is reduced, the difference between the high-level voltage and the low-level voltage of the first scan signal transmitted in the first scan signal line can also be reduced, which is beneficial to further reduce the driving power consumption of the display panel.

[0010] On the other hand, when the display panel is in a high-brightness mode or an average image level high-brightness mode, the voltage of the first sub-signal transmitted in the first sub-signal line can be adjusted to increase the current of the third transistor in the pixel circuit of the first color sub-pixel. Similarly, the voltage of the second sub-signal transmitted in the second sub-signal line can be adjusted to increase the current of the third transistor in the pixel circuit of the second color sub-pixel. This reduces the probability of insufficient driving current of the third transistor, thereby helping the display panel to achieve high-brightness display.

[0011] On the other hand, when the display panel is in low-frequency display mode, the brightness of the light-emitting device in the first color sub-pixel can be adjusted and compensated in real time by dynamically adjusting the voltage of the first sub-signal transmitted in the first sub-signal line. This helps to reduce the probability of uneven brightness of the light-emitting device in the first color sub-pixel during the write frame and hold frame due to transistor leakage and source retrace hysteresis. As a result, the brightness of the light-emitting device in the first color sub-pixel can be kept uniform and stable during the write frame and hold frame, which helps to reduce the probability of flickering in the image displayed by the display panel and further improves the display effect of the display panel.

[0012] When the display panel is in low-frequency display mode, the brightness of the light-emitting device in the second color sub-pixel can be dynamically adjusted and compensated in real time by dynamically adjusting the voltage of the second sub-signal transmitted in the second sub-signal line. This helps to reduce the probability of uneven brightness of the light-emitting device in the second color sub-pixel during the write frame and hold frame due to transistor leakage and source retrace hysteresis. As a result, the brightness of the light-emitting device in the second color sub-pixel can be kept uniform and stable during the write frame and hold frame, which helps to further reduce the probability of flickering in the image displayed by the display panel and further improve the display effect of the display panel.

[0013] In some embodiments, the first sub-signal line and the second sub-signal line are parallel to the substrate, and the first sub-signal line is substantially parallel to the second sub-signal line.

[0014] In some embodiments, the display panel further includes a first conductive layer and a second conductive layer. Along a direction perpendicular to the substrate, the first conductive layer is located on one side of the substrate and includes a first sub-signal line. The second conductive layer is located on the side of the first conductive layer away from the substrate and includes a second sub-signal line. The orthographic projection of the first sub-signal line onto the substrate overlaps with the orthographic projection of the second sub-signal line onto the substrate.

[0015] In some embodiments, the first control sub-circuit includes a first transistor, the first transistor including a first active pattern. The first active pattern is connected to a first reference voltage signal line.

[0016] The orthographic projection of the first active pattern onto the substrate overlaps with the orthographic projection of the first sub-signal line onto the substrate. And / or, the orthographic projection of the first active pattern onto the substrate overlaps with the orthographic projection of the second sub-signal line onto the substrate.

[0017] In some embodiments, the plurality of sub-pixels further includes a third color sub-pixel. The first reference voltage signal line also includes a third sub-signal line, which is connected to a first control sub-circuit of the pixel circuit within the third color sub-pixel.

[0018] In some embodiments, the first sub-signal line, the second sub-signal line, and the third sub-signal line are parallel to the substrate, and the first sub-signal line is substantially parallel to the second sub-signal line and the third sub-signal line.

[0019] In some embodiments, the display panel further includes a first conductive layer, a second conductive layer, and a third conductive layer. Along a direction perpendicular to the substrate, the first conductive layer is located on one side of the substrate and includes a first sub-signal line. The second conductive layer is located on the side of the first conductive layer away from the substrate and includes a second sub-signal line. The third conductive layer is located on the side of the second conductive layer away from the first conductive layer and includes a third sub-signal line. The orthographic projection of the third sub-signal line onto the substrate is located on the same side as the orthographic projection of the first sub-signal line onto the substrate.

[0020] In some embodiments, the first control sub-circuit includes a first transistor, the first transistor including a first active pattern. The first active pattern is connected to a first reference voltage signal line. The orthographic projection of the first active pattern onto the substrate overlaps with the orthographic projection of the third sub-signal line onto the substrate.

[0021] In some embodiments, the orthographic projection of the first sub-signal line onto the substrate and the orthographic projection of the first active pattern onto the substrate overlap.

[0022] The display panel also includes a first connecting portion, through which a third sub-signal line is connected to a first active pattern. The orthographic projection of the first connecting portion onto the substrate overlaps with the orthographic projection of the first sub-signal line onto the substrate.

[0023] In some embodiments, the first reference voltage signal line further includes a fourth sub-signal line and a fifth sub-signal line. The fourth sub-signal line is connected to the first sub-signal line, and the orthographic projection of the fourth sub-signal line onto the substrate intersects with the orthographic projection of the first sub-signal line onto the substrate. The fifth sub-signal line is connected to the second sub-signal line, and the orthographic projection of the fifth sub-signal line onto the substrate intersects with the orthographic projection of the second sub-signal line onto the substrate.

[0024] In some embodiments, the fourth sub-signal line and the fifth sub-signal line are disposed on the same layer. The fourth sub-signal line is substantially parallel to the fifth sub-signal line.

[0025] In some embodiments, the fourth sub-signal line and the fifth sub-signal line are arranged alternately. The display panel includes a plurality of pixel circuits arranged along the extension direction of the first sub-signal line. The plurality of pixel circuits include a plurality of pixel circuit groups, and the pixel circuit groups include pixel circuits within a first color sub-pixel and pixel circuits within a second color sub-pixel. In orthographic projection onto the substrate, the fourth sub-signal line is located between two adjacent pixel circuits, the fifth sub-signal line is located between two adjacent pixel circuits, and the pixel circuit groups are located between adjacent fourth and fifth sub-signal lines.

[0026] In some embodiments, the first reference voltage signal line further includes a sixth sub-signal line, which is connected to the third sub-signal line. The orthographic projection of the sixth sub-signal line onto the substrate intersects with the orthographic projection of the third sub-signal line onto the substrate.

[0027] In some embodiments, the display panel further includes a fourth sub-signal line and a fifth sub-signal line. The fourth, fifth, and sixth sub-signal lines are disposed on the same layer, and the fourth sub-signal line is substantially parallel to the fifth and sixth sub-signal lines.

[0028] In some embodiments, the display panel further includes a fourth sub-signal line and a fifth sub-signal line, the fourth sub-signal line being substantially parallel to the fifth and sixth sub-signal lines. The display panel includes a plurality of pixel circuits arranged along the extension direction of the first sub-signal line. The plurality of pixel circuits includes a plurality of pixel circuit groups, each pixel circuit group including pixel circuits within a first color sub-pixel, pixel circuits within a second color sub-pixel, and pixel circuits within a third color sub-pixel. In orthographic projection onto the substrate, the sixth sub-signal line is located between two adjacent pixel circuits, and the pixel circuit group is located between adjacent fourth and sixth sub-signal lines, and between adjacent sixth and fifth sub-signal lines.

[0029] On the other hand, a display device is provided. The display device includes a display panel and a driver chip as described in any of the above embodiments. The driver chip is connected to the display panel.

[0030] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0032] Figure 1 This is a plan view of a display device according to some embodiments; Figure 2 A plan view of a display panel according to some embodiments; Figure 3 Structure of light-emitting devices within sub-pixels according to some embodiments Figure 1 ; Figure 4 Structure of light-emitting devices within sub-pixels according to some embodiments Figure 2 ; Figure 5 A plan view of the pixel circuitry within a sub-pixel according to some embodiments; Figure 6 Equivalent circuit of pixel circuit within a sub-pixel according to some embodiments Figure 1 ; Figure 7 Equivalent circuit of pixel circuit within a sub-pixel according to some embodiments Figure 2 ; Figure 8 This is a plan view of a partial region of the first active layer within the pixel driving layer of a display panel according to some embodiments; Figure 9 This is a plan view of a partial region of the fifth conductive layer within the pixel driving layer of a display panel according to some embodiments; Figure 10 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first active layer and a fifth conductive layer within a pixel driving layer; Figure 11 Driving timing of pixel circuits within sub-pixels according to some embodiments Figure 1 ; Figure 12 for Figure 7 The state diagram of the pixel circuit in the first reset phase and the second reset phase is shown below. Figure 13 for Figure 7 The diagram shows the state of the pixel circuit during the threshold compensation stage. Figure 14 for Figure 7The diagram shows the state of the pixel circuit during the data writing phase. Figure 15 for Figure 7 The diagram shows the state of the pixel circuit during the light-emitting stage. Figure 16 Driving timing of pixel circuits within sub-pixels according to some embodiments Figure 2 ; Figure 17 Equivalent circuit of pixel circuit within a sub-pixel according to some embodiments Figure 3 ; Figure 18 Equivalent circuit of pixel circuit within a sub-pixel according to some embodiments Figure 4 ; Figure 19 This is a plan view of a partial region of the first conductive layer within the pixel driving layer of a display panel according to some embodiments; Figure 20 This is a plan view of a partial region of the second conductive layer within the pixel driving layer of a display panel according to some embodiments; Figure 21 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first conductive layer and a second conductive layer within a pixel driving layer; Figure 22 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first active layer, a first conductive layer, and a second conductive layer within a pixel driving layer; Figure 23 Equivalent circuit of pixel circuit within a sub-pixel according to some embodiments Figure 5 ; Figure 24 This is a plan view of a partial region of the third conductive layer within the pixel driving layer of a display panel according to some embodiments; Figure 25 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first conductive layer and a third conductive layer within a pixel driving layer; Figure 26 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a second conductive layer and a third conductive layer within a pixel driving layer; Figure 27 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first active layer and a third conductive layer within a pixel driving layer; Figure 28 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first active layer, a first conductive layer, and a third conductive layer within a pixel driving layer; Figure 29A plan view of partial regions of the first conductive layer and the fourth conductive layer within the pixel driving layer of a display panel according to some embodiments; Figure 30 This is a plan view of a substrate within a display panel according to some embodiments, and a partial region of a first active layer, a fifth conductive layer, and a fourth conductive layer within a pixel driving layer; Figure 31 This is a plan view of a partial region of the second and fourth conductive layers within the pixel driving layer of a display panel according to some embodiments; Figure 32 This is a plan view of a partial region of the fourth conductive layer within the pixel driving layer of a display panel according to some embodiments; Figure 33 This is a plan view of a partial region of the third and fourth conductive layers within the pixel driving layer of a display panel according to some embodiments; Figure 34 This is a cross-sectional view of a partial area of ​​a display panel according to some embodiments; Figure 35 This is a plan view of a partial region of the first electrode layer and the pixel definition layer within the light-emitting device layer according to some embodiments; Figure 36 This is a plan view of a local region of the pixel driving layer according to some embodiments; Figure 37 This is a plan view of a partial region of the light-shielding layer within the pixel driving layer according to some embodiments; Figure 38 This is a plan view of a substrate according to some embodiments, and a partial region of a light-shielding layer and a first active layer within a pixel driving layer. Detailed Implementation

[0033] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0034] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0035] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0036] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0037] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0038] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0039] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0040] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0041] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0042] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0043] For ease of description below, an XYZ coordinate system is established. The first direction Z is perpendicular to the substrate, and the second direction X and the third direction Y are parallel to the substrate (i.e., both the second direction X and the third direction Y are perpendicular to the first direction Z), and the second direction X and the third direction Y intersect. For example, the second direction X can be perpendicular to the third direction Y.

[0044] It should be noted that, for example, 2 (100) in the accompanying drawings of this disclosure indicates that component 2 belongs to component 100, and other similar reference numerals in the drawings also follow the above description.

[0045] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000.

[0046] Exemplarily, the display device 1000 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, Global Positioning System (GPS) receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 The following is an illustration using a mobile phone as an example of a display device 1000.

[0047] For example, the display device 1000 may be an electroluminescent display device or a photoluminescent display device.

[0048] When the display device 1000 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device.

[0049] When the display device 1000 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0050] The following describes some embodiments of this disclosure using an organic light-emitting diode display device or a quantum dot light-emitting diode display device as examples.

[0051] In some embodiments, please continue reading Figure 1 The display device 1000 may include a display panel 100 and a driver chip (not shown in the figure). The driver chip is connected to the display panel 100 and can be configured to drive the display panel 100 to display images.

[0052] It should be noted that, from the perspective of connection medium and signal transmission principle, the above-mentioned "connection" can be electrical connection, etc.

[0053] For example, the connection between the driver chip and the display panel 100 can be an electrical connection.

[0054] When the connection between the driver chip and the display panel 100 is an electrical connection, an electrical path can be established between the driver chip and the display panel 100 through a conductive material, so that electrical signals can be effectively transmitted between the driver chip and the display panel 100.

[0055] From the perspective of the connection path, the above "connection" can be a direct connection or an indirect connection, etc.

[0056] For example, the connection between the driver chip and the display panel 100 can be a direct connection.

[0057] When the connection between the driver chip and the display panel 100 is a direct connection, the driver chip and the display panel 100 can communicate directly through a dedicated channel to achieve fast data signal transmission.

[0058] For example, the connection between the driver chip and the display panel 100 can be an indirect connection.

[0059] When the connection between the driver chip and the display panel 100 is indirect, the driver chip and the display panel 100 can transfer data signals through an intermediate component to enhance the flexibility of the display device 1000.

[0060] The following description of "connection" will follow this explanation and will not be repeated.

[0061] For example, the driver chip within the display device 1000 may include a source driver IC or the like.

[0062] For example, the driver chip in the display device 1000 can be encapsulated by means of chip on film (COF), chip on glass (COG), or chip on flexible material (COP) and bonded to the display panel 100.

[0063] For example, when the display device 1000 is an organic light-emitting diode (OLED) display device, the display panel 100 within the display device 1000 can be an OLED display panel.

[0064] When the display device 1000 is a quantum dot light-emitting diode display device, the display panel 100 within the display device 1000 can be a quantum dot light-emitting diode display panel.

[0065] The structure of the above-mentioned display panel 100 will be described in detail below.

[0066] In some embodiments, such as Figure 2 As shown, Figure 2 This is a plan view of a display panel 100 according to some embodiments. The display panel 100 may be a rectangular structure.

[0067] It should be noted that the aforementioned "rectangular structure" refers to the fact that the overall shape of the boundary of the display panel 100 is rectangular, but it is not limited to a standard rectangle. That is, "rectangle" here includes not only the shape of a standard rectangle, but also, considering manufacturing conditions, shapes similar to rectangles. For example, please refer to [further details omitted]. Figure 2 The long and short sides of the rectangle can be curved at each intersection (i.e., at the corner G), that is, the corner G is smooth, so that the boundary of the display panel 100 is a rounded rectangle in the plan view.

[0068] In other embodiments, the display panel 100 may be a circular structure or other shapes with corners.

[0069] The following uses a rectangular structure for the display panel 100 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the shape of the display panel 100 can also be any other shape.

[0070] In some embodiments, please continue reading Figure 2 The display panel 100 has a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0071] For example, the peripheral area AN can be located on one side of the display area AA.

[0072] Alternatively, the peripheral area AN can be located on opposite sides of the display area AA.

[0073] Alternatively, please continue reading Figure 2 The surrounding area AN can surround the display area AA.

[0074] For example, please continue reading Figure 2 The peripheral area AN of the display panel 100 may be equipped with a gate driver on array (GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.). However, the functions of the peripheral area AN of the display panel 100 include, but are not limited to, these.

[0075] In some embodiments, please continue reading Figure 2 The display panel 100 may include a substrate 1.

[0076] For example, substrate 1 can be a rigid substrate.

[0077] For example, the material of substrate 1 may include one of glass and polymethyl methacrylate (PMMA).

[0078] For example, the material of substrate 1 may include multiple materials (two or more) such as glass and polymethyl methacrylate.

[0079] Alternatively, substrate 1 can be a flexible substrate.

[0080] For example, the material of substrate 1 may include one of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide (PI).

[0081] For example, the material of substrate 1 may include a variety of materials such as polyethylene terephthalate, polyethylene thiocyanate, and polyimide.

[0082] In some embodiments, please continue reading Figure 2 The display panel 100 may include multiple sub-pixels S.

[0083] For example, please continue reading Figure 2 In the case where the display panel 100 includes a substrate 1, the sub-pixel S can be located on one side of the substrate 1 along a direction perpendicular to the substrate 1 (i.e., the first direction Z).

[0084] For example, please continue reading Figure 2 When the display panel 100 has a display area AA, multiple sub-pixels S can be located within the display area AA of the display panel 100. Each sub-pixel S is the smallest light-emitting unit within the display area AA.

[0085] For example, please continue reading Figure 2 Multiple sub-pixels S within the display panel 100 can be arranged in an array.

[0086] For example, please continue reading Figure 2 Multiple sub-pixels S can be arranged at intervals along the second direction X and the third direction Y, respectively. The second direction X and the third direction Y are both perpendicular to the first direction Z, and the second direction X and the third direction Y intersect.

[0087] For example, please continue reading Figure 2 The multiple sub-pixels S within the display panel 100 may include a first color sub-pixel S1. For example, the first color sub-pixel S1 may be a red sub-pixel that emits red light.

[0088] For example, please continue reading Figure 2 The multiple sub-pixels S within the display panel 100 may include a second color sub-pixel S2. For example, the second color sub-pixel S2 may be a blue sub-pixel that emits blue light.

[0089] For example, please continue reading Figure 2 The multiple sub-pixels S within the display panel 100 may include a third color sub-pixel S3. For example, the third color sub-pixel S3 may be a green sub-pixel that emits green light.

[0090] In some embodiments, please continue reading Figure 2 In the case where the display panel 100 includes sub-pixels S, the sub-pixels S may include light-emitting devices 30.

[0091] For example, such as Figure 3 and Figure 4 As shown, Figure 3 and Figure 4 These are all structural diagrams of the light-emitting device 30 within a sub-pixel S according to some embodiments. The light-emitting device 30 may include a first electrode 311.

[0092] For example, the material of the first electrode 311 within the light-emitting device 30 may include a metallic material. Specifically, the material of the first electrode 311 may include one or more (two or more) of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0093] The material of the first electrode 311 within the light-emitting device 30 may also include an alloy material. Specifically, the material of the first electrode 311 may include one or more of aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb).

[0094] The material of the first electrode 311 within the light-emitting device 30 may also include a transparent conductive material. Specifically, the material of the first electrode 311 may include one or more of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0095] For example, the first electrode 311 within the light-emitting device 30 can be a single-layer structure. Alternatively, the first electrode 311 within the light-emitting device 30 can be a multi-layer composite structure.

[0096] When the first electrode 311 in the light-emitting device 30 is a multilayer composite structure, the first electrode 311 can be a titanium / aluminum / titanium (Ti / Al / Ti) structure, an indium tin oxide / silver / indium tin oxide (ITO / Ag / ITO) structure, or a molybdenum / aluminum-neodymium alloy / indium tin oxide (Mo / AlNd / ITO) structure, etc.

[0097] For example, please continue reading Figure 3 and Figure 4 The light-emitting device 30 may include a light-emitting part 331.

[0098] The light-emitting part 331 may include a light-emitting layer 3311.

[0099] For example, please continue reading Figure 3 When the display panel 100 is an organic light-emitting diode (OLED) display panel, the light-emitting layer 3311 within the light-emitting part 331 may include an electroluminescent material layer (EML). The electroluminescent material layer may include a host material and a guest material, and the guest material may be a fluorescent dopant or a phosphorescent dopant, etc.

[0100] For example, please continue reading Figure 4 In the case where the display panel 100 is a quantum dot electroluminescent diode display panel, the light-emitting layer 3311 within the light-emitting part 331 may include a quantum dot layer (QDL). The quantum dot layer may include quantum dot particles, which may be interconnected by surface modification groups.

[0101] Please continue reading. Figure 3 and Figure 4 The light-emitting part 331 may also include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0102] For example, please continue reading Figure 3 and Figure 4 The light-emitting device 30 may include a second electrode 321.

[0103] For example, the material of the second electrode 321 within the light-emitting device 30 may include a metallic material. Specifically, the material of the second electrode 321 may include one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0104] The material of the second electrode 321 within the light-emitting device 30 may also include an alloy material. Specifically, the material of the second electrode 321 may include one or more of aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb).

[0105] The material of the second electrode 321 within the light-emitting device 30 may also include a transparent conductive material. Specifically, the material of the second electrode 321 may include one or more of indium tin oxide (ITO) and indium zinc oxide (IZO).

[0106] For example, please continue reading Figure 3 and Figure 4 When the light-emitting device 30 includes a first electrode 311, a light-emitting part 331, and a second electrode 321, the first electrode 311, the light-emitting part 331, and the second electrode 321 can be stacked sequentially along the first direction Z. The first electrode 311 and the second electrode 321 can provide charge carriers such as electrons and holes to the light-emitting part 331 so that the light-emitting part 331 emits light.

[0107] Please continue reading. Figure 3 and Figure 4 One of the first electrode 311 and the second electrode 321 can be used as the anode of the light-emitting device 30, and the other can be used as the cathode of the light-emitting device 30.

[0108] For example, please continue reading Figure 3 and Figure 4 The first electrode 311 can be used as the anode of the light-emitting device 30, and the second electrode 321 can be used as the cathode of the light-emitting device 30.

[0109] When the first electrode 311 serves as the anode of the light-emitting device 30 and the second electrode 321 serves as the cathode of the light-emitting device 30, when a voltage is applied between the first electrode 311 and the second electrode 321, holes injected from the first electrode 311 can be transported to the light-emitting portion 331 within the light-emitting device 30, and electrons injected from the second electrode 321 can also be transported to the light-emitting portion 331 within the light-emitting device 30. Electrons and holes, as charge carriers, recombine in the light-emitting portion 331 to generate excitons. When the excitons transition from the excited state to the ground state, they emit light, thereby causing the light-emitting portion 331 to emit light, and thus causing the light-emitting device 30 to emit light.

[0110] In some embodiments, please continue reading Figure 2 In the case where the display panel 100 includes sub-pixels S and sub-pixels S include light-emitting devices 30, sub-pixels S may also include pixel circuits 20, which are connected to the light-emitting devices 30.

[0111] In the aforementioned display panel 100, the pixel circuit 20 is connected to the light-emitting device 30. The pixel circuit 20 can generate a driving signal (e.g., a driving current), and the light-emitting device 30 can emit light under the driving action of the driving signal generated by the pixel circuit 20.

[0112] For example, please continue reading Figure 2 The pixel circuit 20 and the light-emitting device 30 can have a one-to-one driving relationship. That is, one light-emitting device 30 can be connected to a corresponding pixel circuit 20.

[0113] Alternatively, the pixel circuit 20 and the light-emitting device 30 can have a one-to-many driving relationship. That is, one pixel circuit 20 can be connected to multiple light-emitting devices 30 and configured to drive multiple light-emitting devices 30 to emit light.

[0114] For example, such as Figure 5 As shown, Figure 5 This is a plan view of a pixel circuit 20 within a sub-pixel S according to some embodiments. The display panel 100 may include a plurality of pixel circuits 20. The plurality of pixel circuits 20 may be arranged along a second direction X.

[0115] Please continue reading. Figure 5 The multiple pixel circuits 20 within the display panel 100 may include multiple pixel circuit groups 20a. Each pixel circuit group 20a includes at least one pixel circuit 20.

[0116] For example, please continue reading Figure 5 In the case where multiple sub-pixels S in the display panel 100 include a first color sub-pixel S1, the pixel circuit group 20a may include the pixel circuit 20 in the first color sub-pixel S1.

[0117] In the case where multiple sub-pixels S in the display panel 100 include a second color sub-pixel S2, the pixel circuit group 20a may include the pixel circuit 20 in the second color sub-pixel S2.

[0118] In the case where the plurality of sub-pixels S in the display panel 100 include a third color sub-pixel S3, the pixel circuit group 20a may include the pixel circuit 20 in the third color sub-pixel S3.

[0119] In some embodiments, such as Figure 6 As shown, Figure 6This is an equivalent circuit diagram of the pixel circuit 20 within a sub-pixel S according to some embodiments. When the display panel 100 includes a sub-pixel S and the sub-pixel S includes a pixel circuit 20, the pixel circuit 20 may include a driving sub-circuit 201, a coupling sub-circuit 202, a data writing sub-circuit 203, and a first control sub-circuit 204.

[0120] The driving sub-circuit 201 can be connected to the first voltage signal line V1 and the second voltage signal line V2, respectively. The coupling sub-circuit 202 can be connected to the driving sub-circuit 201. The data writing sub-circuit 203 can be connected to the first scan signal line Gate, the data signal line Data, and the coupling sub-circuit 202, respectively. The first control sub-circuit 204 can be connected to the first control signal line EM1, the first reference voltage signal line Vref1, and the coupling sub-circuit 202, respectively.

[0121] For example, such as Figure 7 As shown, Figure 7 This is an equivalent circuit diagram of pixel circuit 20 within sub-pixel S according to some embodiments. The driving sub-circuit 201 within pixel circuit 20 may include a third transistor T3.

[0122] Please continue reading. Figure 7 The third transistor T3 may include a control electrode, a first electrode, and a second electrode. The common terminal of the driving sub-circuit 201 and the coupling sub-circuit 202 is the first node N1. The control electrode of the third transistor T3 can be connected to the first node N1, the first electrode of the third transistor T3 can be connected to the first voltage signal line V1, and the second electrode of the third transistor T3 can be connected to the second voltage signal line V2.

[0123] For example, the control electrode of the third transistor T3 can be the gate, the first electrode of the third transistor T3 can be the source, and the second electrode of the third transistor T3 can be the drain. Alternatively, the control electrode of the third transistor T3 can be the gate, the first electrode of the third transistor T3 can be the drain, and the second electrode of the third transistor T3 can be the source.

[0124] It should be noted that the first node N1 mentioned above does not represent an actual existing component, but rather the junction point of related connections in the equivalent circuit diagram of the pixel circuit 20. In other words, the first node N1 is a node equivalent to the junction point of related connections in the equivalent circuit diagram of the pixel circuit 20.

[0125] For example, such as Figure 8 , Figure 9 and Figure 10 As shown, and in combination Figure 7 , Figure 8 This is a plan view of a partial region of the first active layer 26 within the pixel driving layer 2 of the display panel 100 according to some embodiments. Figure 9This is a plan view of a partial region of the fifth conductive layer 25 within the pixel driving layer 2 of the display panel 100 according to some embodiments. Figure 10 This is a plan view of a portion of the substrate 1 within the display panel 100 according to some embodiments, and of the first active layer 26 and the fifth conductive layer 25 within the pixel driving layer 2. When the driving sub-circuit 201 includes a third transistor T3, the third transistor T3 may include a third active pattern T31 and a third gate T32. The orthographic projection of the third active pattern T31 within the third transistor T3 onto the substrate 1 and the orthographic projection of the third gate T32 within the third transistor T3 onto the substrate 1 overlap.

[0126] The third active pattern T31 within the third transistor T3 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0127] The aforementioned "the orthographic projection of the third active pattern T31 in the third transistor T3 onto the substrate 1 and the orthographic projection of the third gate T32 in the third transistor T3 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the third active pattern T31 onto the substrate 1 and the orthographic projection of the third gate T32 onto the substrate 1 overlap.

[0128] For example, please continue reading Figure 7 In the case where the driving sub-circuit 201 includes a third transistor T3, the third transistor T3 can be a P-type transistor or an N-type transistor.

[0129] The turn-on voltage of a P-type transistor can be a low-level voltage (e.g., the turn-on voltage of a P-type transistor can be 0V, -5V, or -10V, etc.), and the turn-off voltage of a P-type transistor can be a high-level voltage (e.g., the turn-off voltage of a P-type transistor can be 5V or 10V, etc.).

[0130] The turn-on voltage of an N-type transistor can be a high-level voltage (e.g., the turn-on voltage of an N-type transistor can be 5V or 10V, etc.), and the turn-off voltage of an N-type transistor can be a low-level voltage (e.g., the turn-off voltage of an N-type transistor can be 0V, -5V, or -10V, etc.).

[0131] The following uses a P-type transistor as an example of the third transistor T3 in the driver sub-circuit 201 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the third transistor T3 can also be other suitable types of transistors.

[0132] For example, when the driving sub-circuit 201 includes a third transistor T3, the third transistor T3 can be a low-temperature poly-silicon thin film transistor (LTPS-TFT). Low-temperature poly-silicon thin film transistors have advantages such as high mobility and fast charging.

[0133] Alternatively, the third transistor T3 can be an oxide thin film transistor (Oxide-TFT). Oxide thin film transistors have advantages such as low leakage current.

[0134] For example, please continue reading Figure 6 The coupling sub-circuit 202 within the pixel circuit 20 may include a first coupling sub-circuit 2021 and a second coupling sub-circuit 2022. The first coupling sub-circuit 2021 may be connected to the driving sub-circuit 201 and the second coupling sub-circuit 2022 respectively, and the second coupling sub-circuit 2022 may be connected to the first coupling sub-circuit 2021, the data writing sub-circuit 203 and the first control sub-circuit 204 respectively.

[0135] For example, please continue reading Figure 7 The first coupling sub-circuit 2021 may include a first capacitor C1, and the second coupling sub-circuit 2022 may include a second capacitor C2.

[0136] The first capacitor C1 may include a first plate and a second plate. The common terminal of the driving sub-circuit 201 and the coupling sub-circuit 202 is the first node N1. The first plate of the first capacitor C1 may be connected to the first node N1, and the second plate of the first capacitor C1 may be connected to the second capacitor C2.

[0137] The second capacitor C2 may include a third plate and a fourth plate. The common terminal of the coupling sub-circuit 202, the data writing sub-circuit 203, and the first control sub-circuit 204 is the third node N3. The third plate of the second capacitor C2 can be connected to the second plate of the first capacitor C1, and the fourth plate of the second capacitor C2 can be connected to the third node N3.

[0138] It should be noted that the aforementioned third node N3 does not represent an actual existing component, but rather the junction point of related connections in the equivalent circuit diagram of pixel circuit 20. In other words, the third node N3 is a node equivalent to the junction point of related connections in the equivalent circuit diagram of pixel circuit 20.

[0139] For example, please continue reading Figure 7 The data writing sub-circuit 203 within the pixel circuit 20 may include a fourth transistor T4.

[0140] Please continue reading. Figure 7 The fourth transistor T4 may include a control electrode, a first electrode, and a second electrode. The common terminal of the coupling sub-circuit 202, the data writing sub-circuit 203, and the first control sub-circuit 204 is the third node N3. The control electrode of the fourth transistor T4 can be connected to the first scan signal line Gate, the first electrode of the fourth transistor T4 can be connected to the data signal line Data, and the second electrode of the fourth transistor T4 can be connected to the third node N3.

[0141] For example, the control electrode of the fourth transistor T4 can be the gate, the first electrode of the fourth transistor T4 can be the source, and the second electrode of the fourth transistor T4 can be the drain. Alternatively, the control electrode of the fourth transistor T4 can be the gate, the first electrode of the fourth transistor T4 can be the drain, and the second electrode of the fourth transistor T4 can be the source.

[0142] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the data writing sub-circuit 203 includes a fourth transistor T4, the fourth transistor T4 may include a fourth active pattern T41 and a fourth gate T42. The orthographic projection of the fourth active pattern T41 in the fourth transistor T4 onto the substrate 1 and the orthographic projection of the fourth gate T42 in the fourth transistor T4 onto the substrate 1 overlap.

[0143] The fourth active pattern T41 within the fourth transistor T4 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0144] The aforementioned "the orthographic projection of the fourth active pattern T41 in the fourth transistor T4 onto the substrate 1 and the orthographic projection of the fourth gate T42 in the fourth transistor T4 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the fourth active pattern T41 onto the substrate 1 and the orthographic projection of the fourth gate T42 onto the substrate 1 overlap.

[0145] For example, please continue reading Figure 7 In the case where the data writing sub-circuit 203 includes a fourth transistor T4, the fourth transistor T4 can be a P-type transistor or an N-type transistor.

[0146] The following uses the example of a P-type transistor as the fourth transistor T4 in the data writing sub-circuit 203 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the fourth transistor T4 can also be other suitable types of transistors.

[0147] For example, when the data writing sub-circuit 203 includes a fourth transistor T4, the fourth transistor T4 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0148] For example, please continue reading Figure 7 The first control sub-circuit 204 within the pixel circuit 20 may include a first transistor T1.

[0149] Please continue reading. Figure 7 The first transistor T1 may include a control electrode, a first electrode, and a second electrode. The common terminal of the coupling sub-circuit 202, the first control sub-circuit 204, and the first control sub-circuit 204 is the third node N3. The control electrode of the first transistor T1 can be connected to the first control signal line EM1, the first electrode of the first transistor T1 can be connected to the first reference voltage signal line Vref1, and the second electrode of the first transistor T1 can be connected to the third node N3.

[0150] For example, the control electrode of the first transistor T1 can be the gate, the first electrode of the first transistor T1 can be the source, and the second electrode of the first transistor T1 can be the drain. Alternatively, the control electrode of the first transistor T1 can be the gate, the first electrode of the first transistor T1 can be the drain, and the second electrode of the first transistor T1 can be the source.

[0151] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the first control sub-circuit 204 includes a first transistor T1, the first transistor T1 may include a first active pattern T11 and a first gate T12. The orthographic projection of the first active pattern T11 in the first transistor T1 onto the substrate 1 and the orthographic projection of the first gate T12 in the first transistor T1 onto the substrate 1 overlap.

[0152] The first active pattern T11 within the first transistor T1 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0153] The aforementioned "the orthographic projection of the first active pattern T11 in the first transistor T1 onto the substrate 1 and the orthographic projection of the first gate T12 in the first transistor T1 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the first active pattern T11 onto the substrate 1 and the orthographic projection of the first gate T12 onto the substrate 1 overlap.

[0154] Please continue reading. Figure 7 and Figure 8 The first active pattern T11 within the first transistor T1 can be connected to the first reference voltage signal line Vref1.

[0155] For example, please continue reading Figure 7 When the first control sub-circuit 204 includes a first transistor T1, the first transistor T1 can be a P-type transistor or an N-type transistor.

[0156] The following uses a P-type transistor as an example of the first transistor T1 in the first control sub-circuit 204 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the first transistor T1 can also be other suitable types of transistors.

[0157] For example, when the first control sub-circuit 204 includes a first transistor T1, the first transistor T1 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0158] For example, please continue reading Figure 6 and Figure 7 and combined Figure 3 and Figure 4 In the case where the sub-pixel S also includes a light-emitting device 30, and the light-emitting device 30 includes a first electrode 311 and a second electrode 321, the first electrode 311 in the light-emitting device 30 can be connected to the driving sub-circuit 201, and the second electrode 321 in the light-emitting device 30 can be connected to the second voltage signal line V2.

[0159] In some embodiments, please continue reading Figure 6 and combined Figure 3 and Figure 4 In the case where the display panel 100 includes a sub-pixel S, the sub-pixel S includes a pixel circuit 20, and the pixel circuit 20 includes a driving sub-circuit 201, a coupling sub-circuit 202, a data writing sub-circuit 203, and a first control sub-circuit 204, the pixel circuit 20 may also include a second control sub-circuit 205, a compensation sub-circuit 206, a first light emission control sub-circuit 207, a second light emission control sub-circuit 208, a first reset sub-circuit 209, a second reset sub-circuit 210, and a third reset sub-circuit 211.

[0160] When the coupling sub-circuit 202 includes a first coupling sub-circuit 2021 and a second coupling sub-circuit 2022, the common terminal of the first coupling sub-circuit 2021 and the second coupling sub-circuit 2022 is the second node N2, and the second control sub-circuit 205 can be connected to the second scan signal line Az, the first voltage signal line V1 and the second node N2 respectively.

[0161] The common terminal of the driving sub-circuit 201 and the coupling sub-circuit 202 is the first node N1. The compensation sub-circuit 206 can be connected to the second scan signal line Az, the driving sub-circuit 201, the first reset sub-circuit 209 and the first node N1 respectively.

[0162] The first light-emitting control sub-circuit 207 can be connected to the first control signal line EM1, the first voltage signal line V1, and the driver sub-circuit 201, respectively.

[0163] When the sub-pixel S also includes a light-emitting device 30, and the light-emitting device 30 includes a first electrode 311 and a second electrode 321, the second light-emitting control sub-circuit 208 can be connected to the second control signal line EM2, the driving sub-circuit 201 and the first electrode 311 in the light-emitting device 30, respectively.

[0164] The common terminal of the driving sub-circuit 201, the compensation sub-circuit 206, and the second light-emitting control sub-circuit 208 is the fifth node N5. The first reset sub-circuit 209 can be connected to the first reset control signal line R1, the first initialization signal line Vinit1, and the fifth node N5, respectively.

[0165] The common terminal of the second light-emitting control sub-circuit 208 and the first electrode 311 in the light-emitting device 30 is the sixth node N6. The second reset sub-circuit 210 can be connected to the second reset control signal line R2, the second initialization signal line Vinit2 and the sixth node N6 respectively.

[0166] The common terminal of the driving sub-circuit 201 and the first light-emitting control sub-circuit 207 is the fourth node N4. The third reset sub-circuit 211 can be connected to the second reset control signal line R2, the second reference voltage signal line Vref2 and the fourth node N4 respectively.

[0167] It should be noted that the second node N2, the fifth node N5, the sixth node N6, and the fourth node N4 mentioned above do not represent actual existing components, but rather represent the junction points of related connections in the equivalent circuit diagram of the pixel circuit 20. In other words, the second node N2, the fifth node N5, the sixth node N6, and the fourth node N4 are nodes equivalent to the junction points of related connections in the equivalent circuit diagram of the pixel circuit 20.

[0168] For example, please continue reading Figure 7 The second control sub-circuit 205 within the pixel circuit 20 may include a ninth transistor T9.

[0169] Please continue reading. Figure 7 The ninth transistor T9 may include a control electrode, a first electrode, and a second electrode. The control electrode of the ninth transistor T9 may be connected to the second scan signal line Az, the first electrode of the ninth transistor T9 may be connected to the first voltage signal line V1, and the second electrode of the ninth transistor T9 may be connected to the second node N2.

[0170] For example, the control electrode of the ninth transistor T9 can be the gate, the first electrode of the ninth transistor T9 can be the source, and the second electrode of the ninth transistor T9 can be the drain. Alternatively, the control electrode of the ninth transistor T9 can be the gate, the first electrode of the ninth transistor T9 can be the drain, and the second electrode of the ninth transistor T9 can be the source.

[0171] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the second control sub-circuit 205 includes a ninth transistor T9, the ninth transistor T9 may include a ninth active pattern T91 and a ninth gate T92. The orthographic projection of the ninth active pattern T91 in the ninth transistor T9 onto the substrate 1 and the orthographic projection of the ninth gate T92 in the ninth transistor T9 onto the substrate 1 overlap.

[0172] The ninth active pattern T91 within the ninth transistor T9 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0173] The aforementioned "the orthographic projection of the ninth active pattern T91 in the ninth transistor T9 onto the substrate 1 and the orthographic projection of the ninth gate T92 in the ninth transistor T9 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the ninth active pattern T91 onto the substrate 1 and the orthographic projection of the ninth gate T92 onto the substrate 1 overlap.

[0174] For example, please continue reading Figure 7 In the case where the second control sub-circuit 205 includes a ninth transistor T9, the ninth transistor T9 can be a P-type transistor or an N-type transistor.

[0175] The following uses the example of a P-type transistor in the second control sub-circuit 205 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the ninth transistor T9 can also be other suitable types of transistors.

[0176] For example, when the second control sub-circuit 205 includes a ninth transistor T9, the ninth transistor T9 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0177] For example, please continue reading Figure 7 The compensator circuit 206 within the pixel circuit 20 may include a second transistor T2.

[0178] Please continue reading. Figure 7The second transistor T2 may include a control electrode, a first electrode, and a second electrode. The control electrode of the second transistor T2 may be connected to the second scan signal line Az, the first electrode of the second transistor T2 may be connected to the fifth node N5, and the second electrode of the second transistor T2 may be connected to the first node N1.

[0179] For example, the control electrode of the second transistor T2 can be the gate, the first electrode of the second transistor T2 can be the source, and the second electrode of the second transistor T2 can be the drain. Alternatively, the control electrode of the second transistor T2 can be the gate, the first electrode of the second transistor T2 can be the drain, and the second electrode of the second transistor T2 can be the source.

[0180] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the compensation sub-circuit 206 includes a second transistor T2, the second transistor T2 may include a second active pattern T21 and a second gate T22. The orthographic projection of the second active pattern T21 in the second transistor T2 onto the substrate 1 overlaps with the orthographic projection of the second gate T22 in the second transistor T2 onto the substrate 1.

[0181] The second active pattern T21 within the second transistor T2 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0182] The above-mentioned "the orthographic projection of the second active pattern T21 in the second transistor T2 onto the substrate 1 and the orthographic projection of the second gate T22 in the second transistor T2 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the second active pattern T21 onto the substrate 1 and the orthographic projection of the second gate T22 onto the substrate 1 overlap.

[0183] For example, please continue reading Figure 7 When the compensator circuit 206 includes a second transistor T2, the second transistor T2 can be a P-type transistor or an N-type transistor.

[0184] The following describes some embodiments of the present disclosure using the example of a P-type transistor as the second transistor T2 in the compensator circuit 206. However, the implementation of the present disclosure includes, but is not limited to, this, and the second transistor T2 can also be other suitable types of transistors.

[0185] For example, when the compensator circuit 206 includes a second transistor T2, the second transistor T2 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0186] For example, please continue reading Figure 7The first light-emitting control sub-circuit 207 within the pixel circuit 20 may include a fifth transistor T5.

[0187] Please continue reading. Figure 7 The fifth transistor T5 may include a control electrode, a first electrode, and a second electrode. The control electrode of the fifth transistor T5 may be connected to the first control signal line EM1, the first electrode of the fifth transistor T5 may be connected to the first voltage signal line V1, and the second electrode of the fifth transistor T5 may be connected to the driver sub-circuit 201.

[0188] For example, the control electrode of the fifth transistor T5 can be the gate, the first electrode of the fifth transistor T5 can be the source, and the second electrode of the fifth transistor T5 can be the drain. Alternatively, the control electrode of the fifth transistor T5 can be the gate, the first electrode of the fifth transistor T5 can be the drain, and the second electrode of the fifth transistor T5 can be the source.

[0189] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the first light-emitting control sub-circuit 207 includes a fifth transistor T5, the fifth transistor T5 may include a fifth active pattern T51 and a fifth gate T52. The orthographic projection of the fifth active pattern T51 in the fifth transistor T5 onto the substrate 1 and the orthographic projection of the fifth gate T52 in the fifth transistor T5 onto the substrate 1 overlap.

[0190] The fifth active pattern T51 within the fifth transistor T5 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0191] The aforementioned "the orthographic projection of the fifth active pattern T51 in the fifth transistor T5 onto the substrate 1 and the orthographic projection of the fifth gate T52 in the fifth transistor T5 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the fifth active pattern T51 onto the substrate 1 and the orthographic projection of the fifth gate T52 onto the substrate 1 overlap.

[0192] For example, please continue reading Figure 7 In the case where the first light-emitting control sub-circuit 207 includes a fifth transistor T5, the fifth transistor T5 can be a P-type transistor or an N-type transistor.

[0193] The following uses the example of a P-type transistor in the first light-emitting control sub-circuit 207 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the fifth transistor T5 can also be other suitable types of transistors.

[0194] For example, when the first light-emitting control sub-circuit 207 includes a fifth transistor T5, the fifth transistor T5 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0195] For example, please continue reading Figure 7 and combined Figure 3 and Figure 4 The second light-emitting control sub-circuit 208 within the pixel circuit 20 may include a sixth transistor T6.

[0196] Please continue reading. Figure 7 The sixth transistor T6 may include a control electrode, a first electrode, and a second electrode. The control electrode of the sixth transistor T6 may be connected to the second control signal line EM2, the first electrode of the sixth transistor T6 may be connected to the driver sub-circuit 201, and the second electrode of the sixth transistor T6 may be connected to the first electrode 311 within the light-emitting device 30.

[0197] For example, the control electrode of the sixth transistor T6 can be the gate, the first electrode of the sixth transistor T6 can be the source, and the second electrode of the sixth transistor T6 can be the drain. Alternatively, the control electrode of the sixth transistor T6 can be the gate, the first electrode of the sixth transistor T6 can be the drain, and the second electrode of the sixth transistor T6 can be the source.

[0198] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the second light-emitting control sub-circuit 208 includes a sixth transistor T6, the sixth transistor T6 may include a sixth active pattern T61 and a sixth gate T62. The orthographic projection of the sixth active pattern T61 in the sixth transistor T6 onto the substrate 1 and the orthographic projection of the sixth gate T62 in the sixth transistor T6 onto the substrate 1 overlap.

[0199] The sixth active pattern T61 within the sixth transistor T6 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0200] The aforementioned "the orthographic projection of the sixth active pattern T61 in the sixth transistor T6 onto the substrate 1 and the orthographic projection of the sixth gate T62 in the sixth transistor T6 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the sixth active pattern T61 onto the substrate 1 and the orthographic projection of the sixth gate T62 onto the substrate 1 overlap.

[0201] For example, please continue reading Figure 7 In the case where the second light-emitting control sub-circuit 208 includes a sixth transistor T6, the sixth transistor T6 can be a P-type transistor or an N-type transistor.

[0202] The following uses the example of a P-type transistor in the second light-emitting control sub-circuit 208 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the sixth transistor T6 can also be other suitable types of transistors.

[0203] For example, when the second light-emitting control sub-circuit 208 includes a sixth transistor T6, the sixth transistor T6 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0204] For example, please continue reading Figure 7 The first reset circuit 209 within the pixel circuit 20 may include the tenth transistor T10.

[0205] Please continue reading. Figure 7 The tenth transistor T10 may include a control electrode, a first electrode, and a second electrode. The control electrode of the tenth transistor T10 may be connected to the first reset control signal line R1, the first electrode of the tenth transistor T10 may be connected to the first initialization signal line Vinit1, and the second electrode of the tenth transistor T10 may be connected to the fifth node N5.

[0206] For example, the control electrode of the tenth transistor T10 can be the gate, the first electrode of the tenth transistor T10 can be the source, and the second electrode of the tenth transistor T10 can be the drain. Alternatively, the control electrode of the tenth transistor T10 can be the gate, the first electrode of the tenth transistor T10 can be the drain, and the second electrode of the tenth transistor T10 can be the source.

[0207] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the first reset circuit 209 includes a tenth transistor T10, the tenth transistor T10 may include a tenth active pattern T101 and a tenth gate T102. The orthographic projection of the tenth active pattern T101 in the tenth transistor T10 onto the substrate 1 and the orthographic projection of the tenth gate T102 in the tenth transistor T10 onto the substrate 1 overlap.

[0208] The tenth active pattern T101 within the tenth transistor T10 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0209] The aforementioned "the orthographic projection of the tenth active pattern T101 in the tenth transistor T10 onto the substrate 1 and the orthographic projection of the tenth gate T102 in the tenth transistor T10 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the tenth active pattern T101 onto the substrate 1 and the orthographic projection of the tenth gate T102 onto the substrate 1 overlap.

[0210] For example, please continue reading Figure 7 In the case where the first reset circuit 209 includes a tenth transistor T10, the tenth transistor T10 can be a P-type transistor or an N-type transistor.

[0211] The following uses the example of the tenth transistor T10 in the first reset circuit 209 being a P-type transistor to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the tenth transistor T10 may also be other suitable types of transistors.

[0212] For example, when the first reset circuit 209 includes a tenth transistor T10, the tenth transistor T10 may be a low-temperature polycrystalline silicon thin-film transistor or an oxide thin-film transistor, etc.

[0213] For example, please continue reading Figure 7 The second reset circuit 210 within the pixel circuit 20 may include a seventh transistor T7.

[0214] Please continue reading. Figure 7 The seventh transistor T7 may include a control electrode, a first electrode, and a second electrode. The control electrode of the seventh transistor T7 may be connected to the second reset control signal line R2, the first electrode of the seventh transistor T7 may be connected to the second initialization signal line Vinit2, and the second electrode of the seventh transistor T7 may be connected to the sixth node N6.

[0215] For example, the control electrode of the seventh transistor T7 can be the gate, the first electrode of the seventh transistor T7 can be the source, and the second electrode of the seventh transistor T7 can be the drain. Alternatively, the control electrode of the seventh transistor T7 can be the gate, the first electrode of the seventh transistor T7 can be the drain, and the second electrode of the seventh transistor T7 can be the source.

[0216] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the second reset circuit 210 includes a seventh transistor T7, the seventh transistor T7 may include a seventh active pattern T71 and a seventh gate T72. The orthographic projection of the seventh active pattern T71 in the seventh transistor T7 onto the substrate 1 and the orthographic projection of the seventh gate T72 in the seventh transistor T7 onto the substrate 1 overlap.

[0217] The seventh active pattern T71 within the seventh transistor T7 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0218] The aforementioned "the orthographic projection of the seventh active pattern T71 in the seventh transistor T7 onto the substrate 1 and the orthographic projection of the seventh gate T72 in the seventh transistor T7 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the seventh active pattern T71 onto the substrate 1 and the orthographic projection of the seventh gate T72 onto the substrate 1 overlap.

[0219] For example, please continue reading Figure 7 When the second reset circuit 210 includes a seventh transistor T7, the seventh transistor T7 can be a P-type transistor or an N-type transistor.

[0220] The following uses the example of a P-type transistor in the second reset circuit 210 to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the seventh transistor T7 can also be other suitable types of transistors.

[0221] For example, when the second reset circuit 210 includes a seventh transistor T7, the seventh transistor T7 may be a low-temperature polysilicon thin-film transistor or an oxide thin-film transistor, etc.

[0222] For example, please continue reading Figure 7 The third reset circuit 211 within the pixel circuit 20 may include an eighth transistor T8.

[0223] Please continue reading. Figure 7 The eighth transistor T8 may include a control electrode, a first electrode, and a second electrode. The control electrode of the eighth transistor T8 may be connected to the second reset control signal line R2, the first electrode of the eighth transistor T8 may be connected to the second reference voltage signal line Vref2, and the second electrode of the eighth transistor T8 may be connected to the fourth node N4.

[0224] For example, the control electrode of the eighth transistor T8 can be the gate, the first electrode of the eighth transistor T8 can be the source, and the second electrode of the eighth transistor T8 can be the drain. Alternatively, the control electrode of the eighth transistor T8 can be the gate, the first electrode of the eighth transistor T8 can be the drain, and the second electrode of the eighth transistor T8 can be the source.

[0225] For example, please continue reading Figure 8 , Figure 9 and Figure 10 and combined Figure 7 When the third reset circuit 211 includes an eighth transistor T8, the eighth transistor T8 may include an eighth active pattern T81 and an eighth gate T82. The orthographic projection of the eighth active pattern T81 in the eighth transistor T8 onto the substrate 1 and the orthographic projection of the eighth gate T82 in the eighth transistor T8 onto the substrate 1 overlap.

[0226] The eighth active pattern T81 within the eighth transistor T8 may include a first electrode, a second electrode, and a channel region located between the first electrode and the second electrode.

[0227] The aforementioned "the orthographic projection of the eighth active pattern T81 in the eighth transistor T8 onto the substrate 1 and the orthographic projection of the eighth gate T82 in the eighth transistor T8 onto the substrate 1 overlap" can specifically be the orthographic projection of the channel region in the eighth active pattern T81 onto the substrate 1 and the orthographic projection of the eighth gate T82 onto the substrate 1 overlap.

[0228] For example, please continue reading Figure 7 In the case where the third reset circuit 211 includes an eighth transistor T8, the eighth transistor T8 can be a P-type transistor or an N-type transistor.

[0229] The following uses the eighth transistor T8 in the third reset circuit 211 as an example of a P-type transistor to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the eighth transistor T8 can also be other suitable types of transistors.

[0230] For example, when the third reset circuit 211 includes an eighth transistor T8, the eighth transistor T8 may be a low-temperature polysilicon thin-film transistor or an oxide thin-film transistor, etc.

[0231] In some embodiments, such as Figure 11 As shown, and in combination Figure 7 , Figure 11This is a timing diagram showing the driving of a pixel circuit 20 within a sub-pixel S according to some embodiments. The sub-pixel S within the display panel 100 includes a pixel circuit 20 and a light-emitting device 30. The pixel circuit 20 includes a driving sub-circuit 201, a coupling sub-circuit 202, a data writing sub-circuit 203, a first control sub-circuit 204, a second control sub-circuit 205, a compensation sub-circuit 206, a first light-emitting control sub-circuit 207, a second light-emitting control sub-circuit 208, a first reset sub-circuit 209, a second reset sub-circuit 210, and a third reset sub-circuit 211. The driving sub-circuit 201 includes a third transistor T3, the coupling sub-circuit 202 includes a first capacitor C1 and a second capacitor C2, the data writing sub-circuit 203 includes a fourth transistor T4, and the first control sub-circuit 204 includes a first capacitor C1 and a second capacitor C2. In the case that a transistor T1 is included, a second control sub-circuit 205 includes a ninth transistor T9, a compensation sub-circuit 206 includes a second transistor T2, a first light-emitting control sub-circuit 207 includes a fifth transistor T5, a second light-emitting control sub-circuit 208 includes a sixth transistor T6, a first reset sub-circuit 209 includes a tenth transistor T10, a second reset sub-circuit 210 includes a seventh transistor T7, and a third reset sub-circuit 211 includes an eighth transistor T8, the driving process of the pixel circuit 20 driving the light-emitting device 30 to emit light may include a first reset stage t11, a second reset stage t12, a bias stage t13, a threshold compensation stage t14, a data writing stage t15, and a light-emitting stage t16.

[0232] It should be noted that, in Figure 11 In this context, Vgs refers to the voltage difference between the gate and source of the third transistor T3.

[0233] First reset phase t11: Please refer to the following: Figure 11 and combined Figure 12 , Figure 12 for Figure 7 The pixel circuit 20 shown is in state diagrams for the first reset phase t11 and the second reset phase t12. The second scan signal provided by the second scan signal line Az is at a low level, and both the second transistor T2 and the ninth transistor T9 are in the on state. The first voltage signal provided by the first voltage signal line V1 can be transmitted to the second node N2 through the ninth transistor T9 to initialize the potential of the second node N2. The second reset control signal provided by the second reset control signal line R2 is at a low level, and both the seventh transistor T7 and the eighth transistor T8 are in the on state. The second initialization signal provided by the second initialization signal line Vinit2 can be transmitted to the sixth node N6 through the seventh transistor T7 to initialize the potential of the sixth node N6. The second reference voltage signal provided by the second reference voltage signal line Vref2 can be transmitted to the fourth node N4 through the eighth transistor T8 to initialize the potential of the fourth node N4.

[0234] Second reset phase t12: Please refer to the following: Figure 11 and Figure 12 The second scan signal provided by the second scan signal line Az is at a low level, the second transistor T2 is in the on state, the first reset control signal provided by the first reset control signal line R1 is at a low level, the tenth transistor T10 is in the on state, the first initialization signal provided by the first initialization signal line Vinit1 can be transmitted to the fifth node N5 through the tenth transistor T10 to initialize the potential of the fifth node N5, and can be transmitted to the first node N1 through the second transistor T2 to initialize the potential of the first node N1.

[0235] Bias phase t13: Please refer to the following section. Figure 11 The second reset control signal provided by the second reset control signal line R2 is at a low level, the eighth transistor T8 is in the on state, the second reference voltage signal provided by the second reference voltage signal line Vref2 can be transmitted to the fourth node N4 through the eighth transistor T8, and the third transistor T3 is in the bias state.

[0236] Threshold compensation stage t14: Please refer to the following section. Figure 11 and combined Figure 13 , Figure 13 for Figure 7 The pixel circuit 20 shown is in state during threshold compensation stage t14. The second scan signal provided by the second scan signal line Az is at a low level, and both the second transistor T2 and the ninth transistor T9 are in the on state. The first voltage signal provided by the first voltage signal line V1 can be transmitted to the second node N2 through the ninth transistor T9. The first control signal provided by the first control signal line EM1 is at a low level, and both the first transistor T1 and the fifth transistor T5 are in the on state. The first reference voltage signal provided by the first reference voltage signal line Vref1 can be transmitted to the third node N3 through the first transistor T1 to initialize the potential of the third node N3. The first voltage signal provided by the first voltage signal line V1 can be transmitted to the fourth node N4 through the fifth transistor T5. The third transistor T3 is in the on state, and the first voltage signal provided by the first voltage signal line V1 can charge the first node N1 through the fifth transistor T5, the third transistor T3, and the second transistor T2 until the threshold voltage of the third transistor T3 is stored in the first capacitor C1.

[0237] Data writing phase t15: Please refer to the following section. Figure 11 and combined Figure 14 , Figure 14 for Figure 7The diagram shows the state of the pixel circuit 20 during the data writing phase t15. First, the first scan signal provided by the first scan signal line Gate is low, the fourth transistor T4 is turned on, and the data signal provided by the data signal line Data can be transmitted to the third node N3 through the fourth transistor T4. Then, the first control signal provided by the first control signal line EM1 is low, the first transistor T1 is turned on, and the first reference voltage signal provided by the first reference voltage signal line Vref1 can be transmitted to the third node N3 through the first transistor T1, and the data signal is transmitted to the first node N1 through the coupling effect of the coupling sub-circuit 202.

[0238] Phase 16: Please refer to the following section. Figure 11 and combined Figure 15 , Figure 15 for Figure 7 The diagram shows the state of the pixel circuit 20 during the light-emitting stage t16. The first control signal provided by the first control signal line EM1 is low, and both the first transistor T1 and the fifth transistor T5 are in the on state. The second control signal provided by the second control signal line EM2 is low, and the sixth transistor T6 is in the on state, allowing the third transistor T3 to drive the light-emitting device 30 to emit light.

[0239] For example, such as Figure 16 As shown, and in combination Figure 7 and Figure 11 , Figure 16 This is a timing diagram showing the driving of the pixel circuit 20 within a sub-pixel S according to some embodiments. The refresh rate of the display panel 100 can be switched to achieve low-frequency driving, which helps to reduce the power consumption of the display panel 100 and improve the display quality of the display panel 100.

[0240] When the display panel 100 switches refresh rates, there are usually several adjustment methods. One such method is to reduce the refresh rate based on the base refresh rate (i.e., the fundamental frequency), typically by reducing the refresh rate in integer multiples. Reducing the refresh rate in integer multiples is called frame interpolation frequency modulation. In frame interpolation, the display frames at the base refresh rate include write frames, while the display frames after reducing the refresh rate from the base refresh rate include write frames and hold frames.

[0241] In other words, by inserting hold frames between adjacent write frames, the refresh rate of the display panel 100 can be reduced, and by changing the number of hold frames inserted between adjacent write frames, the reduction factor of the refresh rate can be changed.

[0242] For example, if the base refresh rate is 120Hz, inserting one hold frame reduces the refresh rate to 60Hz, inserting two hold frames reduces the refresh rate to 40Hz, and so on. Switching between two different refresh rates can be between the base refresh rate and the refresh rate after downscaling from the base refresh rate, or it can be between two refresh rates after downscaling from the same base refresh rate.

[0243] In some embodiments, such as Figure 17 and Figure 18 As shown, Figure 17 and Figure 18 All are equivalent circuit diagrams of pixel circuits 20 within sub-pixels S according to some embodiments. In a display panel 100 comprising multiple sub-pixels S and a first reference voltage signal line Vref1, where each sub-pixel S includes a pixel circuit 20, the pixel circuit 20 includes a first control sub-circuit 204, the first reference voltage signal line Vref1 is connected to the first control sub-circuit 204, and the multiple sub-pixels S within the display panel 100 include a first color sub-pixel S1 and a second color sub-pixel S2, the first reference voltage signal line Vref1 may include a first sub-signal line Vref11 and a second sub-signal line Vref12. The first sub-signal line Vref11 may be connected to the first control sub-circuit 204 of the pixel circuit 20 within the first color sub-pixel S1, and the second sub-signal line Vref12 may be connected to the first control sub-circuit 204 of the pixel circuit 20 within the second color sub-pixel S2.

[0244] In the aforementioned display panel 100, the first reference voltage signal line Vref1 includes a first sub-signal line Vref11 and a second sub-signal line Vref12. The first sub-signal line Vref11 is connected to the first control sub-circuit 204 of the pixel circuit 20 in the first color sub-pixel S1, and the second sub-signal line Vref12 is connected to the first control sub-circuit 204 of the pixel circuit 20 in the second color sub-pixel S2. On the one hand, the connection between the first color sub-pixel S1 and the first sub-signal line Vref11 in the first reference voltage signal line Vref1, and the connection between the second color sub-pixel S2 and the second sub-signal line Vref12 in the first reference voltage signal line Vref1, can realize independent driving of the first color sub-pixel S1 and the second color sub-pixel S2. This is beneficial to improving the driving capability of the first reference voltage signal line Vref1 and improving the stability of the first reference voltage signal transmitted in the first reference voltage signal line Vref1. In turn, it is beneficial to reduce the probability of flickering of the image displayed by the display panel 100 due to voltage fluctuations of the first reference voltage signal, thereby improving the display effect of the display panel 100.

[0245] On the other hand, when the pixel circuit 20 includes a driving sub-circuit 201, and the driving sub-circuit 201 includes a third transistor T3, the saturation current I of the third transistor T3 is I = 1 / 2 * μ * Cox * W / L * (Vref1 - Vdata)^2, where μ represents the carrier mobility in the third transistor T3, Cox represents the capacitance per unit area of ​​the oxide layer, W / L represents the ratio of the width to the length of the channel region in the third transistor T3, and (Vref1 - Vdata) represents the difference between the voltage of the first reference voltage signal transmitted in the first reference voltage signal line Vref1 and the voltage of the data signal transmitted in the data signal line Data.

[0246] As shown in the above formula, the saturation current I of the third transistor T3 is related to (Vref1-Vdata). Since the first color sub-pixel S1 is connected to the first sub-signal line Vref11 within the first reference voltage signal line Vref1, and the second color sub-pixel S2 is connected to the second sub-signal line Vref12 within the first reference voltage signal line Vref1, the voltage of the first sub-signal transmitted within the first sub-signal line Vref11 and the voltage of the second sub-signal transmitted within the second sub-signal line Vref12 can be adjusted respectively. This reduces or approaches zero the difference between the voltage of the data signal transmitted within the data signal line Data connected to the first color sub-pixel S1 and the voltage of the data signal transmitted within the data signal line Data connected to the second color sub-pixel S2. Consequently, the effective driving voltage range of the source driver chip (i.e., the voltage gate maximum positive (VGMP) and voltage gate minimum positive (VGMP)) can be reduced. The difference between the positive (VGSP) and the source driver chip reduces the power consumption, which in turn helps to reduce the driving power consumption of the display panel 100.

[0247] When the effective driving voltage range of the source driver chip is reduced, the difference between the high-level voltage (Voltage Gate High, VGH) and low-level voltage (Voltage Gate Low, VGL) of the first scan signal transmitted in the first scan signal line Gate can also be reduced, which is beneficial to further reduce the driving power consumption of the display panel 100.

[0248] On the other hand, when the display panel 100 is in display modes such as High Brightness Mode (HBM) or Average Picture Level (APL), the voltage of the first sub-signal transmitted in the first sub-signal line Vref11 can be adjusted to increase the current of the third transistor T3 in the pixel circuit 20 of the first color sub-pixel S1, and the voltage of the second sub-signal transmitted in the second sub-signal line Vref12 can be adjusted to increase the current of the third transistor T3 in the pixel circuit 20 of the second color sub-pixel S2. This can reduce the probability of insufficient driving current of the third transistor T3, thereby helping the display panel 100 to achieve high brightness display.

[0249] On the other hand, please continue to refer to Figure 16 and Figure 17 When the display panel 100 is in low-frequency display mode, the brightness of the light-emitting device 30 in the first color sub-pixel S1 can be adjusted and compensated in real time by dynamically adjusting the voltage of the first sub-signal transmitted in the first sub-signal line Vref11. This helps to reduce the probability of uneven brightness of the light-emitting device 30 in the first color sub-pixel S1 during the write frame and hold frame due to transistor leakage and back-to-source (BTS) hysteresis. As a result, the brightness of the light-emitting device 30 in the first color sub-pixel S1 can be kept uniform and stable during the write frame and hold frame, thereby reducing the probability of flickering in the image displayed by the display panel 100 and further improving the display effect of the display panel 100.

[0250] Please continue reading. Figure 16 and Figure 18 When the display panel 100 is in low-frequency display mode, the brightness of the light-emitting device 30 in the second color sub-pixel S2 can be adjusted and compensated in real time by dynamically adjusting the voltage of the second sub-signal transmitted in the second sub-signal line Vref12. This helps to reduce the probability of uneven brightness of the light-emitting device 30 in the second color sub-pixel S2 during the write frame and hold frame due to transistor leakage and source retrace hysteresis. As a result, the brightness of the light-emitting device 30 in the second color sub-pixel S2 can be kept uniform and stable during the write frame and hold frame, which helps to further reduce the probability of flickering in the image displayed by the display panel 100 and further improve the display effect of the display panel 100.

[0251] For example, such as Figure 19 As shown, Figure 19This is a plan view of a partial region of the first conductive layer 21 within the pixel driving layer 2 of a display panel 100 according to some embodiments. The first sub-signal line Vref11 may extend along the second direction X.

[0252] For example, such as Figure 20 As shown, Figure 20 This is a plan view of a partial region of the second conductive layer 22 within the pixel driving layer 2 of a display panel 100 according to some embodiments. The second sub-signal line Vref12 may extend along the second direction X.

[0253] For example, such as Figure 21 As shown, Figure 21 This is a plan view of a partial region of a substrate 1 within a display panel 100 according to some embodiments, and a first conductive layer 21 and a second conductive layer 22 within a pixel driving layer 2. The first sub-signal line Vref11 and the second sub-signal line Vref12 may be parallel to the substrate 1 within the display panel 100, and the first sub-signal line Vref11 may be substantially parallel to the second sub-signal line Vref12.

[0254] It should be noted that the above statement "the first sub-signal line Vref11 can be roughly parallel to the second sub-signal line Vref12" means that the extension direction of the first sub-signal line Vref11 and the extension direction of the second sub-signal line Vref12 are basically the same. There may be slight angular deviations or local slight displacements due to manufacturing process errors or wiring space limitations, but there are no obvious intersections or large directional deviations.

[0255] For example, please continue reading Figure 21 The orthographic projection of the first sub-signal line Vref11 onto the substrate 1 within the display panel 100 can overlap with the orthographic projection of the second sub-signal line Vref12 onto the substrate 1.

[0256] For example, such as Figure 22 As shown, and in combination Figure 17 , Figure 22 This is a plan view of a portion of the substrate 1 within the display panel 100 according to some embodiments, and of the first active layer 26, the first conductive layer 21, and the second conductive layer 22 within the pixel driving layer 2. In the pixel circuit 20, the first control sub-circuit 204 includes a first transistor T1, which includes a first active pattern T11. When the first active pattern T11 is connected to the first reference voltage signal line Vref1, the orthographic projection of the first active pattern T11 onto the substrate 1 can overlap with the orthographic projection of the first sub-signal line Vref11 onto the substrate 1.

[0257] For example, please continue reading Figure 22 and combined Figure 18The first control sub-circuit 204 in the pixel circuit 20 includes a first transistor T1, the first transistor T1 includes a first active pattern T11, and when the first active pattern T11 is connected to the first reference voltage signal line Vref1, the orthogonal projection of the first active pattern T11 onto the substrate 1 can overlap with the orthogonal projection of the second sub-signal line Vref12 onto the substrate 1.

[0258] For example, the voltage value of the first sub-signal transmitted in the first sub-signal line Vref11 can be greater than or equal to 0.5V and less than or equal to 4.5V.

[0259] For example, the voltage value of the first sub-signal transmitted in the first sub-signal line Vref11 can be 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V, 3 V, 3.5 V, 4 V or 4.5 V, etc.

[0260] For example, the voltage value of the second sub-signal transmitted within the second sub-signal line Vref12 can be greater than or equal to 0.5V and less than or equal to 4.5V.

[0261] For example, the voltage value of the second sub-signal transmitted in the second sub-signal line Vref12 can be 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V, 3 V, 3.5 V, 4 V or 4.5 V, etc.

[0262] For example, the material of the first sub-signal line Vref11 may include molybdenum (Mo) or the like.

[0263] For example, the material of the second sub-signal line Vref12 may include molybdenum (Mo) or the like.

[0264] In some embodiments, such as Figure 23 As shown, Figure 23 This is an equivalent circuit diagram of the pixel circuit 20 within a sub-pixel S according to some embodiments. In a display panel 100 that includes a plurality of sub-pixels S and a first reference voltage signal line Vref1, where each sub-pixel S includes a pixel circuit 20, the pixel circuit 20 includes a first control sub-circuit 204, the first reference voltage signal line Vref1 is connected to the first control sub-circuit 204, and the plurality of sub-pixels S within the display panel 100 includes a third color sub-pixel S3, the first reference voltage signal line Vref1 may include a third sub-signal line Vref13, and the third sub-signal line Vref13 may be connected to the first control sub-circuit 204 of the pixel circuit 20 within the third color sub-pixel S3.

[0265] Please continue reading. Figure 17 , Figure 18 and Figure 23In the aforementioned display panel 100, the plurality of sub-pixels S within the display panel 100 further include a first color sub-pixel S1 and a second color sub-pixel S2. The first reference voltage signal line Vref1 further includes a first sub-signal line Vref11 and a second sub-signal line Vref12. The first sub-signal line Vref11 is connected to the first control sub-circuit 204 of the pixel circuit 20 within the first color sub-pixel S1, and the second sub-signal line Vref12 is connected to the first control sub-circuit 204 of the pixel circuit 20 within the second color sub-pixel S2. In the case where the first color sub-pixel S1 is connected to the first sub-signal line Vref11 within the first reference voltage signal line Vref1, and the second color sub-pixel S2 is connected to the first reference voltage signal line... The second sub-signal line Vref12 within Vref1 is connected, and the third color sub-pixel S3 is connected to the third sub-signal line Vref13 within the first reference voltage signal line Vref1. This enables independent driving of the first color sub-pixel S1, the second color sub-pixel S2, and the third color sub-pixel S3, which is beneficial for further improving the driving capability of the first reference voltage signal line Vref1 and the stability of the first reference voltage signal transmitted within the first reference voltage signal line Vref1. This, in turn, helps to further reduce the probability of flickering in the image displayed on the display panel 100 due to voltage fluctuations in the first reference voltage signal, thereby further improving the display effect of the display panel 100.

[0266] On the other hand, when the pixel circuit 20 includes a driving sub-circuit 201, and the driving sub-circuit 201 includes a third transistor T3, the saturation current I of the third transistor T3 is related to (Vref1-Vdata). Since the first color sub-pixel S1 is connected to the first sub-signal line Vref11 within the first reference voltage signal line Vref1, the second color sub-pixel S2 is connected to the second sub-signal line Vref12 within the first reference voltage signal line Vref1, and the third color sub-pixel S3 is connected to the third sub-signal line Vref13 within the first reference voltage signal line Vref1, the first sub-signal line transmitted within the first sub-signal line Vref11 can be controlled respectively. The voltage of the first sub-pixel S1, the voltage of the second sub-signal transmitted in the second sub-signal line Vref12, and the voltage of the third sub-signal transmitted in the third sub-signal line Vref13 reduce or approach 0 the difference between the voltage of the data signal transmitted in the data signal line Data connected to the first color sub-pixel S1, the data signal transmitted in the data signal line Data connected to the second color sub-pixel S2, and the data signal transmitted in the data signal line Data connected to the third color sub-pixel S3. This reduces the effective driving voltage range of the source driver chip, thereby reducing the power consumption of the source driver chip and thus helping to reduce the driving power consumption of the display panel 100.

[0267] When the effective driving voltage range of the source driver chip is reduced, the difference between the high-level voltage and the low-level voltage of the first scan signal transmitted in the first scan signal line Gate can also be reduced, which is beneficial to further reduce the driving power consumption of the display panel 100.

[0268] On the other hand, when the display panel 100 is in a high brightness mode or an average image level high brightness mode, the voltage of the third sub-signal transmitted in the third sub-signal line Vref13 can be adjusted to increase the current of the third transistor T3 in the pixel circuit 20 in the third color sub-pixel S3. This can reduce the probability of insufficient driving current of the third transistor T3, thereby helping the display panel 100 to achieve high brightness display.

[0269] On the other hand, please continue to refer to Figure 16 and Figure 23 When the display panel 100 is in low-frequency display mode, the brightness of the light-emitting device 30 in the third color sub-pixel S3 can be adjusted and compensated in real time by dynamically adjusting the voltage of the third sub-signal transmitted in the third sub-signal line Vref13. This helps to reduce the probability of uneven brightness of the light-emitting device 30 in the third color sub-pixel S3 during the write frame and hold frame due to transistor leakage and back-to-source (BTS) hysteresis. As a result, the brightness of the light-emitting device 30 in the third color sub-pixel S3 can be kept uniform and stable during the write frame and hold frame, thereby reducing the probability of flickering in the image displayed by the display panel 100 and further improving the display effect of the display panel 100.

[0270] For example, such as Figure 24 As shown, Figure 24 This is a plan view of a partial region of the third conductive layer 23 within the pixel driving layer 2 of a display panel 100 according to some embodiments. The third sub-signal line Vref13 may extend along the second direction X.

[0271] For example, please continue reading Figure 21 and Figure 24 When the first reference voltage signal line Vref1 also includes a first sub-signal line Vref11 and a second sub-signal line Vref12, the first sub-signal line Vref11, the second sub-signal line Vref12 and the third sub-signal line Vref13 can be parallel to the substrate 1 in the display panel 100, and the first sub-signal line Vref11 can be approximately parallel to the second sub-signal line Vref12 and the third sub-signal line Vref13.

[0272] It should be noted that the statement "the first sub-signal line Vref11 can be roughly parallel to the second sub-signal line Vref12 and the third sub-signal line Vref13" means that the extension directions of the first sub-signal line Vref11, the second sub-signal line Vref12, and the third sub-signal line Vref13 are basically the same. There may be slight angular deviations or local slight displacements due to manufacturing process errors or wiring space limitations, but there are no obvious intersections or large directional deviations.

[0273] For example, such as Figure 25 As shown, Figure 25 This is a plan view of a partial region of the substrate 1 within the display panel 100 according to some embodiments, and the first conductive layer 21 and the third conductive layer 23 within the pixel driving layer 2. When the first reference voltage signal line Vref1 further includes a first sub-signal line Vref11, the orthogonal projection of the third sub-signal line Vref13 onto the substrate 1 may be located on one side of the orthogonal projection of the first sub-signal line Vref11 onto the substrate 1.

[0274] For example, please continue reading Figure 25 The orthogonal projection of the third sub-signal line Vref13 onto the substrate 1 can be located on the side of the orthogonal projection of the first sub-signal line Vref11 onto the substrate 1 along the third direction Y.

[0275] For example, such as Figure 26 As shown, Figure 26 This is a plan view of a partial region of the substrate 1 within the display panel 100 according to some embodiments, and the second conductive layer 22 and the third conductive layer 23 within the pixel driving layer 2. When the first reference voltage signal line Vref1 further includes a second sub-signal line Vref12, the orthogonal projection of the third sub-signal line Vref13 onto the substrate 1 may be located on one side of the orthogonal projection of the second sub-signal line Vref12 onto the substrate 1.

[0276] For example, please continue reading Figure 26 The orthogonal projection of the third sub-signal line Vref13 onto the substrate 1 can be located on the side of the orthogonal projection of the second sub-signal line Vref12 onto the substrate 1 along the third direction Y.

[0277] For example, such as Figure 27 As shown, and in combination Figure 23 , Figure 27This is a plan view of a portion of the substrate 1 within the display panel 100 according to some embodiments, and of the first active layer 26 and the third conductive layer 23 within the pixel driving layer 2. In the pixel circuit 20, the first control sub-circuit 204 includes a first transistor T1, which includes a first active pattern T11. When the first active pattern T11 is connected to the first reference voltage signal line Vref1, the orthographic projection of the first active pattern T11 onto the substrate 1 can overlap with the orthographic projection of the third sub-signal line Vref13 onto the substrate 1.

[0278] For example, such as Figure 28 As shown, Figure 28 This is a plan view of a partial region of the substrate 1 within the display panel 100 according to some embodiments, and the first active layer 26, the first conductive layer 21, and the third conductive layer 23 within the pixel driving layer 2. In the case where the first reference voltage signal line Vref1 further includes a first sub-signal line Vref11, and the orthographic projection of the first sub-signal line Vref11 onto the substrate 1 overlaps with the orthographic projection of the first active pattern T11 onto the substrate 1, the display panel 100 may further include a first connecting portion 231, through which the third sub-signal line Vref13 is connected to the first active pattern T11. The orthographic projection of the first connecting portion 231 onto the substrate 1 may overlap with the orthographic projection of the first sub-signal line Vref11 onto the substrate 1.

[0279] For example, the voltage value of the third sub-signal transmitted in the third sub-signal line Vref13 can be greater than or equal to 0.5V and less than or equal to 4.5V.

[0280] For example, the voltage value of the third sub-signal transmitted in the third sub-signal line Vref13 can be 0.5 V, 1 V, 1.5 V, 2 V, 2.5 V, 3 V, 3.5 V, 4 V or 4.5 V, etc.

[0281] For example, the material of the third sub-signal line Vref13 may include molybdenum (Mo) or the like.

[0282] In some embodiments, such as Figure 29 As shown, Figure 29This is a plan view of a partial region of the first conductive layer 21 and the fourth conductive layer 24 within the pixel driving layer 2 of a display panel 100 according to some embodiments. When the display panel 100 includes a first reference voltage signal line Vref1, and the first reference voltage signal line Vref1 includes a first sub-signal line Vref11, the display panel 100 may further include a fourth sub-signal line Vref14, which is connected to the first sub-signal line Vref11. The orthographic projection of the fourth sub-signal line Vref14 onto the substrate 1 within the display panel 100 may intersect with the orthographic projection of the first sub-signal line Vref11 onto the substrate 1.

[0283] For example, please continue reading Figure 29 The first sub-signal line Vref11 can extend along the second direction X, and the fourth sub-signal line Vref14 can extend along the third direction Y.

[0284] In the aforementioned display panel 100, the fourth sub-signal line Vref14 is connected to the first sub-signal line Vref11, such that both the fourth sub-signal line Vref14 and the first sub-signal line Vref11 are used to transmit the first sub-signal. Since the fourth sub-signal line Vref14 extends along the third direction Y, and the first sub-signal line Vref11 extends along the second direction X, and the second direction X intersects with the third direction Y, the first sub-signal line Vref11 extending along the second direction X and the fourth sub-signal line Vref14 extending along the third direction Y can jointly form a mesh structure, which is beneficial to reducing the loss of the first sub-signal during transmission, and thus beneficial to reducing the voltage drop difference between the first sub-signals in different areas within the display panel 100, thereby improving the display effect of the display panel 100.

[0285] For example, such as Figure 30 As shown, Figure 30 This is a plan view of a partial region of the substrate 1 within the display panel 100 according to some embodiments, and the first active layer 26, the fifth conductive layer 25, and the fourth conductive layer 24 within the pixel driving layer 2. When the display panel 100 includes a plurality of pixel circuits 20, and the plurality of pixel circuits 20 are arranged along the extension direction (i.e., the second direction X) of the first sub-signal line Vref11, in a projected image onto the substrate 1, the fourth sub-signal line Vref14 may be located between two adjacent pixel circuits 20.

[0286] In some embodiments, such as Figure 31 As shown, Figure 31This is a plan view of a partial region of the second conductive layer 22 and the fourth conductive layer 24 within the pixel driving layer 2 of a display panel 100 according to some embodiments. When the display panel 100 includes a first reference voltage signal line Vref1, and the first reference voltage signal line Vref1 includes a second sub-signal line Vref12, the display panel 100 may further include a fifth sub-signal line Vref15, which is connected to the second sub-signal line Vref12. The orthographic projection of the fifth sub-signal line Vref15 onto the substrate 1 within the display panel 100 may intersect with the orthographic projection of the second sub-signal line Vref12 onto the substrate 1.

[0287] For example, please continue reading Figure 31 The second sub-signal line Vref12 can extend along the second direction X, and the fifth sub-signal line Vref15 can extend along the third direction Y.

[0288] In the aforementioned display panel 100, the fifth sub-signal line Vref15 is connected to the second sub-signal line Vref12, such that both the fifth sub-signal line Vref15 and the second sub-signal line Vref12 are used to transmit the second sub-signal. Since the fifth sub-signal line Vref15 extends along the third direction Y, and the second sub-signal line Vref12 extends along the second direction X, and the second direction X intersects with the third direction Y, the second sub-signal line Vref12 extending along the second direction X and the fifth sub-signal line Vref15 extending along the third direction Y can jointly form a mesh structure, which is beneficial to reducing the loss of the second sub-signal during transmission, and thus beneficial to reducing the voltage drop difference between the second sub-signals in different areas within the display panel 100, thereby improving the display effect of the display panel 100.

[0289] For example, please continue reading Figure 30 In the case where the display panel 100 includes a plurality of pixel circuits 20 and the plurality of pixel circuits 20 are arranged along the extension direction of the first sub-signal line Vref11 (i.e., the second direction X), the fifth sub-signal line Vref15 may be located between two adjacent pixel circuits 20 in the orthogonal projection onto the substrate 1.

[0290] For example, such as Figure 32 As shown, Figure 32 This is a plan view of a partial area of ​​the fourth conductive layer 24 within the pixel driving layer 2 of the display panel 100 according to some embodiments. When the first reference voltage signal line Vref1 further includes a fourth sub-signal line Vref14, the fourth sub-signal line Vref14 and the fifth sub-signal line Vref15 can be disposed on the same layer, and the fourth sub-signal line Vref14 can be substantially parallel to the fifth sub-signal line Vref15.

[0291] It should be noted that the above statement that "the fourth sub-signal line Vref14 can be roughly parallel to the fifth sub-signal line Vref15" means that the extension direction of the fourth sub-signal line Vref14 and the extension direction of the fifth sub-signal line Vref15 are basically the same. There may be slight angular deviations or local slight displacements due to manufacturing process errors or wiring space limitations, but there is no obvious intersection or large directional deviation.

[0292] Please continue reading. Figure 32 The fourth sub-signal line Vref14 and the fifth sub-signal line Vref15 can be arranged at intervals along the second direction X.

[0293] For example, please continue reading Figure 32 The fourth sub-signal line Vref14 and the fifth sub-signal line Vref15 can be arranged alternately along the second direction X.

[0294] For example, please continue reading Figure 30 In the case where the display panel 100 includes a plurality of pixel circuits 20, the plurality of pixel circuits 20 are arranged along the extension direction (i.e., the second direction X) of the first sub-signal line Vref11, and the plurality of pixel circuits 20 include a plurality of pixel circuit groups 20a, in the orthographic projection onto the substrate 1 within the display panel 100, the pixel circuit group 20a may be located between adjacent fourth sub-signal lines Vref14 and fifth sub-signal lines Vref15.

[0295] For example, the material of the fourth sub-signal line Vref14 may include titanium (Ti) and aluminum (Al), etc.

[0296] For example, the material of the fifth sub-signal line Vref15 may include titanium (Ti) and aluminum (Al), etc.

[0297] In some embodiments, such as Figure 33 As shown, Figure 33 This is a plan view of a partial region of the third conductive layer 23 and the fourth conductive layer 24 within the pixel driving layer 2 of a display panel 100 according to some embodiments. When the display panel 100 includes a first reference voltage signal line Vref1, and the first reference voltage signal line Vref1 includes a third sub-signal line Vref13, the display panel 100 may further include a sixth sub-signal line Vref16, which is connected to the third sub-signal line Vref13. The orthographic projection of the sixth sub-signal line Vref16 onto the substrate 1 within the display panel 100 may intersect with the orthographic projection of the third sub-signal line Vref13 onto the substrate 1.

[0298] For example, please continue reading Figure 33The third sub-signal line Vref13 can extend along the second direction X, and the sixth sub-signal line Vref16 can extend along the third direction Y.

[0299] In the aforementioned display panel 100, the sixth sub-signal line Vref16 is connected to the third sub-signal line Vref13, so that both the sixth sub-signal line Vref16 and the third sub-signal line Vref13 are used to transmit the third sub-signal. Since the sixth sub-signal line Vref16 extends along the third direction Y, and the third sub-signal line Vref13 extends along the second direction X, and the second direction X and the third direction Y intersect, the third sub-signal line Vref13 extending along the second direction X and the sixth sub-signal line Vref16 extending along the third direction Y can jointly form a mesh structure, which is beneficial to reducing the loss of the third sub-signal during transmission, and thus beneficial to reducing the voltage drop difference between the third sub-signals in different areas within the display panel 100, thereby improving the display effect of the display panel 100.

[0300] For example, please continue reading Figure 30 In the case where the display panel 100 includes a plurality of pixel circuits 20 and the plurality of pixel circuits 20 are arranged along the extension direction of the first sub-signal line Vref11 (i.e., the second direction X), in the orthogonal projection onto the substrate 1, the sixth sub-signal line Vref16 may be located between two adjacent pixel circuits 20.

[0301] For example, please continue reading Figure 32 When the first reference voltage signal line Vref1 also includes a fourth sub-signal line Vref14 and a fifth sub-signal line Vref15, the fourth sub-signal line Vref14, the fifth sub-signal line Vref15 and the sixth sub-signal line Vref16 can be arranged on the same layer, and the fourth sub-signal line Vref14 can be approximately parallel to the fifth sub-signal line Vref15 and the sixth sub-signal line Vref16.

[0302] It should be noted that the statement "the fourth sub-signal line Vref14 can be roughly parallel to the fifth sub-signal line Vref15 and the sixth sub-signal line Vref16" means that the extension directions of the fourth sub-signal line Vref14, the fifth sub-signal line Vref15, and the sixth sub-signal line Vref16 are basically the same. There may be slight angular deviations or local minor displacements due to manufacturing process errors or wiring space limitations, but there are no obvious intersections or large directional deviations.

[0303] Please continue reading. Figure 32 The fourth sub-signal line Vref14, the fifth sub-signal line Vref15, and the sixth sub-signal line Vref16 can be arranged at intervals along the second direction X.

[0304] For example, please continue reading Figure 32 The fourth sub-signal line Vref14, the sixth sub-signal line Vref16, and the fifth sub-signal line Vref15 can be arranged sequentially at intervals along the second direction X.

[0305] For example, please continue reading Figure 30 In the case where the display panel 100 includes a plurality of pixel circuits 20, the plurality of pixel circuits 20 are arranged along the second direction X, and the plurality of pixel circuits 20 include a plurality of pixel circuit groups 20a, in the orthographic projection onto the substrate 1 within the display panel 100, the pixel circuit group 20a may be located between adjacent fourth sub-signal line Vref14 and sixth sub-signal line Vref16, and between adjacent sixth sub-signal line Vref16 and fifth sub-signal line Vref15.

[0306] For example, the material of the sixth sub-signal line Vref16 may include titanium (Ti) and aluminum (Al), etc.

[0307] The sub-pixels S (e.g., pixel circuits 20 and light-emitting devices 30 within sub-pixels S), first voltage signal line V1, second voltage signal line V2, data signal line Data, first initialization signal line Vinit1, second initialization signal line Vinit2, first reference voltage signal line Vref1, second reference voltage signal line Vref2, first scan signal line Gate, second scan signal line Az, first control signal line EM1, second control signal line EM2, first reset control signal line R1, and second reset control signal line R2, etc., within the display panel 100 can be disposed within the film layer structure of the display panel 100. The film layer structure of the display panel 100 will be described in detail below.

[0308] In some embodiments, such as Figure 34 As shown, Figure 34 This is a cross-sectional view of a partial area of ​​a display panel 100 according to some embodiments. When the display panel 100 includes a substrate 1, the display panel 100 may further include a pixel driving layer 2 and a light-emitting device layer 3, and the substrate 1, the pixel driving layer 2 and the light-emitting device layer 3 may be stacked sequentially along a first direction Z.

[0309] For example, please continue reading Figure 34 and combined Figure 5 In the case where the sub-pixel S in the display panel 100 includes the pixel circuit 20, the pixel circuit 20 may be located in the pixel driving layer 2.

[0310] For example, please continue reading Figure 34 and combined Figure 7The first voltage signal line V1, the second voltage signal line V2, the data signal line Data, the first initialization signal line Vinit1, the second initialization signal line Vinit2, the first reference voltage signal line Vref1, the second reference voltage signal line Vref2, the first scan signal line Gate, the second scan signal line Az, the first control signal line EM1, the second control signal line EM2, the first reset control signal line R1, and the second reset control signal line R2, etc., within the display panel 100 can be located within the pixel driving layer 2.

[0311] For example, please continue reading Figure 34 and combined Figure 5 In the case where the sub-pixel S in the display panel 100 includes the light-emitting device 30, the light-emitting device 30 may be located in the light-emitting device layer 3.

[0312] For example, please continue reading Figure 34 The display panel 100 may also include an encapsulation layer 4. The encapsulation layer 4 is located on the side of the light-emitting device layer 3 away from the substrate 1. The encapsulation layer 4 can be used to encapsulate the light-emitting device layer 3, thereby protecting the light-emitting device layer 3 from corrosion caused by external water and oxygen.

[0313] For example, encapsulation layer 4 may include an inorganic encapsulation layer and an organic encapsulation layer. The inorganic encapsulation layer is made of inorganic materials and can be used to block water and oxygen. The organic encapsulation layer is made of organic materials and can serve to flatten interfaces, cover defects, and relieve stress.

[0314] The structure of the light-emitting device layer 3 described above will be explained in detail below.

[0315] In some embodiments, please continue reading Figure 34 and combined Figure 35 , Figure 35 This is a plan view of a partial region of the first electrode layer 31 and the pixel definition layer PDL within the light-emitting device layer 3 according to some embodiments. The light-emitting device layer 3 may include the first electrode layer 31, the pixel definition layer PDL, the light-emitting functional layer 33, and the second electrode layer 32. The pixel definition layer PDL is located on the side of the first electrode layer 31 away from the substrate 1 within the display panel 100. The second electrode layer 32 is located on the side of the pixel definition layer PDL away from the substrate 1, and on the side of the light-emitting functional layer 33 away from the substrate 1.

[0316] Please continue reading. Figure 35 The first electrode layer 31 may include the first electrode 311 within the light-emitting device 30.

[0317] Please continue reading. Figure 34 and Figure 35The pixel definition layer (PDL) may include a pixel opening K. The orthographic projection of the pixel opening K onto the substrate 1 and the orthographic projection of the first electrode 311 within the light-emitting device 30 onto the substrate 1 at least partially coincide.

[0318] Please continue reading. Figure 34 The light-emitting functional layer 33 may include a light-emitting portion 331 within the light-emitting device 30. The light-emitting portion 331 may be located within the pixel opening K and connected to the first electrode 311 and the second electrode 321 within the light-emitting device 30, respectively.

[0319] Please continue reading. Figure 34 The second electrode layer 32 may include the second electrode 321 within the light-emitting device 30.

[0320] For example, please continue reading Figure 35 The second voltage signal line V2 within the display panel 100 may include a fourth sub-voltage signal line V22, which extends along the second direction X. The fourth sub-voltage signal line V22 may be located within the first electrode layer 31.

[0321] The structure of the pixel driving layer 2 described above will be explained in detail below.

[0322] In some embodiments, such as Figure 36 and Figure 37 As shown, and in combination Figure 34 , Figure 36 This is a plan view of a local region of pixel driving layer 2 according to some embodiments. Figure 37 This is a plan view of a partial region of the light-shielding layer 27 within the pixel driving layer 2 according to some embodiments. The pixel driving layer 2 may include the light-shielding layer 27. The light-shielding layer 27 is located on one side of the substrate 1 within the display panel 100 along the first direction Z.

[0323] In some embodiments, please continue reading Figure 8 The pixel driving layer 2 within the display panel 100 may include a first active layer 26.

[0324] For example, such as Figure 38 As shown, and in combination Figure 34 and Figure 36 , Figure 38 This is a plan view of a portion of the substrate 1, the light-shielding layer 27, and the first active layer 26 within the pixel driving layer 2, according to some embodiments. In the case where the pixel driving layer 2 within the display panel 100 further includes a light-shielding layer 27, and the light-shielding layer 27 is located on one side of the substrate 1 within the display panel 100 along the first direction Z, the first active layer 26 may be located on the side of the light-shielding layer 27 away from the substrate 1.

[0325] For example, please continue reading Figure 8When the pixel circuit 20 in the sub-pixel S includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10, the first active pattern T11 in the first transistor T1, the second active pattern T21 in the second transistor T2, the third active pattern T31 in the third transistor T3, the fourth active pattern T41 in the fourth transistor T4, the fifth active pattern T51 in the fifth transistor T5, the sixth active pattern T61 in the sixth transistor T6, the seventh active pattern T71 in the seventh transistor T7, the eighth active pattern T81 in the eighth transistor T8, the ninth active pattern T91 in the ninth transistor T9, and the tenth active pattern T101 in the tenth transistor T10 can all be located in the first active layer 26.

[0326] In some embodiments, please continue reading Figure 9 The pixel driving layer 2 within the display panel 100 may include a fifth conductive layer 25.

[0327] For example, please continue reading Figure 10 In the case where the pixel driving layer 2 in the display panel 100 also includes a first active layer 26, the fifth conductive layer 25 may be located on the side of the first active layer 26 away from the substrate 1 in the display panel 100.

[0328] For example, please continue reading Figure 9 and combined Figure 7 In the case that the pixel circuit 20 in the sub-pixel S includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10, the first gate T12 in the first transistor T1, the second gate T22 in the second transistor T2, the third gate T32 in the third transistor T3, the fourth gate T42 in the fourth transistor T4, the fifth gate T52 in the fifth transistor T5, the sixth gate T62 in the sixth transistor T6, the seventh gate T72 in the seventh transistor T7, the eighth gate T82 in the eighth transistor T8, the ninth gate T92 in the ninth transistor T9, and the tenth gate T102 in the tenth transistor T10 can all be located in the fifth conductive layer 25.

[0329] For example, please continue reading Figure 9 and combined Figure 7 In the case where the pixel circuit 20 in the sub-pixel S includes a first capacitor C1, the first plate C11 in the first capacitor C1 can be located in the fifth conductive layer 25.

[0330] For example, please continue reading Figure 9 The second initialization signal line Vinit2 within the display panel 100 may include a third sub-initialization signal line Vinit21, which extends along the second direction X. The third sub-initialization signal line Vinit21 may be located within the fifth conductive layer 25.

[0331] In some embodiments, please continue reading Figure 19 and combined Figure 34 The pixel driving layer 2 within the display panel 100 may include a first conductive layer 21. Along a direction perpendicular to the substrate 1 (i.e., the first direction Z), the first conductive layer 21 is located on one side of the substrate 1 within the display panel 100.

[0332] For example, please continue reading Figure 36 and combined Figure 34 In the case where the pixel driving layer 2 in the display panel 100 also includes a fifth conductive layer 25, the first conductive layer 21 may be located on the side of the fifth conductive layer 25 away from the substrate 1.

[0333] For example, please continue reading Figure 19 When the first reference voltage signal line Vref1 within the display panel 100 includes a first sub-signal line Vref11, the first sub-signal line Vref11 may be located within the first conductive layer 21. That is, the first conductive layer 21 may include the first sub-signal line Vref11.

[0334] For example, please continue reading Figure 19 The second reference voltage signal line Vref2 within the display panel 100 may include a first sub-reference voltage signal line Vref21, which extends along a second direction X. The first sub-reference voltage signal line Vref21 may be located within the first conductive layer 21.

[0335] For example, please continue reading Figure 19 and combined Figure 7 In the case where the pixel circuit 20 within the sub-pixel S includes a first capacitor C1, the second plate C12 within the first capacitor C1 can be located within the first conductive layer 21.

[0336] For example, please continue reading Figure 19 and combined Figure 7 In the case where the pixel circuit 20 in the sub-pixel S includes a second capacitor C2, the third plate C21 in the second capacitor C2 can be located in the first conductive layer 21.

[0337] In some embodiments, please continue reading Figure 20 and combined Figure 34 The pixel driving layer 2 within the display panel 100 may include a second conductive layer 22. The second conductive layer 22 is located on one side of the substrate 1 within the display panel 100 along the first direction Z.

[0338] For example, please continue reading Figure 36 and combined Figure 34 In the case where the pixel driving layer 2 in the display panel 100 also includes a first conductive layer 21, the second conductive layer 22 may be located on the side of the first conductive layer 21 away from the substrate 1.

[0339] For example, please continue reading Figure 20 When the first reference voltage signal line Vref1 within the display panel 100 includes a second sub-signal line Vref12, the second sub-signal line Vref12 may be located within the second conductive layer 22. That is, the second conductive layer 22 may include the second sub-signal line Vref12.

[0340] For example, please continue reading Figure 20 and combined Figure 7 In the case where the pixel circuit 20 in the sub-pixel S includes a second capacitor C2, the fourth plate C22 in the second capacitor C2 can be located in the second conductive layer 22.

[0341] In some embodiments, please continue reading Figure 24 and combined Figure 34 The pixel driving layer 2 within the display panel 100 may include a third conductive layer 23. The third conductive layer 23 is located on one side of the substrate 1 within the display panel 100 along the first direction Z.

[0342] For example, please continue reading Figure 36 and combined Figure 34 The pixel driving layer 2 in the display panel 100 also includes a first conductive layer 21 and a second conductive layer 22. When the second conductive layer 22 is located on the side of the first conductive layer 21 away from the substrate 1, the third conductive layer 23 may be located on the side of the second conductive layer 22 away from the first conductive layer 21.

[0343] For example, please continue reading Figure 24 When the first reference voltage signal line Vref1 within the display panel 100 includes a third sub-signal line Vref13, the third sub-signal line Vref13 may be located within the third conductive layer 23. That is, the third conductive layer 23 may include the third sub-signal line Vref13.

[0344] For example, please continue reading Figure 24The first initialization signal line Vinit1 within the display panel 100 may include a first sub-initialization signal line Vinit11, which extends along the second direction X. The first sub-initialization signal line Vinit11 may be located within the third conductive layer 23.

[0345] For example, please continue reading Figure 24 The first reset control signal line R1 within the display panel 100 can be located within the third conductive layer 23. The first reset control signal line R1 can extend along the second direction X.

[0346] For example, please continue reading Figure 24 The second scan signal line Az within the display panel 100 can be located within the third conductive layer 23. The second scan signal line Az can extend along the second direction X.

[0347] For example, please continue reading Figure 24 The first voltage signal line V1 within the display panel 100 may include a first sub-voltage signal line V11, which extends along the second direction X. The first sub-voltage signal line V11 may be located within the third conductive layer 23.

[0348] For example, please continue reading Figure 24 The second control signal line EM2 within the display panel 100 can be located within the third conductive layer 23. The second control signal line EM2 can extend along the second direction X.

[0349] For example, please continue reading Figure 24 The first scan signal line Gate within the display panel 100 may be located within the third conductive layer 23. The first scan signal line Gate may extend along the second direction X.

[0350] For example, please continue reading Figure 24 The first control signal line EM1 within the display panel 100 may be located within the third conductive layer 23. The first control signal line EM1 may extend along the second direction X.

[0351] For example, please continue reading Figure 24 The second reset control signal line R2 within the display panel 100 can be located within the third conductive layer 23. The second reset control signal line R2 can extend along the second direction X.

[0352] In some embodiments, please continue reading Figure 32 The pixel driving layer 2 within the display panel 100 may include a fourth conductive layer 24.

[0353] For example, please continue reading Figure 36 and combined Figure 34In the case where the pixel driving layer 2 in the display panel 100 also includes a third conductive layer 23, the fourth conductive layer 24 may be located on the side of the third conductive layer 23 away from the substrate 1 in the display panel 100.

[0354] For example, please continue reading Figure 32 In the case where the first reference voltage signal line Vref1 in the display panel 100 includes the fourth sub-signal line Vref14, the fourth sub-signal line Vref14 may be located in the fourth conductive layer 24.

[0355] For example, please continue reading Figure 32 In the case where the first reference voltage signal line Vref1 in the display panel 100 includes the fifth sub-signal line Vref15, the fifth sub-signal line Vref15 may be located in the fourth conductive layer 24.

[0356] For example, please continue reading Figure 32 In the case where the first reference voltage signal line Vref1 in the display panel 100 includes the sixth sub-signal line Vref16, the sixth sub-signal line Vref16 may be located in the fourth conductive layer 24.

[0357] For example, please continue reading Figure 32 and combined Figure 2 In the case where the multiple sub-pixels S in the display panel 100 include a first color sub-pixel S1, the data signal line Data in the display panel 100 may include a first data signal line Data1, and the first data signal line Data1 is connected to the first color sub-pixel S1.

[0358] The first data signal line Data1 can be located within the fourth conductive layer 24. The first data signal line Data1 can extend along the third direction Y.

[0359] For example, please continue reading Figure 32 and combined Figure 2 In the case where the multiple sub-pixels S in the display panel 100 include the second color sub-pixel S2, the data signal line Data in the display panel 100 may include the second data signal line Data2, and the second data signal line Data2 is connected to the second color sub-pixel S2.

[0360] The second data signal line Data2 can be located within the fourth conductive layer 24. The second data signal line Data2 can extend along the third direction Y.

[0361] For example, please continue reading Figure 32 and combined Figure 2In the case where the multiple sub-pixels S in the display panel 100 include a third color sub-pixel S3, the data signal line Data in the display panel 100 may include a third data signal line Data3, and the third data signal line Data3 is connected to the third color sub-pixel S3.

[0362] The third data signal line Data3 can be located within the fourth conductive layer 24. The third data signal line Data3 can extend along the third direction Y.

[0363] For example, please continue reading Figure 32 The first voltage signal line V1 within the display panel 100 may include a second sub-voltage signal line V12, which extends in the third direction Y. The second sub-voltage signal line V12 may be located within the fourth conductive layer 24.

[0364] Please continue reading. Figure 33 When the first voltage signal line V1 further includes a first sub-voltage signal line V11, and the first sub-voltage signal line V11 extends along the second direction X, the second sub-voltage signal line V12 can be connected to the first sub-voltage signal line V11.

[0365] For example, please continue reading Figure 32 The second voltage signal line V2 within the display panel 100 may include a third sub-voltage signal line V21, which extends in the third direction Y. The third sub-voltage signal line V21 may be located within the fourth conductive layer 24.

[0366] Please continue reading. Figure 32 and Figure 35 When the second voltage signal line V2 also includes a fourth sub-voltage signal line V22, and the fourth sub-voltage signal line V22 extends along the second direction X, the third sub-voltage signal line V21 can be connected to the fourth sub-voltage signal line V22. The third sub-voltage signal line V21 and the fourth sub-voltage signal line V22 can jointly form a mesh structure, which is beneficial to reducing the loss of the second voltage signal during transmission.

[0367] For example, please continue reading Figure 32 The second initialization signal line Vinit2 within the display panel 100 may include a fourth sub-initialization signal line Vinit22, which extends along a third direction Y. The fourth sub-initialization signal line Vinit22 may be located within the fourth conductive layer 24.

[0368] Please continue reading. Figure 9 and Figure 32In the case that the second initialization signal line Vinit2 also includes a third sub-initialization signal line Vinit21, and the third sub-initialization signal line Vinit21 extends along the second direction X, the fourth sub-initialization signal line Vinit22 can be connected to the third sub-initialization signal line Vinit21.

[0369] For example, please continue reading Figure 32 The first initialization signal line Vinit1 within the display panel 100 may include a second sub-initialization signal line Vinit12, which extends along a third direction Y. The second sub-initialization signal line Vinit12 may be located within the fourth conductive layer 24.

[0370] Please continue reading. Figure 33 In the case that the first initialization signal line Vinit1 also includes a first sub-initialization signal line Vinit11, and the first sub-initialization signal line Vinit11 extends along the second direction X, the second sub-initialization signal line Vinit12 can be connected to the first sub-initialization signal line Vinit11.

[0371] For example, please continue reading Figure 32 The second reference voltage signal line Vref2 within the display panel 100 may include a second sub-reference voltage signal line Vref22, which extends along a third direction Y. The second sub-reference voltage signal line Vref22 may be located within the fourth conductive layer 24.

[0372] Please continue reading. Figure 29 When the second reference voltage signal line Vref2 also includes a first sub-reference voltage signal line Vref21, and the first sub-reference voltage signal line Vref21 extends along the second direction X, the second sub-reference voltage signal line Vref22 can be connected to the first sub-reference voltage signal line Vref21.

[0373] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, Includes a substrate and multiple sub-pixels; Along a direction perpendicular to the substrate, the sub-pixel is located on one side of the substrate; The sub-pixel includes a pixel circuit, the pixel circuit comprising: The driving sub-circuit is connected to the first voltage signal line and the second voltage signal line respectively; A coupling sub-circuit, connected to the driving sub-circuit; The data writing sub-circuit is connected to the first scan signal line, the data signal line, and the coupling sub-circuit, respectively. The first control sub-circuit is connected to the first control signal line, the first reference voltage signal line and the coupling sub-circuit, respectively. The plurality of sub-pixels include a first color sub-pixel and a second color sub-pixel; the first reference voltage signal line includes a first sub-signal line and a second sub-signal line; the first sub-signal line is connected to a first control sub-circuit of the pixel circuit in the first color sub-pixel, and the second sub-signal line is connected to a first control sub-circuit of the pixel circuit in the second color sub-pixel.

2. The display panel according to claim 1, characterized in that, The first sub-signal line and the second sub-signal line are parallel to the substrate, and the first sub-signal line is substantially parallel to the second sub-signal line.

3. The display panel according to claim 1, characterized in that, The display panel also includes: A first conductive layer; the first conductive layer is located on one side of the substrate along a direction perpendicular to the substrate; the first conductive layer includes the first sub-signal line; A second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes a second sub-signal line; the orthographic projection of the first sub-signal line onto the substrate and the orthographic projection of the second sub-signal line onto the substrate overlap.

4. The display panel according to claim 3, characterized in that, The first control sub-circuit includes a first transistor, the first transistor including a first active pattern; the first active pattern is connected to the first reference voltage signal line; The orthographic projection of the first active pattern onto the substrate and the orthographic projection of the first sub-signal line onto the substrate overlap; And / or, The orthographic projection of the first active pattern onto the substrate and the orthographic projection of the second sub-signal line onto the substrate overlap.

5. The display panel according to claim 1, characterized in that, The plurality of sub-pixels also includes a third color sub-pixel; The first reference voltage signal line further includes a third sub-signal line, which is connected to the first control sub-circuit of the pixel circuit within the third color sub-pixel.

6. The display panel according to claim 5, characterized in that, The first sub-signal line, the second sub-signal line, and the third sub-signal line are parallel to the substrate, and the first sub-signal line is substantially parallel to the second sub-signal line and the third sub-signal line.

7. The display panel according to claim 5, characterized in that, The display panel also includes: A first conductive layer; the first conductive layer is located on one side of the substrate along a direction perpendicular to the substrate; the first conductive layer includes the first sub-signal line; A second conductive layer is located on the side of the first conductive layer away from the substrate; the second conductive layer includes the second sub-signal line; A third conductive layer is located on the side of the second conductive layer away from the first conductive layer; the third conductive layer includes the third sub-signal line; the orthogonal projection of the third sub-signal line onto the substrate is located on the side of the orthogonal projection of the first sub-signal line onto the substrate.

8. The display panel according to claim 5, characterized in that, The first control sub-circuit includes a first transistor, the first transistor including a first active pattern; the first active pattern is connected to the first reference voltage signal line; The orthographic projection of the first active pattern onto the substrate and the orthographic projection of the third sub-signal line onto the substrate overlap.

9. The display panel according to claim 8, characterized in that, The orthographic projection of the first sub-signal line onto the substrate overlaps with the orthographic projection of the first active pattern onto the substrate; The display panel further includes a first connecting portion, and the third sub-signal line is connected to the first active pattern through the first connecting portion; the orthographic projection of the first connecting portion onto the substrate and the orthographic projection of the first sub-signal line onto the substrate overlap.

10. The display panel according to any one of claims 1-9, characterized in that, The first reference voltage signal line further includes: A fourth sub-signal line is connected to the first sub-signal line; the orthographic projection of the fourth sub-signal line onto the substrate intersects with the orthographic projection of the first sub-signal line onto the substrate. The fifth sub-signal line is connected to the second sub-signal line; the orthographic projection of the fifth sub-signal line onto the substrate intersects with the orthographic projection of the second sub-signal line onto the substrate.

11. The display panel according to claim 10, characterized in that, The fourth sub-signal line and the fifth sub-signal line are arranged on the same layer; The fourth sub-signal line is approximately parallel to the fifth sub-signal line.

12. The display panel according to claim 11, characterized in that, The fourth sub-signal line and the fifth sub-signal line are arranged alternately; The display panel includes a plurality of pixel circuits, which are arranged along the extension direction of the first sub-signal line; the plurality of pixel circuits include a plurality of pixel circuit groups, which include pixel circuits in the first color sub-pixel and pixel circuits in the second color sub-pixel. In the orthographic projection onto the substrate, the fourth sub-signal line is located between two adjacent pixel circuits, the fifth sub-signal line is located between two adjacent pixel circuits, and the pixel circuit group is located between the adjacent fourth sub-signal line and the fifth sub-signal line.

13. The display panel according to any one of claims 5-9, characterized in that, The first reference voltage signal line further includes a sixth sub-signal line, which is connected to the third sub-signal line; the orthographic projection of the sixth sub-signal line onto the substrate intersects with the orthographic projection of the third sub-signal line onto the substrate.

14. The display panel according to claim 13, characterized in that, The display panel also includes a fourth sub-signal line and a fifth sub-signal line; The fourth sub-signal line, the fifth sub-signal line, and the sixth sub-signal line are arranged on the same layer, and the fourth sub-signal line is approximately parallel to the fifth sub-signal line and the sixth sub-signal line.

15. The display panel according to claim 13, characterized in that, The display panel further includes a fourth sub-signal line and a fifth sub-signal line, wherein the fourth sub-signal line is substantially parallel to the fifth sub-signal line and the sixth sub-signal line; The display panel includes a plurality of pixel circuits, which are arranged along the extension direction of the first sub-signal line; the plurality of pixel circuits include a plurality of pixel circuit groups, which include pixel circuits in the first color sub-pixel, pixel circuits in the second color sub-pixel, and pixel circuits in the third color sub-pixel. In a projection onto the substrate, the sixth sub-signal line is located between two adjacent pixel circuits, the pixel circuit group is located between adjacent fourth and sixth sub-signal lines, and between adjacent sixth and fifth sub-signal lines.

16. A display device, characterized in that, include: The display panel as described in any one of claims 1-15; The driver chip is connected to the display panel.

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