Methods and apparatus for system clock control
The control state machine in the clock controller circuit addresses voltage droops and current fluctuations by coordinating droop mitigation and DVFS operations, enhancing system reliability and reducing power consumption in integrated circuits.
Patent Information
- Application Number
- GB2024003983
- Authority / Receiving Office
- GB · GB
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-24
- Filing Date
- 2024-03-20
- Publication Date
- 2025-04-30
- Estimated Expiration
- 2044-03-20
AI Technical Summary
Existing systems face challenges in managing voltage droops and current fluctuations in integrated circuits, leading to performance issues, data corruption, increased power consumption, and potential device failure, particularly in safety-critical applications like automotive and avionics systems, while balancing power consumption and performance requirements.
A control state machine in a clock controller circuit that manages droop mitigation, dynamic voltage and frequency scaling (DVFS), and over-current situations through a centralized control mechanism involving state machines and a four-state handshaking protocol to coordinate operations among droop, DVFS, and over-current state machines.
Effectively mitigates voltage droops and manages current fluctuations, ensuring reliable operation and reducing power consumption, thereby preventing performance issues and device failures in complex systems.