Function-Based Activation of Memory Hierarchies
The use of a 3D compute-in-memory architecture addresses the inefficiencies in large deep learning models by performing computations directly in-memory, reducing the need for DRAM and enhancing inference speed and energy efficiency.
Patent Information
- Application Number
- JP2025514236
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-09-13
- Filing Date
- 2023-08-08
- Publication Date
- 2025-10-09
AI Technical Summary
Current deep learning architectures with large numbers of parameters face challenges in training and inference due to high computational costs and the need for large amounts of dynamic random access memory (DRAM), preventing fast and energy-efficient operations.
Implementing a neural network model system with a hierarchy of compute-in-memory structures using a 3D memory architecture, such as resistive memory or 3D NAND flash, to perform computations in-memory, thereby eliminating the need for constant weight passing between memory and CPU/GPU and reducing DRAM requirements.
Enables fast and energy-efficient inference for models with billions of parameters by leveraging 3D compute-in-memory systems, which store weights within the memory architecture and perform computations directly in-memory, thus enhancing computational speed and throughput.