Optimizing Reconfigurable Hardware Using Data Sampling

By generating predicted computer instructions based on estimated data values and executing alternative instructions upon misprediction, the solution addresses the challenge of pipeline mispredictions, enhancing processing performance and efficiency.

JP7763256B2Active Publication Date: 2025-10-31NEXTSILICON LTD
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Patent Information

Application Number
JP2023541978
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-01-11
Filing Date
2022-01-11
Publication Date
2025-10-31
Estimated Expiration
2042-01-11

AI Technical Summary

Technical Problem

Existing processing architectures face challenges in predicting the execution order of computer instructions due to branch instructions, leading to pipeline mispredictions and reduced performance, as they often rely on limited branch prediction methods that increase latency and decrease throughput.

Method used

The proposed solution involves generating a predicted set of computer instructions based on estimated data values, allowing for the execution of alternative instructions when mispredictions occur, thereby reducing pipeline flushes and optimizing performance.

Benefits of technology

This approach improves processing performance by reducing pipeline flushes and enhancing throughput and latency by accurately predicting the execution order of instructions, even in the presence of branch instructions.

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Abstract

1. A computing device comprising: a processing circuit configured to calculate a result of executing a set of computer instructions including a set of data variables, the calculation including: identifying an initial state of the processing circuit; executing an expected set of computer instructions generated based on the set of computer instructions and an estimated data value, the estimated data value being a value of one of the set of data variables expected to be calculated by executing the set of computer instructions and calculated using at least one program data value; and upon identification of a prediction failure during execution of the expected set of computer instructions in which the data variable does not equal the estimated data value, restoring the initial state of the processing circuit; and executing an alternative set of computer instructions generated based on the set of computer instructions and the at least one estimated data value.
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