Semiconductor package including bump

The semiconductor package addresses connectivity and miniaturization challenges through a wiring structure with optimized electrode segments and bump configurations, enhancing reliability and performance.

TW202633470APending Publication Date: 2026-08-01SK HYNIX INC
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Patent Information

Application Number
TW114141646
Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-19
Filing Date
2025-10-28
Publication Date
2026-08-01

AI Technical Summary

Technical Problem

Existing semiconductor packages face challenges in achieving reliable connectivity and efficient miniaturization due to limitations in redistribution layer and bump technologies, which affect the performance and reliability of semiconductor devices.

Method used

The semiconductor package includes a wiring structure with a first electrode having segments of varying widths, a first bump with a conductive post and solder layer, and a semiconductor wafer configuration that enhances electrical connectivity and reliability by optimizing the dimensions and placement of conductive elements.

Benefits of technology

This configuration improves the reliability and efficiency of semiconductor packages by ensuring stable electrical connections and enhanced miniaturization, thereby supporting the performance of semiconductor devices.

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Abstract

A semiconductor package includes a wiring structure, a first bump, and a semiconductor chip. The wiring structure includes a first electrode and has a first surface and a second surface that faces away from the first surface. The second surface of the wiring structure includes a recessed area that overlaps the first electrode. The first bump includes a first conductive pillar on the first surface of the wiring structure and a first solder layer on the first conductive pillar. The first bump contacts the first electrode. The first electrode includes a first section and a second section. The first section of the first electrode is disposed between the first surface of the wiring structure and the second surface of the wiring structure. The second section of the first electrode has a lower surface that is included in the first surface of the wiring structure. The horizontal width of the first conductive pillar is less than the horizontal width of the first electrode. A semiconductor chip is disposed above the second surface of the wiring structure.
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