Reconfigurable OFDM Baseband Processor

Abstract

20 25 28 35 74 18 D ec 2 02 5 A B S T R A C T 2 0 2 5 2 8 3 5 7 4 1 8 D e c 2 0 2 5 1 / 2 C o n tr o l p a th R ec o n fi g u ra b le s ta te m ac h in e R eg is te r In te rr u p t co n tr o l m o d u le In te rr u p t si g n al T X d at a R X d at a R eg is te r S ta te m a ch in e A cc el er at io n c o re D M A S am p le p o in t p ro ce ss in g u n it R eg is te r S ta te m a ch in e A cc el er at io n c o re D M A S y m b o l p ro ce ss in g u n it R eg is te r S ta te m a ch in e A cc el er at io n c o re D M A B lo ck p ro ce ss in g u n it D M A D at a p ac k e t m a n ag em en t m o d u le M ai n b u s in te rf ac e D at a tr an sm is si o n b u s D a ta p a th S h ar ed m em o ry u n it N b an k s O F D M b a se b a n d p ro ce ss o r C o n n ec te d t o a r eg is te r co n fi g u ra ti o n b u s a n d a d at a tr a n sm is si o n b u s S la v e b u s in te rf ac e R eg is te r co n fi g u ra ti o n b u s F IG . 1 Interrupt Control Interrupt signal control path Reconfigurable state machine Register module Register configuration bus State State State Main bus TX data Register machine Register Register DMA machine machine interface Data packet Acceleration core Acceleration core Acceleration core management RX data DMA Sample point DMA Symbol Block module 1 / 2 DMA processing processing processing unit unit unit Data transmission bus Data path Shared memory unit Connected to a register configuration bus and a Slave bus N banks OFDM baseband processor data transmission bus interface FIG. 1 20 25 28 35 74 18 D ec 2 02 5 2 0 2 5 2 8 3 5 7 4 1 8 D e c 2 0 2 5 Reconfigurable state machine Register configuration bus V T X d a t a m a c h i n e m a c h i n e Acceleration coreAcceleration core R X d a t a S a m p l e p o i n t p r o c e s s i n g p r o c e s s i n g Data transmission bus Shared memory unit N b a n k sO F D M b a s e b a n d p r o c e s s o r

Description

2025283574   18 Dec 2025 TECHNICAL FIELD

[0001] The present disclosure relates to a baseband processor, particularly to a reconfigurable OFDM baseband processor. BACKGROUND

[0002] This part provides background information related to the present disclosure and is not the conventional technology.

[0003] In the modern communication system, the data transmission efficiency, signal processing ability and anti-interference performance of the communication system have been significantly improved with the rapid development of wireless communication technology, especially the wide application of Orthogonal Frequency Division Multiplexing (OFDM) technology. The OFDM divides data into multiple subcarriers and transmits the multiple subcarriers in parallel to make full use of spectrum resources, and obtain strong antimultipath interference capabilities. Therefore, the OFDM has been widely applied in the 4G, 5G mobile communications, Wi-Fi, wireless local area networks and other fields.

[0004] However, as continued update and iteration of communication standards, the communication protocols and algorithms become more and more complex, and existing processor architectures have some shortcomings in facing these challenges:

[0005] The instruction-based processors (such as CPU or DSP) are highly flexible and able to support multiple communication protocols through software programming. However, the processors are not optimized for specific signal processing and communication algorithms. Therefore, the performance of the processors cannot be maximized when the processors execute signal processing algorithms such as modulation or coding.

[0006] The Application Specific Integrated Circuit (ASIC) processors typically provide extremely energy efficiency and performance because the ASIC processors are customized for specific tasks and application scenarios. However, the ASIC is lack of flexibility. Once the design for the ASIC is completed, the hardware functions of the ASIC are fixed, and the ASIC is difficult to adapt to the update of the future communication standard. In order to support new standards or algorithms, a chip should be redesigned, which significantly increases development costs and time.

[0007] The Field Programmable Gate Array (FPGA) provides a solution between the CPU and the ASIC, and the FPGA has good flexibility and programmability, and is suitable for 2025283574   18 Dec 2025 supporting multiple communication standards. However, the FPGA has relatively high cost, especially in mass production, and the price / performance ratio of the FPGA is not ideal. In addition, the energy efficiency of the FPGA is not as good as that of the ASIC, and has higher power consumption, which faces the challenges in energy efficiency-sensitive applications.

[0008] To sum up, the existing communication processor architectures face many challenges in terms of flexibility, energy efficiency and the cost. Especially when dealing with highly similar communication algorithms such as the OFDM, the traditional processor architecture is difficult to meet all the requirements of high-performance, high-energy-efficiency and flexibility. Therefore, a low-cost, high-energy-efficiency, and high-flexibility processor architecture is urgent to be provided to cope with the rapidly evolutional communication standards and complex communication algorithm requirements.

[0009] It should be noted that the information disclosed in the above-described background part is only used for enhancing understanding of the background of the present disclosure, and thus may include information that does not constitute conventional technology known to those skilled in the art. SUMMARY

[0010] The technical problem to be solved by the present disclosure is to provide a reconfigurable OFDM baseband processor for the shortcomings in the conventional technology.

[0011] In order to solve the above technical problem, the present disclosure discloses a reconfigurable OFDM baseband processor, which includes a control path, a data path and a shared memory unit.

[0012] The control path is connected with an interrupt signal of a host CPU and receives interrupt control of the host CPU. The control path is also connected with a slave bus interface of the host CPU and receives state control of the host CPU.

[0013] The data path is connected with a main bus interface of the host CPU, and sends and receives original OFDM data in the host CPU. The data path converts an externally received OFDM time domain signal into original OFDM data and sends the original OFDM data to the host CPU, or receives original OFDM data sent by the host CPU and converts the original OFDM data into an OFDM time domain signal, and sends the OFDM time domain signal to the outside.

[0014] The data path is also connected with the slave bus interface of the host CPU, which is used by the host CPU to configure the data pat.

[0015] The shared memory unit is configured to provide storage space in a shared memory 2025283574   18 Dec 2025 manner to the data path.

[0016] Further, the data path includes a data packet management module which is connected with the main bus interface of the host CPU, and configured to transmit and receive the original OFDM data.

[0017] The data packet management module is connected with a data processing module, and the data processing module is configured to perform mutual conversion between the original OFDM data and the OFDM time domain signal.

[0018] The data path further includes a data transmission bus and a register configuration bus. The data processing module uses the shared memory unit through the data transmission bus, and the control path controls the data processing module through the register configuration bus.

[0019] Further, the data processing module is divided into three processing units according to an OFDM data processing process, which are a block processing unit, a symbol processing unit, and a sampling point processing unit.

[0020] The block processing unit is connected with the data packet management module, and is configured for transmitting and receiving the original OFDM data of the data packet management module, and performing mutual conversion between the original OFDM data and a data block.

[0021] The symbol processing unit is configured to perform mutual conversion between the data block and symbol data.

[0022] The sampling point processing unit is configured to perform mutual conversion between the symbol data and a sampling point signal.

[0023] The data interaction among the block processing unit, the symbol processing unit and the sampling point processing unit is performed through the data transmission bus and the shared memory unit.

[0024] Further, the block processing unit includes a block processing unit direct memory access (DMA) sub-module, a block processing unit register, a block processing unit state machine, a check unit and a codec unit.

[0025] The block processing unit DMA sub-module is configured to perform data interaction with the shared memory unit through the data transmission bus.

[0026] The block processing unit register is configured to configure the block processing unit through the register configuration bus.

[0027] The block processing unit state machine is configured to control an operation state of the block processing unit according to the control path. 2025283574   18 Dec 2025

[0028] The check unit is configured to check the integrity of the data.

[0029] The codec unit is configured to perform error correction encoding and decoding of data.

[0030] Further, the symbol processing unit configured to perform mutual conversion between the data block in the form of bit data and the symbol data in the form of carrier data includes a symbol processing unit DMA sub-module, a symbol processing unit register, a symbol processing unit state machine, a modulation demodulation sub-module, an interleaving submodule, and a fast Fourier transform FFT or inverse fast Fourier transform IFFT processing sub-module.

[0031] The symbol processing unit DMA sub-module is configured to perform data interaction with the shared memory unit through the data transmission bus.

[0032] The symbol processing unit register is configured to configure the symbol processing unit through the register configuration bus.

[0033] The symbol processing unit state machine is configured to control an operation state of the symbol processing unit according to the control path.

[0034] The modulation and demodulation sub-module is configured to map an encoded data block into symbol data by a modulator, or convert the symbol data into a data block by demodulation.

[0035] The interleaving sub-module is configured to perform an interleaving operation before or after modulation.

[0036] The fast FFT or IFFT processing sub-module is configured to implement the conversion of the signal between the frequency domain and the time domain.

[0037] Further, the sampling point processing unit includes a sampling point processing unit DMA sub-module, a sampling point processing unit register, a sampling point processing unit state machine, a signal interpolation and decimation sub-module, and a filtering and enhancement sub-module.

[0038] The sampling point processing unit DMA sub-module is configured to perform data interaction with the shared memory unit through the data transmission bus.

[0039] The sampling point processing unit register is configured to configure the sampling point processing unit through the register configuration bus.

[0040] The sampling point processing unit state machine is configured to control an operation state of the sampling point processing unit according to the control path.

[0041] The signal interpolation and decimation sub-module is configured to perform an interpolation and decimation operation according to sampling rates and channel conditions of different transmission channels. 2025283574   18 Dec 2025

[0042] A filtering and enhancement sub-module is configured to clear noise or interference in the data signal by a filter and performs a signal enhancement operation.

[0043] Further, the control path includes a reconfigurable state machine, a control path register and an interrupt control module.

[0044] The reconfigurable state machine is configured to control state machines in the block processing unit, the symbol processing unit and the sampling point processing unit.

[0045] The control path register is connected to the register configuration bus and is configured to control the processing unit or read a state of the processing unit through the register in the processing unit.

[0046] The interrupt control module is configured to deliver the interrupt signal to the host CPU to perform transaction level communication.

[0047] Further, the shared memory unit is divided into N independent data storage blocks according to the number of processing units in the data processing module.

[0048] Further, a two-phase reconfiguration strategy is used for configuration.

[0049] Further, the two-phase reconfiguration strategy includes: hardware generation and runtime configuration.

[0050] The hardware generation is to generate a hardware configuration according to a requirement and determine a maximum processing capacity of the OFDM baseband processor, which includes: when performing OFDM baseband processing, a set of FFT points to be supported, the maximum processing order, the maximum symbol length, the maximum windowing length, the maximum cyclic prefix length, the maximum interleaving depth, the maximum lookup table length, the maximum throughput of the processing unit and the size of the shared memory unit.

[0051] The runtime configuration is to adjust the OFDM baseband processor through a configuration of the register after the hardware generation is completed, which includes: when OFDM baseband processing is performed, the current number of FFT points, the order of the current filter chain and the corresponding coefficient, the current symbol length, the current windowing length and the corresponding coefficient, the current cyclic prefix length, the current interleaving depth, the current lookup table size and the contents thereof are included.

[0052] Beneficial effects are described below.

[0053] The present disclosure proposes a novel reconfigurable OFDM baseband processor architecture to provide sufficient flexibility while maintaining high energy efficiency, adapt to various communication protocols and standards, and reduce design and production costs. 2025283574   18 Dec 2025

[0054] In one aspect, flexibility is enhanced. In order to solve the problem of insufficient flexibility of the ASIC, the present disclosure adopts a reconfigurable architecture design, so that the processor can be configured to support existing and future communication standards. Through the collaborative configuration of hardware and software, the processor can quickly adapt to the update of communication protocol and reduce the cost and time of redesigning hardware.

[0055] In another aspect, energy efficiency is ensured. The processor architecture of the present disclosure optimizes the execution efficiency of the OFDM communication algorithm through a special signal processing acceleration unit, and maintains lower power consumption while realizing efficient parallel processing, thereby ensuring the overall energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The present disclosure is further illustrated below in conjunction with the accompanying drawings and the embodiments, and the advantages of the above and / or other aspects of the present disclosure will become apparent.

[0057] FIG. 1 is a schematic diagram of an overall architecture of the present disclosure.

[0058] FIG. 2 is an architectural schematic diagram of an embodiment. DETAILED DESCRIPTION

[0059] The general idea of the present disclosure is described as follows:

[0060] After the shortcomings of the CPU / DSP, ASIC and FPGA architectures in the conventional technology are analyzed, the present disclosure provides a different processing unit design classified by based on OFDM data structure characteristic, and combines a double-phase reconfiguration strategy to effectively solve the balance problem among flexibility, energy efficiency and cost. The traditional CPU / DSP has high flexibility but low energy efficiency, while the ASIC is efficient but poor flexibility, and the FPGA has high cost and insufficient energy efficiency. Specifically, the system architecture according to the present disclosure performs optimization processing on different data levels by dividing the sampling point processing unit, the symbol processing unit and the block processing unit, and ensures that the processor can flexibly adapt to multiple communication standards through the double-phase reconstruction strategy without large-scale hardware modification.

[0061] Therefore, the present disclosure not only significantly improves the flexibility of the system, but also ensures the signal processing efficiency and energy efficiency, and thus can 2025283574   18 Dec 2025 efficiently cope with the continued evolutional communication standards.

[0062] The specific technical solutions of the present disclosure are described as follows.

[0063] The overall architecture and unit division basis are described first.

[0064] The overall architecture is as shown by the architecture of the baseband processor shown in FIG. 1. The entire baseband communicates with a host CPU through a main bus interface, a slave bus interface and an interrupt signal. The main bus interface is configured for interacting with a data packet management module. The slave bus interface is connected to a register configuration bus and a data transmission bus, so that the CPU configures a register of each functional unit or read data in a shared memory unit, to configure or monitor the register and the data. In this system, the CPU can efficiently control and monitor various processing modules within the baseband processor.

[0065] The processor is composed of a number of functional units, which are configured for managing the various stages of OFDM processing data. According to the type of data processed, these functional units are divided into three categories: a sampling point processing unit, a symbol processing unit and a block processing unit. Each of the functional units is optimized for the specific buffer size and throughput thereof. In this way, the data is processed efficiently and performance at each stage of the processing chain is maximized.

[0066] Data exchange between the functional units is performed through the shared memory, which is divided into N independent banks. This design reduces a conflict in accessing the memory and ensures an efficient flow of a data flow within the system. The access to the shared memory unit is performed via a data transmission bus, and each functional unit is equipped with its own dedicated DMA subunit.

[0067] The control path is separate from the data path, and a control signal of each functional unit directly interacts with a finite state machine (FSM, that is, the reconfigurable state machine in FIG. 1) related to a data protocol of the current OFDM baseband processor. The FSM may be reconfigured by reloading specific control and status registers (CSRs), thereby enhancing the flexibility of the system for supporting different communication protocols.

[0068] The division basis of the sampling point processing unit, the symbol processing unit and the block processing unit is described below.

[0069] In an OFDM system, a series of levels of processing is performed on a data flow, including different processing steps from a sampling point to a symbol, and then to a physical block. Because the data characteristics and processing requirements of the levels are different, the system is divided into reasonable units in order to efficiently process all types of data in the data flow. A data structure in the OFDM system is analyzed below, which includes a structure 2025283574   18 Dec 2025 of a sampling point, a structure of a symbol and a structure of a block.

[0070] The OFDM symbol are typically processed through sampling points, and each symbol includes multiple sampling points. The sampling point is a representation of the symbol in the time domain, and are critical roles especially at the physical level. The processing on the sampling points usually includes interpolation, decimation and other operations, and has a high data rate, and requires high throughput.

[0071] The feature is that the number of sampling points is large and a data rate is extremely high, and the processor must have extremely high throughput and real-time processing capabilities. Processing at the sampling level is essential for high-speed data processing and signal conversion in the physical layer.

[0072] After the data block is encoded, the data is modulated into symbols. The OFDM symbols are signals transmitted over a period of time and represent modulated data. Each symbol contains many modulated subcarriers, which are interleaved, modulated (such as QAM, PSK) and other processed to improve transmission efficiency and signal robustness.

[0073] The feature is that the symbol-level data represents the transmitted physical signal unit. The processing to the symbols includes modulation, interleaving, FFT and other operations, and the data rate is moderate.

[0074] In an OFDM system, initial input data is processed in data blocks. Each block usually consists of a set of bits or bytes that are encoded (such as Turbo encoding, convolutional encoding etc.) to enhance the robustness of the data. The processing before transmitting the block-level data focuses on error correction coding and data packing.

[0075] The feature is that the amount of block-level data is large, complex coding and error correction algorithms is processed, and a data rate is low.

[0076] The unit function design is described below, including a sampling point processing unit, a symbol processing unit, a block processing unit, a control unit, and a shared memory unit.

[0077] The sampling point processing unit (i.e., the sampling point processor) is configured to process sampling point data after symbol processing, mainly concentrating on the data transmission part of the physical layer. Due to the high data rate, the sampling point processor is mainly configured to process and optimize a high-speed signal.

[0078] Signal interpolation and decimation are described. In order to ensure the transmission quality of the signal under different sampling rates and channel conditions, the sampling point processor performs interpolation and decimation, so that the signal can be converted in different frequency ranges to meet the requirements of the transmission channel.

[0079] Filtering and enhancement are described. The sampling point processor typically includes 2025283574   18 Dec 2025 a filter configured to clear noise or other interference in the signal. In addition, the filter may also perform signal enhancement, so as to ensure that the received signal maintains sufficient signal strength and quality for subsequent symbol demodulation and data recovery.

[0080] The symbol processing unit (i.e., the symbol processor) processes data which is packed and encoded by the block processor and converts the data into symbols for further modulation and transmission. The symbol processor plays the role of mapping bit data into carrier data in the data transmission link.

[0081] Modulation / Demodulation is described below. The symbol processor maps encoded bits to OFDM symbols (such as BPSK, QPSK, 16-QAM, etc.) through a modulator. At the receiving end, the symbol processor performs demodulation to convert the received symbols into a bitstream.

[0082] Interleaving is described below. The symbol processor performs an interleaving operation before or after modulation to ensure that adjacent symbols are scrambled during transmission, thereby improving anti-interference ability and preventing the consecutive symbols from being affected by burst errors.

[0083] The FFT / IFFT processing is described. In an OFDM system, the symbol processor performs conversion between the frequency domain and the time domain, and implement the modulation and demodulation of the signal by fast Fourier transform (FFT) or inverse fast Fourier transform (IFFT). The IFFT is used to convert a frequency domain signal into a time domain signal for transmission, and the FFT is used for demodulation at the receiving end.

[0084] The block processing unit (i.e., the block processor) is configured to process an input data block, and the main functions of the block processor include data verification, encoding and decoding. The block processor is the first layer of processing after the data enters the system, and the processing ensures that the data has strong anti-interference ability in subsequent transmission. Specifically, the block processor may include but is not limited to the following processing units.

[0085] A CRC check unit is configured to generate and attach a cyclic redundancy check (CRC) code for integrity check of data transmission. The receiving end can determine whether the data is correct by verifying the CRC.

[0086] The codec unit is configured to implement error correction coding (such as Turbo coding, convolutional coding, Reed-Solomon coding, etc.) to enhance the robustness of data. Therefore, even if a part of the data is interfered during transmission, the original data can be recovered through decoding.

[0087] The control unit is configured to perform scheduling and process management of the 2025283574   18 Dec 2025 entire system, for ensuring that all processing units operate synchronously on time. The control unit manages the transfer of a data flow, the start and stop of processing units, coordinates the efficient operation of all modules, and ensures the stability and reliability of the entire system.

[0088] The shared memory unit is configured to perform data exchange between various processing units, and provides efficient data storage and reading functions. The shared memory unit avoids possible bottlenecks in the process of data transfer, and ensures that data can be transferred from one processing unit to another processing unit quickly and accurately.

[0089] Two-phase reconfiguration strategy is described below.

[0090] In terms of reconfigurability, the present disclosure adopts a two-phase reconfigurable strategy to achieve a balance between hardware capability and operation flexibility of the system. The strategy mainly includes two phases: a hardware generation phase and a runtime configuration phase.

[0091] At the hardware generation phase, the system generates a hardware configuration according to the target application requirements and determines the maximum processing capacity of the accelerator, and the configuration includes, but is not limited to: a set of FFT points to be supported, a maximum processing order, a maximum symbol length, a maximum windowing length, a maximum cyclic prefix length, a maximum interleaving depth, a maximum look-up table length of the codec unit, a maximum throughput of each processing unit, and the size of the shared memory unit.

[0092] For example, the system presets, for an FFT accelerator during the hardware generation phase, an upper limit of the number of FFT points (such as 4096 points) and determines a symbol time, a buffer size, and the number of butterfly computing units related to the upper limit. The hardware generation phase ensures that the accelerator can meet the highest performance requirements in different scenarios.

[0093] After the hardware generation is complete, the system can fine-tune the accelerator at runtime by a configuration of the register in the runtime configuration phase. The configuration includes, but is not limited to: the number of current FFT points, the order of the current filter chain and the corresponding coefficient, the current symbol length, the current windowing length and the corresponding coefficient, the current cyclic prefix length, the current interleaving depth, the size of the lookup table of the current codec unit and the content thereof.

[0094] For example, the number of FFT points may be controlled through the register to dynamically adapt to the specific needs of different protocols or applications. The design of 2025283574   18 Dec 2025 this phase provides flexibility in runtime, which enables the system to operate efficiently under different communication protocols.

[0095] This two-phase reconfigurable strategy not only ensures maximum performance support in hardware, but also allows dynamic adjustment at runtime, thereby ensuring that the system has sufficient flexibility and scalability when handling diverse protocols and applications.

[0096] An embodiment is described below.

[0097] As shown in FIG. 2, in an embodiment according to the technical solution of the present disclosure, the data protocol of the current OFDM baseband processor is taken as an example, a reconfigurable OFDM processor is designed, and a high-speed power line communication high performance low communication (HPLC) protocol state machine is designed for the HPLC-like protocol, and an acceleration unit such as the Turbo codec / inter-leaver is integrated for the processing unit of the HPLC-like protocol. The number of shared memory banks is two, and the specific solution of this embodiment is described as follows: dividing into submodules in a unit, and interaction between a computing unit and a control unit.

[0098] In the embodiment, the system is divided into three main computing units: a sampling point processing unit, a symbol processing unit and a block processing unit, and each unit includes multiple sub-modules for respectively realizing different functions.

[0099] The block processing unit includes a data packing module, a Turbo codec module, a convolutional code codec module and a verification module.

[0100] The symbol processing unit includes an interleaving module, a constellation mapping module and an FFT accelerator. The interleaving module disrupts the order of bits to enhance the anti-interference ability, the constellation mapping module maps the bits into modulation symbols, and the FFT accelerator realizes the conversion between the time domain and the frequency domain.

[0101] The sampling point processing unit includes modules such as a filter chain, windowing, a cyclic prefix and gain control. The modules operate together to perform the sampling and channel compensation of received signals, thereby ensuring efficient transmission of the signals in the physical layer.

[0102] Each processing unit (the sample point processing unit, the symbol processing unit, and the block processing unit) is scheduled and managed by the control unit. The control unit dynamically configures operating parameters of each processing unit according to the timing requirements of data processing and the requirements of current communication protocols. The control unit interacts with each computing unit through a configuration of the register to ensure that the control unit and the computing unit can operate synchronously and complete 2025283574   18 Dec 2025 their respective tasks on time. For example, the control unit may dynamically adjust, through the register, the number of FFT points in the symbol processing unit or an interpolation ratio in the sampling point processing unit.

[0103] In specific implementation, the present disclosure provides a computer storage medium and a corresponding data processing unit. The computer storage medium can store a computer program which, when the computer program is executed by the data processing unit, implement the contents of a reconfigurable OFDM baseband processor provided by the present disclosure and some or all of the steps in all the embodiments. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like.

[0104] The skilled in the art can clearly understand that the technical solutions in the embodiments of the present disclosure can be implemented by means of a computer program and a corresponding general hardware platform. Based on such understanding, an essential part of the technical solutions in the embodiments of the present disclosure or a part thereof contributing to the conventional technology may be embodied in the form of a computer program, that is, a software product, which may be stored in a storage medium and includes several instructions for causing a device (which may be a personal computer, a server, a single chip microcomputer, an MCU, a network device, or the like) including a data processing unit to perform the methods described in various embodiments or some portions of the embodiments of the present disclosure.

[0105] The present disclosure provides an idea and a method of a reconfigurable OFDM baseband processor, and there are many methods and ways to implement the technical solution. The foregoing is only a preferred embodiment of the present disclosure, and it should be pointed out that for ordinary skilled personnel in the technical field, several improvements and modification can also be made without departing from the principles of the present disclosure, and the improvements and modification should also be regarded as the scope of protection of the present disclosure. The components not specified in the embodiment can be implemented by the conventional technology.

Claims

2025283574   18 Dec 20251. A reconfigurable Orthogonal Frequency Division Multiplexing (OFDM) baseband processor, comprising: a control path, a data path, and a shared memory unit, wherein,the control path is connected with an interrupt signal of a host central processing unit (CPU) and is configured to receive interrupt control of the host CPU, and the control path is further connected with a slave bus interface of the host CPU and is configured to receive state control of the host CPU;the data path is connected with a main bus interface of the host CPU, and is configured to send and receive original OFDM data in the host CPU, and the data path is configured to convert an externally received OFDM time domain signal into original OFDM data and send the original OFDM data to the host CPU, or receive original OFDM data sent by the host CPU and convert the original OFDM data into an OFDM time domain signal and send the OFDM time domain signal to outside;the data path is further connected with the slave bus interface of the host CPU, which is used by the host CPU to configure the data path; andthe shared memory unit is configured to provide storage space to the data path in a shared memory manner.

2. The reconfigurable OFDM baseband processor according to claim 1, wherein the data path comprises:a data packet management module which is connected with the main bus interface of the host CPU and configured to send and receive the original OFDM data,wherein the data packet management module is connected with a data processing module, and the data processing module is configured to perform mutual conversion between the original OFDM data and the OFDM time domain signal, andthe data path further comprises a data transmission bus and a register configuration bus, wherein the data processing module uses the shared memory unit through the data transmission bus, and the control path controls the data processing module through the register configuration bus.

3. The reconfigurable OFDM baseband processor according to claim 2, wherein the data processing module is divided into three processing units according to an OFDM data processing process, and the three processing units are a block processing unit, a symbol processing unit, and2025283574   18 Dec 2025a sampling point processing unit, wherein,the block processing unit data is connected with the data packet management module, and is configured to send and receive the original OFDM data of the data packet management module, and perform mutual conversion between the original OFDM data and a data block;the symbol processing unit is configured to perform mutual conversion between the data block and symbol data;the sampling point processing unit is configured to perform mutual conversion between the symbol data and a sampling point signal; anddata interaction among the block processing unit, the symbol processing unit and the sampling point processing unit is performed through the data transmission bus and the shared memory unit.

4. The reconfigurable OFDM baseband processor according to claim 3, wherein the block processing unit comprises: a block processing unit direct memory access (DMA) sub-module, a block processing unit register, a block processing unit state machine, a check unit and a codec unit, wherein,the block processing unit DMA sub-module is configured to perform data interaction with the shared memory unit through the data transmission bus;the block processing unit register is configured to configure the block processing unit through the register configuration bus;the block processing unit state machine is configured to control an operation state of the block processing unit according to the control path;the check unit is configured to check integrity of the data; andthe codec unit is configured to perform error correction coding and decoding of the data.

5. The reconfigurable OFDM baseband processor according to claim 4, wherein the symbol processing unit configured to perform mutual conversion between the data block in the form of bit data and the symbol data in the form of carrier data comprises: a symbol processing unit DMA sub-module, a symbol processing unit register, a symbol processing unit state machine, a modulation demodulation sub-module, an interleaving sub-module, and a fast Fourier transform (FFT) or inverse fast Fourier transform (IFFT) processing sub-module, wherein,the symbol processing unit DMA sub-module is configured to perform data interaction with the shared memory unit through the data transmission bus;the symbol processing unit register is configured to configure the symbol processing unit2025283574   18 Dec 2025through the register configuration bus;the symbol processing unit state machine is configured to control an operation state of the symbol processing unit according to the control path;the modulation and demodulation sub-module is configured to map an encoded data block to symbol data by a modulator, or convert symbol data into a data block by demodulation;the interleaving sub-module is configured to perform an interleaving operation before or after modulation; andthe FFT or IFFT processing sub-module is configured to convert a signal between the frequency domain and the time domain.

6. The reconfigurable OFDM baseband processor according to claim 5, wherein the sampling point processing unit comprises: a sampling point processing unit DMA sub-module, a sampling point processing unit register, a sampling point processing unit state machine, a signal interpolation and decimation sub-module, and a filtering and enhancement sub-module, wherein,the sampling point processing unit DMA sub-module is configured to perform data interaction with the shared memory unit through the data transmission bus;the sampling point processing unit register is configured to configure the sampling point processing unit through the register configuration bus;the sampling point processing unit state machine is configured to control an operation state of the sampling point processing unit according to the control path;the signal interpolation and decimation sub-module is configured to perform an interpolation and decimation operation according to sampling rates and channel conditions of different transmission channels; andthe filtering and enhancement sub-module is configured to clear noise or interference in a data signal by using a filter and perform a signal enhancement operation.

7. The reconfigurable OFDM baseband processor according to claim 6, wherein the control path comprises: a reconfigurable state machine, a control path register and an interrupt control module, whereinthe reconfigurable state machine is configured to control the state machines in the block processing unit, the symbol processing unit and the sampling point processing unit;the control path register is connected to the register configuration bus and is configured to control the processing unit or read a state of the processing unit through the register in the processing unit; and2025283574   18 Dec 2025the interrupt control module is configured to deliver the interrupt signal to the host CPU to perform transaction level communication.

8. The reconfigurable OFDM baseband processor according to claim 7, wherein the shared memory unit is divided into N independent data storage blocks according to the number of processing units in the data processing module.

9. The reconfigurable OFDM baseband processor according to claim 8, wherein a two-phase reconfiguration strategy is used for configuration.

10. The reconfigurable OFDM baseband processor according to claim 9, wherein the two-phase reconfiguration strategy comprises: hardware generation and runtime configuration, whereinthe hardware generation is configured to generate a hardware configuration according to a requirement, and determine a maximum processing capacity of the OFDM baseband processor, which comprises:when OFDM baseband processing is performed, a set of FFT points to be supported, a maximum processing order, a maximum symbol length, a maximum windowing length, a maximum cyclic prefix length, a maximum interleaving depth, a maximum lookup table length, a maximum throughput of the processing unit and a size of the shared memory unit; andthe runtime configuration is configured to adjust the OFDM baseband processor through a configuration of the register after hardware generation is completed, which comprises:when OFDM baseband processing is performed, a number of FFT points, an order of a filter chain and a coefficient corresponding to the filter chain, a symbol length, a windowing length and a coefficient corresponding to the windowing length, a cyclic prefix length, a interleaving depth, a size and contents of a lookup table.

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