Method of handling radiation, readout circuit, radiation detector, and imaging apparatus

Abstract

A method of handling radiation comprising providing a plurality of pixels; providing a readout circuit comprising at least one register; acquiring, by the readout circuit in a first mode, first counted data based on a charge sharing electric signal representative of a sum of radiation energies from a set of pixels, and storing the first counted data in one or more registers, each time during a plurality of first data acquisition periods; and acquiring, by the readout circuit in a second mode, different from the first mode, second counted data based on a primary electric signal, and storing the second counted data in one or more registers, each time during a plurality of second data acquisition periods, the first data acquisition periods and the second data acquisition periods being alternating.

Description

[0001] METHOD OF HANDLING RADIATION, READOUT CIRCUIT, RADIATION DETECTOR, AND IMAGING APPARATUS

[0002] BACKGROUND

[0003] Various radiation detectors for detecting ionizing radiation are known in the art. A radiation source transmits radiation through an object, such as a patient, and the radiation detector measures the attenuated radiation. The radiation is converted to an electric signal, a control system processes these signals and the desired images can be provided.

[0004] For a radiation detector comprising a plurality of pixels, pulses can be summed over local pixel clusters. In this way, a risk for double counting photons which share charge between pixels can be reduced. The sum may be compared with one or more energy thresholds and the hit (and energy) may be accorded to the pixel with the greatest energy deposit. This technology is referred to as charge sharing correction, CSC. One example of such charge sharing correction is described in Reference 1, incorporated herein by reference.

[0005] Reference 1: "Medipix2, a 64k pixel read out chip with 55 pm square elements working in single photon counting mode"; X. Llopart, M. Campbell, D. San Segundo, E. Pernigotti, R. Dinapoli; IEEE 2002 0-7803-7324-3 / 02.

[0006] BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

[0007] FIG. 1: schematically represents an imaging apparatus comprising a radiation detector;

[0008] FIG. 2: schematically represents a top view of the radiation detector;

[0009] FIG. 3: schematically represents a partial cross-sectional side view of the radiation detector in section A-A in FIG. 2;

[0010] FIG. 4: schematically represents a readout circuit of the radiation detector when a switch arrangement is in a first state; FIG. 5: schematically represents the readout circuit in FIG. 4 when the switch arrangement is in a second state;

[0011] FIG. 6: schematically represents a readout circuit of the radiation detector according to a further example when a switch arrangement is in the first state;

[0012] FIG. 7: schematically represents the readout circuit in FIG. 6 when the switch arrangement is in the second state;

[0013] FIG. 8: schematically represents a readout circuit of the radiation detector according to a further example when a switch arrangement is in the first state;

[0014] FIG. 9: schematically represents the readout circuit in FIG. 8 when the switch arrangement is in the second state;

[0015] FIG. 10: schematically represents the readout circuit in FIGS. 8 and 9 when the switch arrangement is in a third state;

[0016] FIG. 11: schematically represents one example of a more detailed implementation of the readout circuit in FIGS. 6 and 7;

[0017] FIG. 12: schematically represents a part of the readout circuit in FIGS.

[0018] 6 and 7;

[0019] FIG. 13: schematically shows output count rates for a charge sharing correction circuit;

[0020] FIG. 14-16: show examples of alternations between first and second modes;

[0021] FIGS. 17-20: show examples of alternations between first, second and third modes; and

[0022] FIG. 21: is a flowchart outlining general steps of a method.

[0023] DETAILED DESCRIPTION

[0024] In the following, a method of handling radiation, a readout circuit for a radiation detector, a radiation detector comprising a plurality of pixels and at least one readout circuit, and an imaging apparatus comprising a radiation detector, will be described. The same or similar reference numerals will be used to denote the same or similar structural features. All known prior art charge sharing correction implementations have a reduced maximum output count rate due to pulse pile-up for increased input count rates. This may lead to a loss of counts or misregistered energy information. By providing, in a readout circuit for a radiation detector, an alternated acquisition in different frames, of first counted data based on a charge sharing electric signal representative of a sum of radiation energies from a set of pixels, and second counted data based on a primary electric signal representative of radiation energy from only a primary pixel, the performance of the radiation detector can be improved.

[0025] FIG. i schematically represents one example of an imaging apparatus io. The imaging apparatus io comprises a radiation detector 12 and a control system 14. The imaging apparatus 10 may be used for computed tomography (CT) scanning.

[0026] The imaging apparatus 10 further comprises a radiation source 16, such as an X-ray tube, for emitting X-rays that are transmitted through an object 18 to be imaged, for example through the body of a patient. After transmission through the object 18, the X-rays reach the radiation detector 12 where the X- rays are detected and converted into signals representing a spatially resolved projection image of the object 18.

[0027] The control system 14 is operatively connected to the radiation detector 12. The control system 14 is configured to read radiation data from the radiation detector 12. The control system 14 maybe configured to acquire 2D projection images. The acquired 2D images maybe used to reconstruct, for example 3D images, of the object 18 using inter alia known principles of computed tomography.

[0028] The control system 14 comprises a data processing device 20 and a memory 22. The memory 22 has a computer program stored thereon. The computer program comprises program code which, when executed by the data processing device 20, causes the data processing device 20 to perform, or command performance of, various steps described herein. FIG. 2 schematically represents a top view of the radiation detector 12. The radiation detector 12 comprises a plurality of pixels 24-11 to 24-nm. The radiation detector 12 may for example comprise at least 1000 pixels 24-11 to 24-nm. Each pixel 24-11 to 24-nm may also be referred to with reference numeral "24". The pixels 24 are distributed over at least a major part of the radiation detector 12, such as over the entire radiation detector 12. In this example, the pixels 24 form a two-dimensional array. The radiation detector 12 comprises n rows of pixels 24 and m columns of pixels 24, where each of n and m is a positive integer.

[0029] FIG. 2 further illustrates one example of a cluster or set 26 of pixels 24-22 and 24-23. In the set 26, the pixel 24-22 maybe a primary pixel and the pixel 24-23 may be a secondary pixel with respect to the primary pixel 24-22. As shown in FIG. 2, the secondary pixel 24-23 is neighboring to the primary pixel 24-22. The set 26 in FIG. 2 is only one of many examples. For pixels 24 having a square shape like in FIG. 2, the set 26 may comprise one or more neighboring pixels 24 that are arranged side by side to the primary pixel 24- 22 (such as the pixels 24-12, 24-21, 24-23 and 24-32) and / or one or more neighboring pixels 24 that are arranged diagonally adjacent to the primary pixel 24-22 (such as the pixels 24-11, 24-24, 24-31 and 24-33). The pixels 24 do also not need to have a square shape. Examples of alternative shapes of the pixels 24 comprise non-square rectangular shapes and hexagonal shapes.

[0030] Each pixel 24 of the radiation detector 12 may be associated with a unique set 26 of pixels 24 where that pixel 24 is a primary pixel 24 and where the other pixels 24 of that set 26 are secondary pixels 24. The sets 26 are used for charge sharing correction between pixels 24 as described herein.

[0031] FIG. 3 schematically represents a partial cross-sectional side view of the radiation detector 12 in section A-A in FIG. 2. The radiation detector 12 comprises a conversion element 28 and a readout substrate 30, for example a readout application-specific integrated circuit (ASIC) substrate. The radiation detector 12 further comprises a support substrate 32. The pixels 24 are provided in the conversion element 28. The conversion element 28 maybe constituted by at least one semiconductor substrate, such as a cadmium telluride (CdTe) or cadmium zinc telluride (CdZnTe or CZT) substrate. The conversion element 28 may comprise a continuous conversion substrate or several discrete conversion portions.

[0032] The conversion element 28 of this example further comprises a plurality of charge collection electrodes 34, here implemented as contact pads. Each pixel 24 is defined by a charge collection electrode 34.

[0033] When X-rays (or other type of ionizing radiation) impinges on the conversion element 28, electron-hole pairs are created inside the conversion element 28 (thus the term "direct conversion") in response to the absorbed energy.

[0034] Under the influence of an electric field applied across the conversion element 28, these electrons (holes) are transferred to associated charge collection electrodes 34. Thus, the conversion element 28 is configured to produce one or more charge carriers in response to incident radiation. For example, the conversion element 28 can capture and convert incident X-ray photons directly into electric charge.

[0035] The readout substrate 30 comprises a plurality of readout circuits 36-21, 36- 22 and 36-23 to 36-2m. Each readout circuit 36-21, 36-22, and 36-23 to 36- 2m may also be referred to with reference numeral "36". Each readout circuit 36 comprises a readout electrode 38, here implemented as a contact pad. The radiation detector 12 comprises one readout circuit 36 associated with each pixel 24.

[0036] The radiation detector 12 further comprises a plurality of interconnections 40. Each pair of one pixel 24 and one readout circuit 36 is connected by means of an interconnection 40. In FIG. 3, the interconnections 40 are exemplified as solder bumps between the charge collection electrodes 34 and the associated readout electrodes 38. Each readout electrode 38 thereby acts as the input to the associated readout circuit 36. Other types of interconnections 40 are however conceivable. Each readout circuit 36 comprises electronics with functions specific for the associated pixel 24. The readout circuits 36 are arranged to process signals generated by the radiation incident on the conversion element 28.

[0037] FIG. 4 schematically represents a readout circuit 36a. The readout circuit 36a maybe used as one, several or all of the readout circuits 36 of the radiation detector 12. As illustrated, the readout electrode 38 receives an electric input signal 42 from the associated pixel 24. The pixel 24 from which the readout circuit 36a receives the input signal 42 is a primary pixel 24 with respect to the readout circuit 36a. The radiation detector 12 may for example comprise at least 1000 pixels 24 and a readout circuit 36a according to FIG. 4 associated with each pixel 24. The readout circuit 36a is configured to handle the input signals 42 from the primary pixel 24 with respect to the readout circuit 36a.

[0038] The readout circuit 36a of this example comprises a charge sensitive amplifier 44. The charge sensitive amplifier 44 is configured to receive and amplify the input signal 42 from the primary pixel 24 associated with the readout circuit 36a and to output a primary electric signal 46. In this example, the primary electric signal 46 is output to a primary electric line 48. The primary electric signal 46 is representative of radiation energy from only the primary pixel 24, and not from any of the secondary pixels 24 of the set 26.

[0039] The readout circuit 36a is also configured to handle input secondary electric signals 50 (or signals derived therefrom) from one or more secondary pixels 24 with respect to the readout circuit 36a within the set 26 as described below. FIG. 4 illustrates a first input secondary electric signal 50-1 in a first secondary electric line 52-1 and a second input secondary electric signal 50-2 in a second secondary electric line 52-2. Each input secondary electric signal 50-1, 50-2 may also be referred to with reference numeral "50", and each secondary electric line 52-1, 52-2 may also be referred to with reference numeral "52". Although the readout circuit 36a of this example handles two input secondary electric signals 50, the readout circuit 36a may handle q input secondary electric signals 50, where q is a positive integer.

[0040] The readout circuit 36a of this example comprises a summing device 54. The summing device 54 sums the primary electric signal 46 from the primary pixel 24 with respect to the readout circuit 36a and one or more input secondary electric signals 50 from respective secondary pixels 24 with respect to the primary pixel 24, such as secondary pixels 24 neighboring to the primary pixel 24. The summing device 54 of this example outputs a charge sharing electric signal 56. The charge sharing electric signal 56 is thus representative of sum of radiation energies from a set 26 of pixels 24, such as the pixels 24-22, 24-23, 24-32. Due to the summing device 54, the readout circuit 36a is configured to perform a charge sharing correction function and to handle events between different pixels 24.

[0041] The readout circuit 36a of this example further comprises a switch arrangement 58a. The switch arrangement 58a of this example receives the primary electric signal 46 and the charge sharing electric signal 56 as inputs. In FIG. 4, the switch arrangement 58a is in a first state 60. In the first state 60, the switch arrangement 58a of this example outputs the charge sharing electric signal 56, but not the primary electric signal 46. In this example, the charge sharing electric signal 56 is output by the switch arrangement 58a to a tertiary electric line 62.

[0042] The switch arrangement 58a of this specific and non-limiting example comprises a first switch 64a! and a second switch 6432. The first switch 64a! receives the charge sharing electric signal 56 and the second switch 6432 receives the primary electric signal 46. In the first state 60, the first switch 64a! is closed and the second switch 6432 is open. The switch arrangement 58a thereby causes only the charge sharing electric signal 56, and not the primary electric signal 46 alone, to be output to the tertiary electric line 62. The switch arrangement 58a, e.g., the switches 64a!, 6432 thereof, may for example be controlled by the control system 14. The readout circuit 36a of this example further comprises at least one comparator 66. The readout circuit 36a may comprise a plurality of comparators, such as p comparators 66-1, 66-2 and 66-3 to 66-p, where p is a positive integer. Each comparator 66-1, 66-2 and 66-3 to 66-p may also be referred to with reference numeral "66". Each comparator 66 comprises a unique threshold value 68-1, 68-2 and 68-3 to 68-p. For example, a first comparator 66-1 comprises a first threshold value 68-1, a second comparator 66-2 comprises a second threshold value 68-2 higher than the first threshold value 68-1, and a third comparator 66-3 comprises a third threshold value 68-3 higher than the second threshold value 68-2. Each comparator 66 is configured to compare an electric signal in the tertiary electric line 62 with the associated threshold value 68. In the first state 60 of the switch arrangement 58a, each comparator 66 compares the charge sharing electric signal 56 with the respective threshold value 68.

[0043] The readout circuit 36a of this example further comprises one counter 70 associated with each comparator 66. For example, the output of each comparator 66 is coupled to the input of the associated counter 70. FIG. 4 shows p counters 70-1, 70-2 and 70-3 to 70-p. Each counter 70-1, 70-2 and 70-3 to 70-p may also be referred to with reference numeral "70". Each counter 70 counts pulses coming, either directly or indirectly, from the respective comparator 66. In the first state 60 of the switch arrangement 58a, all counters 70 are available for storing information from the charge sharing electric signal 56.

[0044] The readout circuit 36a of this example further comprises one register 72 associated with each counter 70. For example, the output of each counter 70 is coupled to the input of the associated register 72. FIG. 4 shows p registers 72-1, 72-2 and 72-3 to 72-p. Each register 72-1 and 72-2 to 72-p may also be referred to with reference numeral "72". Each register 72 is here exemplified as a shift-register. Each group of a comparator 66, a counter 70 and a register 72 may be referred to as a channel. FIG. 4 further shows a signal line 74. The readout circuit 36a receives serial data from one or more other readout circuits 36a of the radiation detector 12 via the signal line 74. Data from the one or more registers 72 is then added to the serial data and passed on to the next readout circuit 36a and so on until serial data 76 from a last readout circuit 36a is read out.

[0045] In FIG. 4, the readout circuit 36a is in a first mode 78. In the first mode 78 of this example, the switch arrangement 58a is in the first state 60. The first mode 78 of the readout circuit 36a of this example maybe referred to as a charge sharing correction, CSC, mode. The radiation detector 12 may be controlled such that one, several or all of the readout circuits 36a is in the first mode 78 simultaneously, i.e., such that CSC is simultaneously turned on for one, several or all of the pixels 24.

[0046] FIG. 5 schematically represents the readout circuit 36a in a second mode 80. In the second mode 80 of this example, the switch arrangement 58a is in a second state 82. In the second state 82, the switch arrangement 58a of this example outputs the primary electric signal 46, but not the charge sharing electric signal 56. In this example, the primary electric signal 46 is output to the tertiary electric line 62.

[0047] In the second state 82, the first switch 64a! is open and the second switch 6432 is closed. The switch arrangement 58a thereby causes only the primary electric signal 46, and not the charge sharing electric signal 56, to be output to the tertiary electric line 62. In the second state 82, all counters 70 are available for storing information from the primary electric signal 46.

[0048] The second mode 80 of the readout circuit 36a of this example maybe referred to as a non-CSC mode. The radiation detector 12 may be controlled such that one, several or all of the readout circuits 36a is in the second mode 80 simultaneously, i.e., such that CSC is simultaneously turned off for one, several or all of the pixels 24. In this example, the same one or more channels are used in both the first and second modes 78, 80. For example, the charge sharing electric signal 56 is input to the first comparator 66-1 in the first mode 78, and the primary electric signal 46 is input to the first comparator 66-1 in the second mode 80. In this way, a switch between the first and second modes 78, 80 can be used as an alternative to changing the threshold values 68. Thus, the same threshold values 68 can be used in both the first and second modes 78, 80. This enables an easier reconstruction.

[0049] FIG. 6 schematically represents a readout circuit 36b according to a further example. The readout circuit 36b maybe used as one, several or all of the readout circuits 36 of the radiation detector 12. Mainly differences with respect to the readout circuits 36a will be described.

[0050] Instead of the switch arrangement 58a, the readout circuit 36b comprises a switch arrangement 58b. The switch arrangement 58b of this example comprises a first switch 64b! and a second switch 64b2. The first switch 64b! receives the first input secondary electric signal 50-1 and the second switch 64b2 receives the second input secondary electric signal 50-2. In FIG. 6, the switch arrangement 58b is in the first state 60 and the readout circuit 36b is thereby in the first mode 78. In the first state 60 of the switch arrangement 58b of this example, the first and second switches 64b!, 64b2 are closed and thereby output the first and second input secondary electric signals 50-1, 50- 2, respectively, to the summing device 54. The primary electric signal 46, the first input secondary electric signal 50-1 and the second input secondary electric signal 50-2 are thereby summed by the summing device 54 and the charge sharing electric signal 56 is output to the tertiary electric line 62.

[0051] FIG. 7 schematically represents the readout circuit 36b when the switch arrangement 58b is in the second state 82 and the readout circuit 36b thereby is in the second mode 80. In the second state 82 of the switch arrangement 58b of this example, the first and second switches 64b!, 64b2 are open and do thereby not output any of the first and second input secondary electric signals 50-1, 50-2, respectively, to the summing device 54. The summing device 54 thereby only receives the primary electric signal 46 which is thereby also outputted by the summing device 54 to the tertiary electric line 62. FIG. 8 schematically represents a readout circuit 36c according to a further example. The readout circuit 36c maybe used as one, several or all of the readout circuits 36 of the radiation detector 12. Mainly differences with respect to the readout circuit 36a will be described.

[0052] Instead of the switch arrangement 58a, the readout circuit 36c comprises a switch arrangement 58c. The readout circuit 36c of this example further comprises a first tertiary electric line 62 and a second tertiary electric line 84. One or more of the comparators 66, here the first and second comparators 66-1, 66-2, are configured to compare an electric signal in the first tertiary electric line 62 with the associated threshold value 68. One or more of the comparators 66, here the third and last (e.g., fourth) comparators 66-3, 66-p, are configured to compare an electric signal in the second tertiary electric line 84 with the associated threshold value 68. Moreover, in the readout circuit 36c of this example, one or more of the registers 72, here the first and second registers 72-1, 72-2, are arranged in a first register group 86, and one or more of the registers 72, here the third and last registers 72-3, 72-p, are arranged in a second register group 88.

[0053] The switch arrangement 58c of this specific and non-limiting example comprises a first switch 64m, a second switch 6402, a third switch 6403 and a fourth switch 6404. The first and third switches 64m, 6403 receive the charge sharing electric signal 56 from the summing device 54. The second and fourth switches 6402, 6404 receive the primary electric signal 46 from the charge sensitive amplifier 44.

[0054] In FIG. 8, the switch arrangement 58c is in the first state 60 and the readout circuit 36c is thereby in the first mode 78. In the first state 60 of the switch arrangement 58c of this example, the first and third switches 64m, 6403 are closed and the second and fourth switches 6402, 6404 are open. Thereby, the charge sharing electric signal 56, but not the primary electric signal 46 alone, is output to both the first and second tertiary electric lines 62, 84. One, several or all of the readout circuits 36a-36c may also be referred to with reference numeral "36". One, several or all of the switch arrangements 58a- 58c may also be referred to with reference numeral "58".

[0055] FIG. 9 schematically represents the readout circuit 36c. In FIG. 9, the switch arrangement 58c is in the second state 82 and the readout circuit 36c is thereby in the second mode 80. In the second state 82 of the switch arrangement 58c of this example, the first and third switches 64CI, 6403 are open and the second and fourth switches 6402, 6404 are closed. Thereby, the primary electric signal 46, but not the charge sharing electric signal 56, is output to both the first and second tertiary electric lines 62, 84.

[0056] FIG. 10 schematically represents the readout circuit 36c. In FIG. 10, the switch arrangement 58c is in a third state 90 and the readout circuit 36c is thereby in a third mode 92. In the third state 90 of the switch arrangement 58c of this example, the first and fourth switches 6401, 6404 are open and the second and third switches 6402, 6403 are closed. Thereby, the primary electric signal 46 is output to the first tertiary electric line 62 and charge sharing electric signal 56 is output to the second tertiary electric line 84. The third mode 92 of this example maybe referred to as a mixed mode, i.e., a mix between a CSC mode and a non-CSC mode. Opening of the first switch 6401 associated with the relatively low first threshold value 68-1 and closing of the third switch 6403 associated with the relatively high third threshold value 68- 3 provides a better effect in terms of avoiding saturation.

[0057] FIG. 11 schematically represents one specific and non-limiting example of a more detailed implementation of the readout circuit 36b in FIGS. 6 and 7. The readout circuit 36b of this example further comprises a global comparator 94. A global threshold value 96 is set in the global comparator 94. The global comparator 94 compares the input signal 42 or a signal derived from the input signal 42 with the global threshold value 96 and outputs a second primary electric signal 98. In this example, the global comparator 94 compares the primary electric signal 46 from the charge sensitive amplifier 44 with the global threshold value 96. The primary electric signal 46 may thus be referred to as a first primary electric signal 46 in this example. A pulse length of the second primary electric signal 98 is proportional to a charge deposited in the primary pixel 24. The global threshold value 96 may for example be set to a level slightly higher than a noise level, such as three times the noise level.

[0058] The readout circuit 36b of this example comprises at least one charge sharing correction circuit 100. The readout circuit 36b may comprise a plurality of charge sharing correction circuits, such as p charge sharing correction circuits 100-1 and 100-2 to 100-p. Each charge sharing correction circuit 100- 1 and 100-2 to 100-p may also be referred to with reference numeral "100". Each charge sharing correction circuit 100 is configured to handle the charge sharing electric signal 56, e.g., at least in the first mode 78 of the readout circuit 36b. In this example, each charge sharing correction circuit 100 is also configured to handle the second primary electric signal 98 in the second mode 80 of the readout circuit 36b.

[0059] Each charge sharing correction circuit 100 comprises a comparator section 102-1 and 102-2 to 102-p. Each comparator section 102-1 and 102-2 to 102-p may also be referred to with reference numeral "102". Each comparator section 102 comprises one of the comparators 66. Moreover, each charge sharing correction circuit 100 comprises one of the counters 70 and one of the registers 72.

[0060] Each comparator section 102 is configured to output respective sharing data 104-1 and 104-2 to 104-p, e.g., at least in the first mode 78 of the readout circuit 36b. The sharing data 104-1 and 104-2 to 104-p may also be referred to with reference numeral "104". When the readout circuit 36b is in the second mode 80, each comparator section 102 outputs respective nonsharing data 106-1 and 106-2 to 106-p. The non-sharing data 106-1 and 106-2 to 106-p may also be referred to with reference numeral "106".

[0061] Each counter 70 is configured to count sharing data 104 and output respective first counted data 108-1 and 108-2 to 108-p in the first mode 78 of the readout circuit 36b, and to count non-sharing data 106 and output respective second counted data 110-1 and 110-2 to 110-p in the second mode 80 of the readout circuit 36b. The first counted data 108-1 and 108-2 to 108-p and the second counted data 110-1 and 110-2 to 110-p may also be referred to with reference numerals "108" and "no", respectively. Each register 72 is configured to receive and handle the first counted data 108 from the associated counter 70 in the first mode 78 of the readout circuit 36b, and receive and handle the second counted data no from the associated counter 70 in the second mode 80 of the readout circuit 36b.

[0062] In this example, each of the input secondary electric signals 50-1 to 50-q from a secondary pixel 24 corresponds to the first primary electric signal 46 of the primary pixel 24. That is, the relationship between the first primary electric signal 46 and the primary pixel 24 corresponds to each relationship between the input secondary electric signals 50-1 to 50-q and the associated secondary pixel 24. One, several or all of the input secondary electric signals 50-1 to 50- q may also be referred to with reference numeral "50".

[0063] FIG. 11 further shows that the readout circuit 36b of this example handles at least one output primary electric signal 112-1 to 112-q. One, several or all of the output primary electric signal 112-1 to 112-q may also be referred to with reference numeral "112". The readout circuit 36b may provide q output primary electric signals 112 to q other readout circuits 36b of the radiation detector 12. Each output primary electric signal 112 may be constituted by the first primary electric signal 46.

[0064] FIG. 11 further shows that the readout circuit 36b of this example also handles at least one input secondary electric signal 114-1 to 114-q and at least one output secondary electric signal 116-1 to 116-q. Each input secondary electric signal 114-1 to 114-q and each output secondary electric signal 116-1 to 116-q may also be referred to with reference numerals "114" and "116", respectively. FIG. n further shows that the number of input secondary electric signals 50, the number of output primary electric signals 112, the number of input secondary electric signals 114 and the number of output secondary electric signal 116 may be the same. Each group of an input secondary electric signal 50, an output primary electric signal 112, an input secondary electric signal 114 and an output secondary electric signal 116 may be routed between the readout circuit 36b associated with the primary pixel 24 and a readout circuit 36b associated with a secondary pixel 24 in the set 26. The output primary electric signal 112 output from the readout circuit 36b associated with a primary pixel 24 may be used as the input secondary electric signal 50 in the readout circuit 36b associated with a secondary pixel 24, and vice versa. Correspondingly, the output secondary electric signal 116 output from the readout circuit 36b associated with a primary pixel 24 may be used as the input secondary electric signal 114 in the readout circuit 36b associated with a secondary pixel 24, and vice versa.

[0065] Each pixel 24 of the radiation detector 12 may comprise the readout circuit 36b which may as such be identical for each pixel 24. However, the readout circuits 36b may differ from each other in the sense that each readout circuit 36b is in communication with a unique set 26 of pixels 24.

[0066] FIG. 12 schematically represents a part of the readout circuit 36b. The same or similar architecture of the readout circuit 36b as shown in FIGS. 11 and 12 may also be employed for the readout circuits 36a, 36c. In the specific and non-limiting implementation of the readout circuit 36b shown in FIG. 12, each comparator section 102 comprises an OR gate 118, an allocation comparator 120, a summing device 54, the comparator 66 and an AND gate 122. Thus, instead of a common summing device 54 for the entire readout circuit 36b, a summing device 54 maybe implemented in each comparator section 102.

[0067] In case a plurality of comparator sections 102 are used, i.e., if the readout circuit 36b comprises a plurality of charge sharing correction circuits 100, the comparator sections 102 may only differ from each other by the unique threshold values 68.

[0068] In the following, a description is given for the comparator section 102-1. This description is also applicable for each further comparator section 102-2 to 102-p in the readout circuit 36b.

[0069] The OR gate 118-1 is configured to receive the one or more input secondary electric signals 114 from a readout circuit 36b of all secondary pixels 24 within the set 26. The OR gate 118-1 is configured to output an OR gate output signal 124-1.

[0070] When the switch arrangement 58b is in the first state 60, the summing device 54-1 receives the first primary electric signal 46 and the input secondary electric signals 50 from a readout circuit 36b of all secondary pixels 24 within the set 26 as input signals, sums the input signals and outputs the charge sharing electric signal 56-1 as the sum. When the switch arrangement 58b is in the second state 82, the summing device 54-1 receives only the first primary electric signal 46 and thereby also outputs the first primary electric signal 46.

[0071] The allocation comparator 120-1 is configured to receive the OR gate output signal 124-1 and to set an allocation threshold value based on the OR gate output signal 124-1. The allocation comparator 120-1 is configured to compare the second primary electric signal 98 with the allocation threshold value and to output an allocation output signal 126-1 if the second primary electric signal 98 is larger than the OR gate output signal 124-1.

[0072] In the first state 60 of the switch arrangement 58b, the comparator 66-1 compares the charge sharing electric signal 56-1 with the threshold value 68-1 and outputs comparator data, here in the form of a comparator signal 128-1, if the charge sharing electric signal 56-1 is larger than the threshold value 68- 1. In the second state 82 of the switch arrangement 58b, the comparator 66-1 compares the first primary electric signal 46-1 with the threshold value 68-1 and outputs the comparator signal 128-1 if the first primary electric signal 46- 1 is larger than the threshold value 68-1.

[0073] When the switch arrangement 58b is in the first state 60, the AND gate 122-1 is configured to output a high output as sharing data 104-1 only when both the allocation output signal 126-1 and the comparator signal 128-1 are high. When the switch arrangement 58b is in the second state 82, the AND gate 122-1 is configured to output a high output as non-sharing data 106-1 only when both the allocation output signal 126-1 and the comparator signal 128-1 are high.

[0074] In this way, the charge sharing correction circuits 100 can sum radiation energies from a single photon hit from all pixels 24 of the set 26 and allocate the sum of radiation energies only to the pixel 24 of the set 26 where the highest charge is allocated (given that this sum of radiation energies is above the respective threshold value 68). Thus, an event is only counted in the pixel 24 receiving the highest charge and the level of that charge is the sum of all charges in the set 26 at the same time.

[0075] According to one variant, the one or more input secondary electric signals 114 are input to the summing device 54-1 instead of the one or more input secondary electric signals 50. Also in this way, radiation energies from a single photon hit from all pixels 24 of the set 26 can be summed. It would also be possible to utilize the output primary electric signals 112 and the input secondary electric signals 50, but not the input secondary electric signals 114 and the output secondary electric signals 116, to allocate the sum of radiation energies only to the pixel 24 of the set 26 where the highest charge is allocated.

[0076] Although the readout circuit 36b can provide improved energy level information from the incident radiation due to the CSC in the first mode 78, the handling of the radiation by the readout circuit 36b is slower in the first mode 78 than in the second mode 80 due to pulse pile up. When the readout circuit 36b is in the first mode 78, the pulse needs to decrease below the respective threshold value 68, before a new pulse can be triggered. This is for example described in more detail in published Swedish patent application SE 2250970 Al, the contents of which is incorporated herein in its entirety. For a given set of threshold values 68, the deadtime for the charge sharing correction circuits 100 associated with a set 26 will also generally increase in the first mode 78 of the readout circuit 36b with an increased number of pixels 24 in the set 26.

[0077] Due to the ability of the readout circuit 36b to operate in both the first and second modes 78, 80, the readout circuit 36b allows for a different handling of CSC in different frames. For example, the readout circuit 36b allows for an alternating acquisition of CSC counts in the first mode 78 and single pixel counts in the second mode 80 in different frames. Thus, all radiation detectors where a high flux may lead to pulse pile-up will benefit from this solution.

[0078] FIG. 13 schematically shows a specific and non-limiting example of output count rates 130 for one of the charge sharing correction circuits 100 in a common readout circuit 36 when the readout circuit 36 is in the first mode 78 and in the second mode 80 and for different input count rates 132. The unit of the input count rate 132 and the output count rate 130 is counts / s*mm2(counts per second per square millimeter). The input count rate 132 is typically different between different pixels 24 depending on the exposure to radiation of that pixel 24. For example, the input count rate 132 of pixels 24 receiving radiation that has not interacted with the object 18 is typically substantially higher than the input count rate 132 of pixels 24 receiving radiation that has interacted with the object 18.

[0079] A non-sharing curve 134 in this specific and non-limiting example represents output count rates 130 in a charge sharing correction circuit 100 when the readout circuit 36 is in the second mode 80. The charge sharing correction circuit 100 may for example have the threshold value 68 set to 15 keV and a deadtime of 41 ns. A charge sharing correction curve 136 in this specific and non-limiting example represents output count rates 130 in the charge sharing correction circuit 100 when the readout circuit 36 is in the first mode 78. The charge sharing correction circuit 100 may for example have the threshold value 68 set to 15 keV and a deadtime of 117 ns.

[0080] Although the charge sharing correction works well for low input count rates 132, saturation issues occur at lower input count rates 132 for the readout circuit 36 in the first mode 78 than in the second mode 80 due to the longer deadtimes of the charge sharing correction circuit 100 when the readout circuit 36 is in the first mode 78. As shown by the charge sharing correction curve 136, the input count rate 132 may increase while the recorded events decrease when the readout circuit 36 is in the first mode 78.

[0081] As shown in FIG. 13, values of the output count rate 130 on the non-sharing curve 134 uniquely correspond to values of the input count rate 132 from zero to at least relatively high input count rates 132 (from zero to at least to 4*108 counts / s*mm2in the specific example in FIG. 13). For the charge sharing correction curve 136 in contrast, values of the output count rate 130 uniquely correspond to values of the input count rate 132 only to substantially lower input count rates 132 (from zero to approximately 1.8*108 counts / s*mm2in the specific example in FIG. 13). At input count rates 132 above approximately 1.8*108 counts / s*mm2, the output count rate 130 on the charge sharing correction curve 136 decreases for increasing input count rates 132. The reason for this is that the deadtime is longer for the charge sharing correction circuits 100 when the readout circuit 36 is in the first mode 78 than when the readout circuit 36 is in the second mode 80. By determining the output count rate 130 based on recorded events in the charge sharing correction circuits 100 when the readout circuit 36 is in the second mode 80 rather than based on recorded events in the charge sharing correction circuits 100 when the readout circuit 36 is in the first mode 78, the output count rate 130 can be determined correctly for higher input count rates 132. A count rate threshold value 138 maybe set at an input count rate 132 where the output count rate 130 in any of the charge sharing correction circuits 100 decrease for increasing input count rates 132 when the readout circuit 36 is in the first mode 78. A detection of such input count rate 132 where the output count rate 130 of the charge sharing correction curve 136 decrease for increasing input count rates 132 can be made by simulations, calculations and / or experiments. For example, with respect to FIG. 13, it can be seen that the count rate threshold value 138 is set at a peak level of the charge sharing correction curve 136, here at a level of the input count rate 132 where a derivative of the output count rate 130 with respect to the input count rate 132 is zero. The count rate threshold value 138 maybe set by the control system 14. Since each readout circuit 36 has the same hardware, the count rate threshold value 138 maybe the same for all readout circuits 36.

[0082] The imaging apparatus 10, such as the control system 14 thereof, may determine the input count rate 132 for each readout circuit 36 based on the second counted data no.

[0083] The output count rate CRoutput (or 130) maybe determined as:

[0084] / -•n _ Cnsc , output ~ GJ where CnSc is the number of counts counted by the charge sharing correction circuit 100 when the readout circuit 36 is in the second mode 80 (such as the number of counts during a data acquisition period), t is a period of time (such as the data acquisition period), and A is an area of the primary pixel 24 associated with the readout circuit 36. The input count rate 132 may then be determined based on the output count rate 130. The input count rate 132 may for example be determined based on a mathematical formula or simulations representing the relationship between the output count rate 130 and the input count rate 132 for the charge sharing correction circuit 100 when the readout circuit 36 is in the second mode 80, i.e., the non-sharing curve 134 in FIG. 13. The input count rate 132 maybe determined for one, several or all of the readout circuits 36.

[0085] The input count rate 132 for radiation not passing through the object 18 may be substantially higher than the input count rate 132 for radiation passing through the object 18 since fewer X-rays pass through the object 18. The count rate threshold value 138 may thus for example be set such that the input count rate 132 for radiation not passing through the object 18 is above the count rate threshold value 138 and such that the input count rate 132 for radiation passing through the object 18 is below the count rate threshold value 138.

[0086] The radiation detector 12 can thus handle high input count rates 132 in pixels 24 by the readout circuits 36 when adopting the second mode 80 and provide a high energy resolution by the readout circuits 36 when adopting the first mode 78.

[0087] FIG. 14 shows an example of alternations between first data acquisition periods 140 and second data acquisition periods 142. In each first data acquisition period 140, the readout circuit 36 is in the first mode 78, acquires the first counted data 108 based on the charge sharing electric signal 56 and stores the first counted data 108 in the registers 72. In each second data acquisition period 142, the readout circuit 36 is in the second mode 80, acquires the second counted data no based on the primary electric signal 46 and stores the second counted data no in the registers 72.

[0088] FIG. 14 further shows that first frames 144 each comprises the first data acquisition period 140 and a first readout period 146 following the first data acquisition period 140, and that second frames 148 each comprises the second data acquisition period 142 and a second readout period 150 following the second data acquisition period 142. In each first frame 144, the readout circuit 36 is in the first mode 78. In each second frame 148, the readout circuit 36 is in the second mode 80.

[0089] In each first readout period 146, the first counted data 108 is read out from the registers 72. In each second readout period 150, the second counted data no is read out from the registers 72.

[0090] At the end of a first frame 144, between the first frame 144 and the next second frame 148, and / or at the beginning of the next second frame 148, the operation mode is changed from the first mode 78 to the second mode 80. Conversely, at the end of a second frame 148, between the second frame 148 and the next first frame 144, and / or at the beginning of the next first frame 144, the operation mode is changed from the second mode 80 to the first mode 78. The operation mode may thus change between frames.

[0091] As shown in FIG. 14, every two frames is a first frame 144 and every two frames is a second frame 148. There is thus an alternating acquisition of the first counted data 108 and the second counted data no by the readout circuit 36. Moreover, a first frame frequency of the first frames 144 and a second frame frequency of the second frames 148 are here the same. The first and second frame frequencies define a number of first frames 144 and second frames 148, respectively, in a time period.

[0092] The first frames 144 may provide a better energy information than the second frames 148. Conversely, the second frames 148 may provide higher output count rates 130 than the first frames 144.

[0093] In this example, all readout circuits 36 of the radiation detector 12 may simultaneously adopt the first mode 78 in the first frames 144 and simultaneously adopt the second mode 80 in the second frames 148. As one possible exemplifying modification, the readout circuits 36 associated with a first pixel group of pixels 24 may simultaneously adopt the first mode 78 and the readout circuits 36 associated with a second pixel group of pixels 24 may simultaneously adopt the second mode 80 in the first frames 144, and the readout circuits 36 associated with the first pixel group may simultaneously adopt the second mode 80 and the readout circuits 36 associated with the second pixel group may simultaneously adopt the first mode 78 in the second frames 148, or vice versa. Each pixel 24 may in this case belong to either the first pixel group or the second pixel group. Each of the first and second pixel groups may for example form a checkered pattern on the radiation detector 12.

[0094] FIG. 15 shows a further example of alternations between the first data acquisition periods 140 and the second data acquisition periods 142. Up until time ti, the first and second frame frequencies are the same. From time ti, the first frame frequency and the second frame frequency are changed in this example such that the first frame frequency becomes twice the second frame frequency. For example, in case the input count rate 132 is below the count rate threshold value 138, the first frequency maybe increased and the second frequency maybe decreased.

[0095] The change may for example be determined based on the input count rate 132 from a preceding frame, such as from a preceding second frame 148, such as from a preceding second frame 148 immediately before time ti. At some of the second frames 148, the first and / or second frame frequencies may be evaluated and changed. In this way, the radiation detector 12 can efficiently adapt to the radiation to provide an optimal tradeoff between input count rate 132 and energy resolution.

[0096] This adaptation can be performed individually for different readout circuits 36 or different readout circuit groups of readout circuits 36. For example, for a first readout circuit group associated with a first pixel group subjected to a relatively high flux, the first frame frequency may be set relatively low and the second frame frequency maybe set relatively high, or only the second frames 148 may be used. Correspondingly, for a second readout circuit group associated with a second pixel group, different from the first pixel group, subjected to a relatively low flux, the first frame frequency may be set relatively high and the second frame frequency may be set relatively low, or only the first frames 144 may be used.

[0097] FIG. 16 shows a further example of alternations between the first data acquisition periods 140 and the second data acquisition periods 142. Up until time t2, the first and second frame frequencies are the same. From time t2, the first frame frequency and the second frame frequency are changed in this example such that the first frame frequency becomes half the second frame frequency. For example, in case the input count rate 132 is above the count rate threshold value 138, the first frequency maybe decreased and the second frequency maybe increased. In each of FIGS. 14-16, there is an alternating acquisition of the first counted data 108 in the first data acquisition periods 140 and the second counted data no in the second data acquisition periods 142.

[0098] If for example four energy levels should be recorded for each of the charge sharing electric signal 56 and the primary electric signal 46 using simultaneous acquisition, this would require eight registers 72. By instead alternating between the first frames 144 and the second frames 148, a set of same four registers 72 can be used to store the first counted data 108 in the first frames 144 by controlling the readout circuit 36 to operate in the first mode 78, and to store the second counted data no in the second frames 148 by controlling the readout circuit 36 to operate in the second mode 80. Should the input count rate 132 be relatively high, e.g., above the count rate threshold value 138, the second frame frequency maybe increased relative to the first frame frequency, e.g., as shown in FIG. 15 to reduce an amount of pulse pile-up. Conversely, should the input count rate 132 be relatively low, e.g., below the count rate threshold value 138, the first frame frequency may be increased relative to the second frame frequency, e.g., as shown in FIG. 16, to increase energy resolution. In this way, the method enables a provision of both high input count rate 132 and high energy resolution while reducing an amount of data handled by the readout circuit 36, and while requiring relatively few registers 72, e.g., only four instead of eight in the above- mentioned example.

[0099] FIG. 17 shows an example of alternations between the first data acquisition periods 140, the second data acquisition periods 142, and third data acquisition periods 152. Mainly differences with respect to FIGS. 14-16 will be described. In each third data acquisition period 152, the readout circuit 36, such as the readout circuit 36c, is in the third mode 92, acquires both the first counted data 108 and the second counted data no and stores both the first counted data 108 and the second counted data no in the registers 72.

[0100] FIG. 17 further shows that third frames 154 each comprises the third data acquisition period 152 and a third readout period 156 following the third data acquisition period 152. In each third frame 154, the readout circuit 36 is in the third mode 92. In each third readout period 156, both the first counted data 108 and the second counted data no are read out from the registers 72.

[0101] As shown in FIG. 17, every three frames is a first frame 144, every three frames is a second frame 148 and every three frames is a third frame 154. There is thus an alternating acquisition of the first counted data 108 and the second counted data no by the readout circuit 36 also in this example. Moreover, a first frame frequency of the first frames 144, a second frame frequency of the second frames 148 and a third frame frequency of the third frames 154 are the same.

[0102] In this example, all readout circuits 36 of the radiation detector 12 may simultaneously adopt the first mode 78 in the first frames 144, simultaneously adopt the second mode 80 in the second frames 148, and simultaneously adopt the third mode 92 in the third frames 154. As one possible exemplifying modification, the readout circuits 36 associated with a first pixel group may simultaneously adopt the first mode 78, the readout circuits 36 associated with a second pixel group may simultaneously adopt the second mode 80, and the readout circuits 36 associated with a third pixel group may simultaneously adopt the third mode 92, in the first frames 144. In this exemplifying modification, the readout circuits 36 associated with the first pixel group may simultaneously adopt the second mode 80, the readout circuits 36 associated with the second pixel group may simultaneously adopt the third mode 92, and the readout circuits 36 associated with the third pixel group may simultaneously adopt the first mode 78, in the second frames 148. Moreover, in this exemplifying modification, the readout circuits 36 associated with the first pixel group may simultaneously adopt the third mode 92, the readout circuits 36 associated with the second pixel group simultaneously adopt the first mode 78, and the readout circuits 36 associated with the third pixel group may simultaneously adopt the second mode 80, in the third frames 154. Each pixel 24 may in this case belong to one of the first to third pixel groups. FIG. 18 shows a further example of alternations between the first data acquisition periods 140, the second data acquisition periods 142, and third data acquisition periods 152. Up until time t3, the first, second and third frame frequencies are the same. From time t3, the first frame frequency is increased and each of the second and third frame frequencies is decreased. The change may for example be determined based on the input count rate 132 from a preceding frame, such as from a preceding second frame 148 or third frame 154, such as from a preceding second frame 148 or third frame 154 immediately before time t3.

[0103] FIG. 19 shows a further example of alternations between the first data acquisition periods 140, the second data acquisition periods 142, and third data acquisition periods 152. Up until time t4, the first, second and third frame frequencies are the same. From time t4, the second frame frequency is increased and each of the first and third frame frequencies is decreased.

[0104] FIG. 20 shows a further example of alternations between the first data acquisition periods 140, the second data acquisition periods 142, and third data acquisition periods 152. Up until time t5, the first, second and third frame frequencies are the same. From time t5, the third frame frequency is increased and each of the first and second frame frequencies is decreased.

[0105] FIG. 21 is a flowchart outlining general steps of a method. The method comprises providing S10 a plurality of pixels 24 configured to detect radiation energies of incident radiation. The method further comprises providing S12 a readout circuit 36 comprising at least one register 72, the readout circuit 36 being configured to handle a primary electric signal 46 representative of radiation energy from only a primary pixel 24 with respect to the readout circuit 36 among the plurality of pixels 24. The method further comprises acquiring S14, by the readout circuit 36 in a first mode 78, first counted data 108 based on a charge sharing electric signal 56 representative of a sum of radiation energies from a set 26 of pixels 24 among the primary pixel 24 and at least one secondary pixel 24 with respect to the readout circuit 36 among the plurality of pixels 24, and storing the first counted data 108 in one or more of the at least one register 72, each time during a plurality of first data acquisition periods 140.

[0106] The acquisition S14 may comprise comparing S16, by a comparator 66 in the readout circuit 36, the charge sharing electric signal 56 with a threshold value 68; and counting S18, by a counter 70 in the readout circuit 36, comparator data 128 associated with the comparator 66 to acquire the first counted data 108.

[0107] The method may further comprise reading out S20 the first counted data 108 from the one or more registers 72 each time during a plurality of first readout periods 146, each first readout period 146 following a first data acquisition period 140.

[0108] The method further comprises acquiring S22, by the readout circuit 36 in a second mode 80, different from the first mode 78, second counted data no based on the primary electric signal 46, and storing the second counted data no in one or more of the at least one register 72, each time during a plurality of second data acquisition periods 142, the first data acquisition periods 140 and the second data acquisition periods 142 being alternating.

[0109] The acquisition S22 may comprise comparing S24, by the comparator 66, the primary electric signal 46 with the threshold value 68, and counting S26, by the counter 70, comparator data 128 associated with the comparator 66 to acquire the second counted data 110.

[0110] The method may further comprise reading out S28 the second counted data 110 from the one or more registers 72 each time during a plurality of second readout periods 150, each second readout period 150 following a second data acquisition period 142.

[0111] The method may further comprise acquiring S30, by the readout circuit 36 in a third mode 92, first counted data 108 and storing the first counted data 108 in one or more of the registers 72 in the first register group 86, and acquiring, by the readout circuit 36 in the third mode 92, second counted data no and storing the second counted data no in one or more of the registers 72 in the second register group 88, each time during a plurality of third data acquisition periods 152.

[0112] The acquisition S30 may further comprise comparing S32, by two comparators 66, the primary electric signal 46 with a threshold value 68 associated with the first register group 86 and the charge sharing electric signal 56 with a threshold value 68 associated with the second register group 88, and counting S34, by two counters 70, comparator data 128 associated with the two comparators 66 to acquire the first counted data 108 and the second counted data no.

[0113] The method may further comprise reading out S36 the first counted data 108 and the second counted data 110 from the registers 72 each time during a plurality of third readout periods 156, each third readout period 156 following a third data acquisition periods 152.

[0114] The method may further comprise determining S38 an output count rate 130 based on the second counted data 110.

[0115] The method may further comprise determining S40 an input count rate 132 based on the output count rate 130.

[0116] The method may further comprise determining S42, based on the input count rate 132 and for plurality of future frames 144, 148, a first frame frequency of a plurality of first frames 144 and / or a second frame frequency of a plurality of second frames 148.

[0117] The method may further comprise determining S44, based on the input count rate 132 and for the plurality of future frames 144, 148, a relatively high first frame frequency of a plurality of first frames 144 and / or a relatively low second frame frequency of a plurality of second frames 148 when the input count rate 132 is relatively low, and a relatively low first frame frequency of a plurality of first frames 144 and / or a relatively high second frame frequency of a plurality of second frames 148 when the input count rate 132 is relatively high.

[0118] Some embodiments include a method of handling radiation, the method comprising providing S10 a plurality of pixels 24 configured to detect radiation energies of incident radiation; providing S12 a readout circuit 36 comprising at least one register 72, the readout circuit 36 being configured to handle a primary electric signal 46 representative of radiation energy from only a primary pixel 24 with respect to the readout circuit 36 among the plurality of pixels 24; acquiring S14, by the readout circuit 36 in a first mode 78, first counted data 108 based on a charge sharing electric signal 56 representative of a sum of radiation energies from a set 26 of pixels 24 among the primary pixel 24 and at least one secondary pixel 24 with respect to the readout circuit 36 among the plurality of pixels 24, and storing the first counted data 108 in one or more of the at least one register 72, each time during a plurality of first data acquisition periods 140; and acquiring S22, by the readout circuit 36 in a second mode 80, different from the first mode 78, second counted data no based on the primary electric signal 46, and storing the second counted data no in one or more of the at least one register 72, each time during a plurality of second data acquisition periods 142, the first data acquisition periods 140 and the second data acquisition periods 142 being alternating.

[0119] One technical effect provided by the method may be that a reduced amount of data is handled by the readout circuit 36. The method thus includes an alternating acquisition of the first counted data 108 in the first data acquisition periods 140 and the second counted data no in the second data acquisition periods 142. For example, every i'th data acquisition period may be a first data acquisition period 140, and every (i+j)'th data acquisition period maybe a second data acquisition period 142, where i is a positive integer of at least two, and j is a positive integer.

[0120] The data acquisition with respect to charge sharing may be different in the first and second modes 78, 80. For example, charge sharing maybe performed by the readout circuit 36 in the first mode 78 in each first data acquisition period 140, and charge sharing may not be performed by the readout circuit 36 in the second mode 80 in each second data acquisition period 142. Thus, each first data acquisition period 140 may include a data acquisition with CSC and each second data acquisition period 142 may include a data acquisition without CSC.

[0121] The primary electric signal 46 may be representative of single pixel counts for the primary pixels 24. The charge sharing electric signal 56 may be representative of charge sharing corrected counts from the set 26. The method allows for a different handling of CSC in different frames. For example, the method allows for an alternating acquisition of single pixel counts and charge sharing corrected counts in different frames.

[0122] The readout circuit 36 maybe configured to handle a secondary electric signal 50 representative of radiation energy from each of the at least one secondary pixel 24 in order to provide the charge sharing electric signal 56. In the second mode 80, the at least one secondary electric signal 50 and / or the charge sharing electric signal 56 may not be handled by the readout circuit 36. Thus, any provision or reading out of the first counted data 108 can be eliminated in the second mode 80. This enables a reduced handling of data by the readout circuit 36.

[0123] In some embodiments, the method further comprises determining S38 an output count rate 130 based on the second counted data no; determining S40 an input count rate 132 based on the output count rate 130; reading out S20 the first counted data 108 from the one or more registers 72 each time during a plurality of first readout periods 146, each first readout period 146 following a first data acquisition period 140; reading out S28 the second counted data no from the one or more registers 72 each time during a plurality of second readout periods 150, each second readout period 150 following a second data acquisition period 142; and determining S42, based on the input count rate 132 and for plurality of future frames 144, 148, a first frame frequency of a plurality of first frames 144 and / or a second frame frequency of a plurality of second frames 148, where each first frame 144 is constituted by a first data acquisition period 140 and a first readout period 146, and each second frame 148 is constituted by a second data acquisition period 142 and a second readout period 150.

[0124] The method may thus comprise using modes with different CSC settings in different frames. The first frames 144 may be referred to as CSC frames and the second frames 148 may be referred to as non-CSC frames. As an alternative to determining the first and second frame frequencies in this manner, the first and second frame frequencies may be predetermined.

[0125] In some embodiments, the method further comprises determining S44, based on the input count rate 132 and for the plurality of future frames 144, 148, a relatively high first frame frequency of a plurality of first frames 144 and / or a relatively low second frame frequency of a plurality of second frames 148 when the input count rate 132 is relatively low, and a relatively low first frame frequency of a plurality of first frames 144 and / or a relatively high second frame frequency of a plurality of second frames 148 when the input count rate 132 is relatively high. A relatively high frame frequency may be a first frame frequency, and a relatively low frame frequency may be a second frame frequency, lower than the first frame frequency. In some embodiments, the first frame frequency is at least twice the second frame frequency. The relatively low input count rate 132 may be a first input count rate, and the relatively high input count rate 132 maybe a second input count rate, higher than the first input count rate.

[0126] In some embodiments, each first data acquisition period 140 comprises comparing S16, by a comparator 66 in the readout circuit 36, the charge sharing electric signal 56 with a threshold value 68; and counting S18, by a counter 70 in the readout circuit 36, comparator data 128 associated with the comparator 66 to acquire the first counted data 108. In these embodiments, each second data acquisition period 142 may comprise comparing S24, by the comparator 66, the primary electric signal 46 with the threshold value 68; and counting S26, by the counter 70, comparator data 128 associated with the comparator 66 to acquire the second counted data no. Thus, the same comparator 66 may be used in each first data acquisition period 140 to compare the charge sharing electric signal 56 with the threshold value 68, and in each second data acquisition period 142 to compare the primary electric signal 46 with the same threshold value 68. The reconstruction, e.g., of a three-dimensional image, is made easier if the one or more used threshold values 68 are the same in both the first and second modes 78, 80.

[0127] In some embodiments, at least one common register 72 among the at least one register 72 is used both to store the first counted data 108 each time during the first data acquisition periods 140, and to store the second counted data no each time during the second data acquisition periods 142. One technical effect may include that a number of registers 72 in the readout circuit 36 can be reduced.

[0128] In some embodiments, two or more first data acquisition periods 140 are provided between a preceding second data acquisition period 142 and a succeeding second data acquisition period 142. Also in these cases, the first data acquisition periods 140 and the second data acquisition periods 142 are alternating.

[0129] In some embodiments, two or more second data acquisition periods 142 are provided between a preceding first data acquisition period 140 and a succeeding first data acquisition period 140. Also in these cases, the first data acquisition periods 140 and the second data acquisition periods 142 are alternating.

[0130] In some embodiments, the readout circuit 36 comprises at least two registers 72, wherein the at least two registers 72 comprise a first register group 86 and a second register group 88, each including at least one of the at least two registers 72. In these cases, the method may further comprise acquiring S30, by the readout circuit 36 in a third mode 92, first counted data 108 and storing the first counted data 108 in one or more of the registers 72 in the first register group 86, and acquiring, by the readout circuit 36 in the third mode 92, second counted data 110 and storing the second counted data no in one or more of the registers 72 in the second register group 88, each time during a plurality of third data acquisition periods 152.

[0131] The third mode 92 is different from each of the first and second modes 78, 80. The method may further comprise reading out S36 the first counted data 108 and the second counted data no each time during a plurality of third readout periods 156, each third readout period 156 following a third data acquisition period 152.

[0132] The method of these embodiments may thus include an alternating acquisition of the first counted data 108 in the first data acquisition periods 140, the second counted data 110 in the second data acquisition periods 142, and the first counted data 108 and the second counted data 110 in the third data acquisition periods 152. For example, every i'th data acquisition period maybe a first data acquisition period 140, every (i+j)'th data acquisition period maybe a second data acquisition period 142, and every (i+k)'th data acquisition period may be a third data acquisition period 152, where i is a positive integer of at least two, and where each of j and k is a positive integer.

[0133] A third frame 154 may be constituted by a third data acquisition period 152 and a third readout period 156. The third frame 154 may be referred to a combined frame, i.e., a combination of a CSC frame and a non-CSC frame.

[0134] Some embodiments include a readout circuit 36 for a radiation detector 12 comprising a plurality of pixels 24 configured to detect radiation energies of incident radiation, the readout circuit 36 comprising at least one register 72; a primary electric line 48 arranged to receive a primary electric signal 46 representative of radiation energy from only a primary pixel 24 with respect to the readout circuit 36 among the plurality of pixels 24; at least one secondary electric line 52 arranged to receive a secondary electric signal 50 representative of radiation energy from a secondary pixel 24 with respect to the readout circuit 36 among the plurality of pixels 24; at least one tertiary electric line 62, 84 associated with the at least one register 72; a summing device 54 arranged to receive two or more among the primary electric signal 46 from the primary electric line 48 and each secondary electric signal 50 from the at least one secondary electric line 52, and to output a charge sharing electric signal 56 to the at least one tertiary electric line 62, 84, the charge sharing electric signal 56 being representative of a sum of radiation energies from a set 26 of pixels 24 among the primary pixel 24 and the at least one secondary pixel 24; and a switch arrangement 58 configured to adopt a first state 60 where the charge sharing electric signal 56 is output to the at least one tertiary electric line 62, 84, and a second state 82 where the primary electric signal 46 is output to the at least one tertiary electric line 62, 84.

[0135] In some embodiments, the at least one secondary pixel 24 is neighboring to the primary pixel 24.

[0136] In some embodiments, the readout circuit 36 further comprises a comparator 66 configured to compare an electric signal in the at least one tertiary electric line 62, 84 with a threshold value 68. In some embodiments a single comparator 66 is used to compare the charge sharing electric signal 56 with the threshold value 68 in the first state 60, and to compare the primary electric signal 46 with the threshold value 68 in the second state 82.

[0137] In some embodiments, the readout circuit 36 further comprises a counter 70 configured to count comparator data 128 associated with the comparator 66 to acquire counted data 108, no.

[0138] In some embodiments, one of the at least one register 72 is associated with the counter 70 and is configured to store the counted data 108, no.

[0139] In some embodiments, the at least one register 72 comprises at least two registers 72, the at least two registers 72 comprising a first register group 86 and a second register group 88, each including at least one of the at least two registers 72. In these cases, the at least one tertiary electric line 62, 84 may comprise a first tertiary electric line 62 and a second tertiary electric line 84; and the switch arrangement 58 maybe configured to adopt a third state 90 where the charge sharing electric signal 56 is output to the first tertiary electric line 62 and the primary electric signal 46 is output to the second tertiary electric line 84.

[0140] In some embodiments where a same comparator 66 is used to compare the charge sharing electric signal 56 with the threshold value 68 in the first state 60, and to compare the primary electric signal 46 with the threshold value 68 in the second state 82, the same comparator 66 may also be used to compare either the charge sharing electric signal 56 or the primary electric signal 46 with the threshold value 68 in the third state 90.

[0141] Some embodiments include a radiation detector 12 comprising the plurality of pixels 24 and at least one readout circuit 36 according to the present disclosure. In these cases, each readout circuit 36 maybe associated with a unique pixel 24 among the plurality of pixels 24.

[0142] Some embodiments include an imaging apparatus 10 comprising a radiation detector 12 according to the present disclosure.

[0143] In some embodiments, the imaging apparatus 10 further comprises a control system 14 including at least one data processing device 20 and at least one memory 22 having at least one computer program stored thereon.

[0144] In some embodiments, the at least one computer program comprises program code which, when executed by the at least one data processing device 20, causes the at least one data processing device 20 to, for each readout circuit 36 control the switch arrangement 58 to adopt the first state 60 each time during a plurality of first data acquisition periods 140 such that first counted data 108 is acquired based on the charge sharing electric signal 56; and control the switch arrangement 58 to adopt the second state 82 each time during a plurality of second data acquisition periods 142 such that second counted data no is acquired based on the primary electric signal 46, the first data acquisition periods 140 and the second data acquisition periods 142 being alternating. In some embodiments, the at least one computer program comprises program code which, when executed by the at least one data processing device 20, causes the at least one data processing device 20 to, for at least one of the readout circuits 36 determine an output count rate 130 based on the second counted data no; determine an input count rate 132 based on the output count rate 130; command read out of the first counted data 108 from the one or more registers 72 each time during a plurality of first readout periods 146, each first readout period 146 following a first data acquisition period 140; command read out of the second counted data no from the one or more registers 72 each time during a plurality of second readout periods 150, each second readout period 150 following a second data acquisition period 142; and determine, based on the input count rate 132 and for plurality of future frames 144, 148, a first frame frequency of a plurality of first frames 144 and / or a second frame frequency of a plurality of second frames 148, where each first frame 144 is constituted by a first data acquisition period 140 and a first readout period 146, and each second frame 148 is constituted by a second data acquisition period 142 and a second readout period 150.

[0145] In some embodiments, the at least one computer program comprises program code which, when executed by the at least one data processing device 20, causes the at least one data processing device 20 to, for the at least one of the readout circuits 36 determine, based on the input count rate 132 and for the plurality of future frames 144, 148, a relatively high first frame frequency of a plurality of first frames 144 and / or a relatively low second frame frequency of a plurality of second frames 148 when the input count rate 132 is relatively low, and a relatively low first frame frequency of a plurality of first frames 144 and / or a relatively high second frame frequency of a plurality of second frames 148 when the input count rate 132 is relatively high.

[0146] In some embodiments, each readout circuit 36 is configured to use at least one common register 72 among the at least one register 72 both to store the first counted data 108 each time during the first data acquisition periods 140, and to store the second counted data no each time during the second data acquisition periods 142.

[0147] In some embodiments, two or more first data acquisition periods 140 are provided between a preceding second data acquisition period 142 and a succeeding second data acquisition period 142.

[0148] In some embodiments, two or more second data acquisition periods 142 are provided between a preceding first data acquisition period 140 and a succeeding first data acquisition period 140.

[0149] In some embodiments, the radiation detector 12 comprises at least one readout circuit 36 according to claim 14, and wherein the at least one computer program comprises program code which, when executed by the at least one data processing device 20, causes the at least one data processing device 20 to, for the at least one readout circuit 36: control the switch arrangement 58 to adopt the third state 90 each time during a plurality of third data acquisition periods 152 such that first counted data 108 is acquired based on the charge sharing electric signal 56 in the first tertiary electric line 62 and second counted data no is acquired based on the primary electric signal 46 in the second tertiary electric line 84.

[0150] While the present disclosure has been described with reference to exemplary embodiments, it will be appreciated that the present invention is not limited to what has been described above. For example, it will be appreciated that the dimensions of the parts maybe varied as needed. Accordingly, it is intended that the present invention may be limited only by the scope of the claims appended hereto.

Claims

CLAIMS1. A method of handling radiation, the method comprising:- providing (Sio) a plurality of pixels (24) configured to detect radiation energies of incident radiation;- providing (S12) a readout circuit (36) comprising at least one register (72), the readout circuit (36) being configured to handle a primary electric signal (46) representative of radiation energy from only a primary pixel (24) with respect to the readout circuit (36) among the plurality of pixels (24);- acquiring (S14), by the readout circuit (36) in a first mode (78), first counted data (108) based on a charge sharing electric signal (56) representative of a sum of radiation energies from a set (26) of pixels (24) among the primary pixel (24) and at least one secondary pixel (24) with respect to the readout circuit (36) among the plurality of pixels (24), and storing the first counted data (108) in one or more of the at least one register (72), each time during a plurality of first data acquisition periods (140); and- acquiring (S22), by the readout circuit (36) in a second mode (80), different from the first mode (78), second counted data (110) based on the primary electric signal (46), and storing the second counted data (no) in one or more of the at least one register (72), each time during a plurality of second data acquisition periods (142), the first data acquisition periods (140) and the second data acquisition periods (142) being alternating.

2. The method according to claim 1, further comprising:- determining (S38) an output count rate (130) based on the second counted data (no);- determining (S40) an input count rate (132) based on the output count rate (130);- reading out (S20) the first counted data (108) from the one or more registers (72) each time during a plurality of first readout periods (146), each first readout period (146) following a first data acquisition period(140);- reading out (S28) the second counted data (110) from the one or more registers (72) each time during a plurality of second readout periods (150), each second readout period (150) following a second data acquisition period (142); and- determining (S42), based on the input count rate (132) and for plurality of future frames (144, 148), a first frame frequency of a plurality of first frames (144) and / or a second frame frequency of a plurality of second frames (148), where each first frame (144) is constituted by a first data acquisition period (140) and a first readout period (146), and each second frame (148) is constituted by a second data acquisition period (142) and a second readout period (150).

3. The method according to claim 2, further comprising determining (S44), based on the input count rate (132) and for the plurality of future frames (144, 148), a relatively high first frame frequency of a plurality of first frames (144) and / or a relatively low second frame frequency of a plurality of second frames (148) when the input count rate (132) is relatively low, and a relatively low first frame frequency of a plurality of first frames (144) and / or a relatively high second frame frequency of a plurality of second frames (148) when the input count rate (132) is relatively high.

4. The method according to any of the preceding claims, wherein each first data acquisition period (140) comprises:- comparing (S16), by a comparator (66) in the readout circuit (36), the charge sharing electric signal (56) with a threshold value (68); and- counting (S18), by a counter (70) in the readout circuit (36), comparator data (128) associated with the comparator (66) to acquire the first counted data (108); and wherein each second data acquisition periods (142) comprises:- comparing (S24), by the comparator (66), the primary electric signal (46) with the threshold value (68); and- counting (S26), by the counter (70), comparator data (128) associated with the comparator (66) to acquire the second counted data (110).

5. The method according to any of the preceding claims, wherein at least one common register (72) among the at least one register (72) is used both to store the first counted data (108) each time during the first data acquisition periods (140), and to store the second counted data (110) each time during the second data acquisition periods (142).

6. The method according to any of the preceding claims, wherein two or more first data acquisition periods (140) are provided between a preceding second data acquisition period (142) and a succeeding second data acquisition period (142).

7. The method according to any of the preceding claims, wherein two or more second data acquisition periods (142) are provided between a preceding first data acquisition period (140) and a succeeding first data acquisition period (140).

8. The method according to any of the preceding claims, wherein the readout circuit (36) comprises at least two registers (72), wherein the at least two registers (72) comprise a first register group (86) and a second register group (88), each including at least one of the at least two registers (72), and wherein the method further comprises:- acquiring (S30), by the readout circuit (36) in a third mode (92), first counted data (108) and storing the first counted data (108) in one or more of the registers (72) in the first register group (86), and acquiring, by the readout circuit (36) in the third mode (92), second counted data (no) and storing the second counted data (no) in one or more of the registers (72) in the second register group (88), each time during a plurality of third data acquisition periods (152).

9. A readout circuit (36) for a radiation detector (12) comprising a plurality of pixels (24) configured to detect radiation energies of incident radiation, the readout circuit (36) comprising:- at least one register (72);- a primary electric line (48) arranged to receive a primary electric signal (46) representative of radiation energy from only a primary pixel (24) with respect to the readout circuit (36) among the plurality of pixels (24);- at least one secondary electric line (52) arranged to receive a secondary electric signal (50) representative of radiation energy from a secondary pixel (24) with respect to the readout circuit (36) among the plurality of pixels (24);- at least one tertiary electric line (62, 84) associated with the at least one register (72);- a summing device (54) arranged to receive two or more among the primary electric signal (46) from the primary electric line (48) and each secondary electric signal (50) from the at least one secondary electric line (52), and to output a charge sharing electric signal (56) to the at least one tertiary electric line (62, 84), the charge sharing electric signal (56) being representative of a sum of radiation energies from a set (26) of pixels (24) among the primary pixel (24) and the at least one secondary pixel (24); and- a switch arrangement (58) configured to adopt a first state (60) where the charge sharing electric signal (56) is output to the at least one tertiary electric line (62, 84), and a second state (82) where the primary electric signal (46) is output to the at least one tertiary electric line (62, 84).

10. The readout circuit (36) according to claim 9, wherein the at least one secondary pixel (24) is neighboring to the primary pixel (24).

11. The readout circuit (36) according to claim 9 or 10, further comprising a comparator (66) configured to compare an electric signal in the at least one tertiary electric line (62, 84) with a threshold value (68).

12. The readout circuit (36) according to claim 11, further comprising a counter (70) configured to count comparator data (128) associated with the comparator (66) to acquire counted data (108, no).

13. The readout circuit (36) according to claim 12, wherein one of the at least one register (72) is associated with the counter (70) and is configured to store the counted data (108, no).

14. The readout circuit (36) according to any of claims 9 to 13, wherein the at least one register (72) comprises at least two registers (72), the at least two registers (72) comprising a first register group (86) and a second register group (88), each including at least one of the at least two registers (72); wherein the at least one tertiary electric line (62, 84) comprises a first tertiary electric line (62) and a second tertiary electric line (84); and wherein the switch arrangement (58) is configured to adopt a third state (90) where the charge sharing electric signal (56) is output to the first tertiary electric line (62) and the primary electric signal (46) is output to the second tertiary electric line (84).

15. A radiation detector (12) comprising the plurality of pixels (24) and at least one readout circuit (36) according to any of claims 9 to 14, where each readout circuit (36) is associated with a unique pixel (24) among the plurality of pixels (24).

16. An imaging apparatus (10) comprising a radiation detector (12) according to claim 15.

17. The imaging apparatus (10) according to claim 16, further comprising a control system (14) including at least one data processing device (20) and at least one memory (22) having at least one computer program stored thereon.

18. The imaging apparatus (10) according to claim 17, wherein the at least one computer program comprises program code which, when executedby the at least one data processing device (20), causes the at least one data processing device (20) to, for each readout circuit (36):- control the switch arrangement (58) to adopt the first state (60) each time during a plurality of first data acquisition periods (140) such that first counted data (108) is acquired based on the charge sharing electric signal (56); and- control the switch arrangement (58) to adopt the second state (82) each time during a plurality of second data acquisition periods (142) such that second counted data (110) is acquired based on the primary electric signal (46), the first data acquisition periods (140) and the second data acquisition periods (142) being alternating.

19. The imaging apparatus (10) according to claim 18, wherein the at least one computer program comprises program code which, when executed by the at least one data processing device (20), causes the at least one data processing device (20) to, for at least one of the readout circuits (36):- determine an output count rate (130) based on the second counted data (110);- determine an input count rate (132) based on the output count rate (130);- command read out of the first counted data (108) from the one or more registers (72) each time during a plurality of first readout periods (146), each first readout period (146) following a first data acquisition period (140);- command read out of the second counted data (110) from the one or more registers (72) each time during a plurality of second readout periods (150), each second readout period (150) following a second data acquisition period (142); and- determine, based on the input count rate (132) and for plurality of future frames (144, 148), a first frame frequency of a plurality of first frames (144) and / or a second frame frequency of a plurality of second frames (148), where each first frame (144) is constituted by a first dataacquisition period (140) and a first readout period (146), and each second frame (148) is constituted by a second data acquisition period (142) and a second readout period (150).

20. The imaging apparatus (10) according to claim 19, wherein the at least one computer program comprises program code which, when executed by the at least one data processing device (20), causes the at least one data processing device (20) to, for the at least one of the readout circuits (36) determine, based on the input count rate (132) and for the plurality of future frames (144, 148), a relatively high first frame frequency of a plurality of first frames (144) and / or a relatively low second frame frequency of a plurality of second frames (148) when the input count rate (132) is relatively low, and a relatively low first frame frequency of a plurality of first frames (144) and / or a relatively high second frame frequency of a plurality of second frames (148) when the input count rate (132) is relatively high.

21. The imaging apparatus (10) according to any of claims 18 to 20, wherein each readout circuit (36) is configured to use at least one common register (72) among the at least one register (72) both to store the first counted data (108) each time during the first data acquisition periods (140), and to store the second counted data (110) each time during the second data acquisition periods (142).

22. The imaging apparatus (10) according to any of claims 18 to 21, wherein two or more first data acquisition periods (140) are provided between a preceding second data acquisition period (142) and a succeeding second data acquisition period (142).

23. The imaging apparatus (10) according to any of claims 18 to 22, wherein two or more second data acquisition periods (142) are provided between a preceding first data acquisition period (140) and a succeeding first data acquisition period (140).

24. The imaging apparatus (10) according to any of claims 17 to 23, wherein the radiation detector (12) comprises at least one readout circuit (36) according to claim 14, and wherein the at least one computer program comprises program code which, when executed by the at least one data processing device (20), causes the at least one data processing device (20) to, for the at least one readout circuit (36):- control the switch arrangement (58) to adopt the third state (90) each time during a plurality of third data acquisition periods (152) such that first counted data (108) is acquired based on the charge sharing electric signal (56) in the first tertiary electric line (62) and second counted data(no) is acquired based on the primary electric signal (46) in the second tertiary electric line (84).