Semiconductor device and method for manufacturing the same, and display device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof and a display device and a manufacturing method thereof. The semiconductor device includes: an insulating substrate; a polysilicon layer; a first gate insulating layer; a first metal layer; an oxide semiconductor layer; a second gate insulating layer; a second metal layer; a first interlayer insulating layer; a third metal layer; a first thin film transistor, which uses the polysilicon layer as a channel and has a source, a drain and a gate; and a second thin film transistor, which uses the oxide semiconductor layer as a channel and has a source, a drain and a gate, the gate of the first thin film transistor is composed of the first metal layer, the gate of the second thin film transistor is composed of the second metal layer, the source and drain of the first thin film transistor and the source and drain of the second thin film transistor are composed of the third metal layer, and the source or drain of the first thin film transistor and the gate of the second thin film transistor are electrically connected to each other.

Description

Technical Field

[0001] The present application relates to a semiconductor device, a display device, a method for manufacturing a semiconductor device, and a method for manufacturing a display device. Background Art

[0002] In display devices such as organic electroluminescent display devices and liquid crystal display devices, thin film transistors (TFTs) are used in pixel circuits. Examples of thin film transistors include a-Si (amorphous silicon) thin film transistors, low temperature polycrystalline silicon (LTPS) thin film transistors, and thin film transistors using oxide semiconductor films.

[0003] An a-Si thin film transistor is a thin film transistor including a-Si in an active layer. An LTPS thin film transistor is a thin film transistor including LTPS in an active layer. An oxide thin film transistor is a thin film transistor including an oxide semiconductor in an active layer.

[0004] Here, the characteristics between the LTPS thin film transistor and the oxide thin film transistor are compared, and the following differences are observed. The LTPS thin film transistor requires a long channel length, which increases the occupied area. In contrast, the oxide thin film transistor can have a short channel length, which reduces the occupied area. The LTPS thin film transistor has a hysteresis in the source-drain current for the gate voltage. In contrast, the oxide thin film transistor has a slight hysteresis. The LTPS thin film transistor has a high switching performance. In contrast, the oxide thin film transistor has a low switching performance.

[0005] In recent years, the following semiconductor device has been proposed: utilizing the characteristics of the two thin film transistors, the LTPS thin film transistor and the oxide thin film transistor, and simultaneously installing both the LTPS thin film transistor and the oxide thin film transistor. For example, U.S. Unexamined Patent Application Publication No. 2015 / 0055051 proposes a semiconductor device in which the LTPS thin film transistor and the oxide thin film transistor are installed on a pixel circuit, and a display device including the semiconductor device.

[0006] However, in the related art such as US Unexamined Patent Application Publication No. 2015 / 0055051, the gate insulating layer of the LTPS thin film transistor and the gate insulating layer of the oxide thin film transistor are formed of the same layer. This causes the following problem.

[0007] In the manufacturing steps of LTPS thin-film transistors, usually, after forming the gate, an activation step and a hydrogenation step are performed. In the activation step or the hydrogenation step, hydrogen with small atomic and molecular sizes can easily diffuse into the gate insulating layer and reach the polysilicon film formed below the gate insulating layer. The hydrogen reaching the polysilicon film terminates the dangling bond defects on the polysilicon film or the interface. This stabilizes the characteristics of the LTPS thin-film transistor. Similarly, by diffusing hydrogen, the oxide semiconductor layer of the oxide thin-film transistor is exposed to a hydrogen atmosphere in the hydrogenation step. Hydrogen has the effect of reducing oxide semiconductors. Then, a high density of oxygen vacancies is generated in the oxide semiconductor. The oxygen vacancies are used as donors, thereby inducing high density carriers in the oxide semiconductor. This results in a reduction in the resistance value of the oxide semiconductor layer. Thus, the oxide thin-film transistor formed shows a normally-on characteristic. Normally-on means that the drain current flows when no voltage is applied to the gate of the transistor and it maintains the on-state of the transistor. In the case where oxide thin film transistors are used for applications where normally-on is not preferred, devices showing normally-on characteristics will be defective products, which may lead to a decrease in the productivity of semiconductor devices. Summary of the invention

[0008] One aspect of the present invention is to provide a semiconductor device and the like in which a decrease in productivity is suppressed.

[0009] According to one aspect, a semiconductor device includes: an insulating substrate; a polysilicon layer formed on the insulating substrate; a first gate insulating layer formed on the polysilicon layer; a first metal layer formed on the first gate insulating layer; an oxide semiconductor layer formed on the first gate insulating layer; a second gate insulating layer formed on the oxide semiconductor layer; a second metal layer formed on the second gate insulating layer; a first interlayer insulating layer formed on the second metal layer; a third metal layer formed on the first interlayer insulating layer; a first top-gate planar thin film transistor using the polysilicon layer as a channel and having a source electrode , drain and gate; and a second top-gate planar self-aligned thin film transistor, which uses the oxide semiconductor layer as a channel and has a source, a drain and a gate, wherein the gate of the first top-gate planar thin film transistor is composed of the first metal layer, the gate of the second top-gate planar self-aligned thin film transistor is composed of the second metal layer, the source and drain of the first top-gate planar thin film transistor and the source and drain of the second top-gate planar self-aligned thin film transistor are composed of the third metal layer, and the source or drain of the first top-gate planar thin film transistor and the gate of the second top-gate planar self-aligned thin film transistor are electrically connected to each other.

[0010] According to one aspect of the present invention, a decrease in productivity is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a schematic structure of an organic EL display device;

[0012] Figure 2 is a circuit diagram showing an example of a pixel driving circuit provided for each pixel;

[0013] Figure 3 is a top view showing a structural example of a semiconductor device included in a pixel driving circuit;

[0014] Figure 4 is along Figure 3 A cross-sectional view taken along section line IV-IV;

[0015] Figure 5 is along Figure 3 The sectional view taken along the section line V-V in FIG.

[0016] Figure 6 is a flow chart showing a manufacturing process of a semiconductor device;

[0017] 7A to 7C is a cross-sectional view showing a manufacturing process of a semiconductor device;

[0018] FIG. 8A to FIG. 8C is a cross-sectional view showing a manufacturing process of a semiconductor device;

[0019] Fig. 9A and Fig. 9B is a cross-sectional view showing a manufacturing process of a semiconductor device;

[0020] FIG. 10A to FIG. 10C is a cross-sectional view showing a manufacturing process of a semiconductor device according to Embodiment 2;

[0021] FIG. 11A to FIG. 11C is a cross-sectional view showing a manufacturing process of a semiconductor device according to Embodiment 2;

[0022] Fig. 12A and Fig. 12B is a cross-sectional view showing a manufacturing process of a semiconductor device according to Embodiment 2;

[0023] FIG. 13A to FIG. 13C This is the analysis result showing the element concentration in the depth direction based on SIMS analysis.

[0024] Graph of

[0025] Fig.14 is a top view showing a structural example of a semiconductor device included in a pixel driving circuit;

[0026] Fig.15 is along Fig.14 The sectional view taken along the section line XV-XV in FIG.

[0027] Fig.16 is a flow chart showing a manufacturing process of a semiconductor device;

[0028] FIG. 17A to FIG. 17D is a cross-sectional view showing a manufacturing process of a semiconductor device;

[0029] 18A to 18C is a cross-sectional view showing a manufacturing process of a semiconductor device;

[0030] Fig.19A and Fig.19B is a cross-sectional view showing a manufacturing process of a semiconductor device;

[0031] Fig. 20 is a cross-sectional view showing a structural example of a semiconductor device according to a fourth embodiment; and

[0032] Fig.21 is a cross-sectional view showing a structural example of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION

[0033] The embodiments are described in detail below with reference to the accompanying drawings. In addition, the ordinal numbers such as "first" and "second" in the specification and claims are marked to clarify the relationship between the elements and prevent confusion of the elements. Therefore, these ordinal numbers are not intended to limit the number of elements.

[0034] In addition, the term "connected" means that the connected elements are electrically connected to each other. The expression "electrically connected" also includes the case where the elements are connected through electrical elements such as electrodes, wiring, resistors or capacitors.

[0035] The expression "on the insulating layer" is used to clearly indicate the direction in which the layers are stacked, and does not necessarily mean that the element is adjacent to the insulating layer. For example, the expression "forming an oxide semiconductor layer on the first gate insulating layer" includes the case where the first gate insulating layer and the oxide semiconductor layer are adjacent to each other, and the case where the first gate insulating layer and the oxide semiconductor layer are arranged with another layer interposed therebetween. In addition, "above" indicates the upward direction in the figure.

[0036] The size and ratio of each component in the figure are appropriately changed to ensure the visibility of the figure. In addition, the shaded parts in the figure are intended to distinguish each component from each other and do not necessarily represent cross sections.

[0037] The cross-sectional views showing the stacked state are for showing the stacking order, and the thickness and size of each layer and the relationship between the thicknesses (size relationship) of each layer are not limited to those shown in the drawings.

[0038] Hereinafter, a pixel driving circuit in an organic EL display device will be described as an application example of the semiconductor device. Figure 1 2 is a block diagram showing a schematic configuration of an organic EL display device 1 . The organic EL display device 1 includes a display panel 100 and a drive circuit 20 .

[0039] An image is displayed on the display panel 100. The display panel 100 is driven by an active matrix. The display panel 100 has a pixel array unit. The pixel array unit includes a plurality of pixels 10. The pixels 10 are arranged in a matrix. Each pixel 10 corresponds to any one of the pixels of red (R), green (G), blue (B) and white (W), for example. Each pixel 10 includes an organic EL element.

[0040] The pixel array unit includes a power line VL and a plurality of scan lines SL and a signal line (data line) DL. The plurality of scan lines SL are arranged, for example, along the row direction of the pixel array unit. The plurality of signal lines DL are arranged, for example, along the column direction of the pixel array unit. The power line VL is arranged along each signal line DL. One end of each of the scan lines SL, the signal lines DL and the power line VL is connected to the drive circuit 20. Each pixel 10 is arranged to correspond to the intersection of each scan line SL and each signal line DL.

[0041] The driving circuit 20 drives the pixel array unit to display, and includes a video signal processing circuit 21 , a timing generation circuit 22 , a scan line driving circuit 23 , a signal line driving circuit 24 , and a power line driving circuit 25 .

[0042] The video signal processing circuit 21 performs gamma correction or overdrive correction on a digital video signal 21A input from the outside, and outputs the corrected video signal to the signal line driving circuit 24 .

[0043] The timing generation circuit 22 generates a control signal 22A based on the externally input synchronization signal 20B and outputs the generated control signal 22A. The control signal 22A is used to control the scanning line driving circuit 23, the signal line driving circuit 24 and the power line driving circuit 25 so that these circuits operate in coordination with each other.

[0044] The scanning line driving circuit 23 sequentially applies a scanning line voltage to the plurality of scanning lines SL according to the control signal 22A. The application of the scanning line voltage allows the pixels 10 to be sequentially selected.

[0045] The signal line driving circuit 24 generates an analog video signal corresponding to the video signal input from the video signal processing circuit 21 based on the control signal 22A. The generated analog video signal is applied to each signal line DL.

[0046] The power line driving circuit 25 sequentially applies a power voltage to a plurality of power lines VL according to the control signal 22A. The power voltage controls the light emission and extinction of each organic EL element.

[0047] The drive circuit 20 controls each pixel 10 as follows. The pixel 10 is selected according to the control signal 22A output from the scan line drive circuit 23. A video signal voltage based on the analog video signal output from the signal line drive circuit 24 is written to the selected pixel. In addition, writing of the video signal means applying a predetermined voltage between the gate and source of the drive transistor described below.

[0048] Figure 2 is a circuit diagram showing an example of a pixel driving circuit provided for each pixel. The pixel driving circuit includes an organic EL element 14 as a light-emitting element, a first transistor 11, a second transistor 12, and a storage capacitor 13. The anode of the organic EL element 14 is connected to the source of the second transistor 12 and one end of the storage capacitor 13. The cathode of the organic EL element 14 is connected to the power ground terminal. The other end of the storage capacitor 13 is connected to the drain of the first transistor 11. The other end of the storage capacitor 13 is also connected to the gate of the second transistor 12. The drain of the second transistor 12 is connected to the power line VL. The source of the first transistor 11 is connected to the signal line DL. The gate of the first transistor 11 is connected to the scan line SL.

[0049] The first transistor 11 is a switching thin film transistor for selecting a pixel. The second transistor 12 is a driving thin film transistor for flowing the current required for the organic EL element 14 to emit light. Regarding writing, when the gate of the first transistor 11 connected to the scanning line SL is turned on, the signal line DL is incorporated into the pixel, and the voltage is written to the storage capacitor 13. Even when the gate of the first transistor 11 is turned off, the voltage written in the storage capacitor controls the second transistor 12 and causes the current of the set value to flow into the organic EL element 14. Thus, the operating state of the organic EL element 14 is maintained until the next writing is performed.

[0050] As described above, in the pixel driving circuit, the first transistor 11 preferably has high switching performance. Also, preferably, the source-drain current characteristic of the second transistor 12 has less hysteresis with respect to the gate voltage. Therefore, in the following embodiments, the first transistor 11 is set as an LTPS thin film transistor, and the second transistor 12 is set as an oxide thin film transistor.

[0051] Implementation Method 1

[0052] Figure 3 1 is a plan view showing a structural example of a semiconductor device 10 included in a pixel driving circuit. Figure 4 is along Figure 3The semiconductor device 110 includes an insulating substrate 101 , a polysilicon layer 111 , a first gate insulating layer 102 , a first metal layer 103 , an oxide semiconductor layer 121 , a second gate insulating layer 104 , a second metal layer 105 , an interlayer insulating layer 106 , and a third metal layer 107 .

[0053] In the semiconductor device 110, the layers are formed in the above-described order on the upper surface of the insulating substrate 101. That is, a polysilicon layer 111 is formed on the insulating substrate 101. A first gate insulating layer 102 is formed on the polysilicon layer 111. A first metal layer 103 and an oxide semiconductor layer 121 are formed on the first gate insulating layer 102. A second gate insulating layer 104 is formed on the first metal layer 103 and the oxide semiconductor layer 121. A second metal layer 105 is formed on the second gate insulating layer 104. An interlayer insulating layer 106 is formed on the second metal layer 105. A third metal layer 107 is formed on the interlayer insulating layer 106.

[0054] The insulating substrate 101 is formed of a material having insulating properties and light transmittance. The material having insulating properties and light transmittance is, for example, glass. The insulating substrate 101 has a plate-like shape. The insulating substrate 101 is, for example, a glass plate. The polysilicon layer 111 is a layer composed of polysilicon, for example, low-temperature polycrystalline silicon (LTPS). The first gate insulating layer 102, the second gate insulating layer 104, and the interlayer insulating layer 106 are formed of an insulating material. The insulating material may be, for example, silicon oxide or silicon nitride. The first metal layer 103, the second metal layer 105, and the third metal layer 107 are formed of a conductive metal. The conductive metal may be, for example, aluminum, tantalum, molybdenum tantalum, or molybdenum tungsten. The oxide semiconductor layer 121 is a layer containing an oxide semiconductor. The oxide semiconductor is, for example, InGaZnO.

[0055] In the semiconductor device 110, a first transistor 11 and a second transistor 12 are formed. The first transistor 11 and the second transistor 12 are arranged in the wiring direction of the scanning line SL. The first transistor 11 uses the polysilicon layer 111 as a channel. Hereinafter, the polysilicon layer 111 is also referred to as the channel 111. The gate 112 is composed of the first metal layer 103. That is, a part of the first metal layer 103 opposite to the channel 111 is used as the gate 112 of the first transistor 11. The source 113 and the drain 114 of the first transistor 11 are composed of the third metal layer 107. That is, the source 113 is a part of the third metal layer 107. The source 113 is electrically connected to the channel 111 via the contact hole 1131. Similarly, the drain 114 is a part of the third metal layer 107. The drain 114 is electrically connected to the channel 111 via the contact hole 1141. The first transistor 11 is a top gate planar thin film transistor.

[0056] The second transistor 12 uses the oxide semiconductor layer 121 as a channel. The gate 122 is composed of the second metal layer 105. That is, a portion of the second metal layer 105 opposite to the oxide semiconductor (channel) 121 is used as the gate 122. The source 123 and the drain 124 of the second transistor 12 are composed of the third metal layer 107. The second transistor 12 is a top-gate planar self-aligned thin film transistor.

[0057] In the wiring direction of the scanning line SL, a storage capacitor 13 is formed between the first transistor 11 and the second transistor 12 . Figure 5 is along Figure 3 The storage capacitor 13 includes a lower electrode 131 and an upper electrode 132. The lower electrode 131 is formed of the second metal layer 105. The second metal layer 105 including the lower electrode 131 has a planar shape in which the L shape is reversed (an inverted L shape). A portion of the inverted L-shaped portion extending in the wiring direction of the signal line DL corresponds to the gate 122 of the second transistor 12. A portion of the inverted L-shaped portion extending in the wiring direction of the scanning line SL corresponds to the lower electrode 131 of the storage capacitor 13. The portion extending from the lower electrode 131 to the first transistor 11 is connected to the drain 114 of the first transistor 11 via the contact hole 1311. The upper electrode 132 is formed of the third metal layer 107. The upper electrode 132 is integrated with the source 123 of the second transistor 12. A portion of the third metal layer 107 integrated with the upper electrode 132 is provided with a contact hole 141 for electrically connecting the anode of the organic EL element 14 and the upper electrode 132 .

[0058] The signal line DL is formed of the third metal layer 107. The signal line DL is integrated with the source 113 of the first transistor 11. The scan line SL is formed of the first metal layer 103. A portion of the first metal layer 103 has a portion extending in a direction intersecting with the wiring direction of the scan line SL. This portion connects the gate 112 of the first transistor 11 and the scan line SL. The power line VL is formed of the third metal layer 107. The power line VL is integrated with the drain 124 of the second transistor 12.

[0059] Now, the manufacturing process of the semiconductor device 110 will be described. Figure 6 1 is a flowchart showing the manufacturing process of the semiconductor device 110 . 7A to 7C , FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9B It is a cross-sectional view showing the manufacturing process of the semiconductor device 110 . 7A to 7C , FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9B The cross section and Figure 4The cross-sections of the transistors 11 and 12 are the same. The polysilicon manufacturing process (LTPS process) for forming the first transistor 11 and the oxide semiconductor manufacturing process for forming the second transistor 12 are performed simultaneously and in parallel. Figure 6 Steps shown side by side in FIG. 1 imply that they are performed simultaneously. 7A to 7C , FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9B express Figure 6 The completion status after each step in . Figure 6 The structure obtained after the part of the process shown in 7A to 7C , FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9B Shown in.

[0060] First, an insulating substrate 101 is prepared. A polysilicon layer 111 is formed on the insulating substrate 101 (step S1). In step S1, a-Si is deposited on the insulating substrate 101 by, for example, chemical vapor deposition (CVD). The a-Si is crystallized by excimer laser annealing (ELA) to form polysilicon. Thereafter, an island formation step including a photoresist step and an etching step is performed. By performing these steps, an island-shaped polysilicon layer 111 having a predetermined surface area is completed. Thus, a Fig. 7A Status shown.

[0061] The first gate insulating layer 102 is formed on the insulating substrate 101 and the polysilicon layer 111 (step S2). Figure 7B The state shown. The gate 112 of the first transistor 11 is formed on the first gate insulating layer 102 (step S3). In step S3, the first metal layer 103 is deposited by sputtering or the like. The first metal layer 103 is composed of molybdenum (Mo) or a molybdenum alloy such as molybdenum tantalum (MoTa) or molybdenum tungsten (MoW). Next, through a photoresist step, an island-shaped gate 112 is formed. Thus, a Figure 7C Status shown.

[0062] Impurities are doped into the polysilicon layer 111 (step S4). In step S4, the polysilicon layer 111 is doped with impurities while using the gate 112 as a mask. Next, the polysilicon layer 111 is activated (step S5). In step S5, the polysilicon layer 111 is heated. The heating is performed, for example, in an electric furnace. In addition, annealing using an excimer laser can also be used for heating. The heating is performed at a temperature that does not deform the insulating substrate 101. For example, the heating temperature is selected in the range of 300°C to 600°C.

[0063] The polysilicon layer 111 is hydrogenated (step S6). For example, in step S6, plasma hydrogenation is performed. That is, a gas containing hydrogen is flowed into a container that is depressurized to 1 Torr or less by a vacuum pump, thereby generating hydrogen plasma by high-frequency discharge or the like, wherein the polysilicon layer 111 is subjected to heat treatment.

[0064] An oxide semiconductor layer 121 is formed on the first gate insulating layer 102 (step S7). In step S7, an oxide semiconductor is deposited. An island formation step is performed on the deposited oxide semiconductor film. The oxide semiconductor may be, for example, IGZO, which is a compound of indium, gallium, zinc, oxygen, etc. An oxide semiconductor composed of indium (In), tin (Sn), zinc (Zn), and oxygen (O) may be used. Thus, Fig. 8A Status shown.

[0065] The second gate insulating layer 104 is formed (step S8). Figure 8B A portion of the second gate insulating layer 104 is formed on the gate electrode 112 and the oxide semiconductor layer 121 . The other portion of the second gate insulating layer 104 is formed on the first gate insulating layer 102 .

[0066] The gate 122 of the second transistor 12 is formed on the second gate insulating layer 104 (step S9). In step S9, the second metal layer 105 is deposited by sputtering or the like. The second metal layer 105 is composed of molybdenum (Mo) or a molybdenum alloy such as molybdenum tantalum (MoTa) or molybdenum tungsten (MoW). Then, an island-shaped gate 122 is formed by a photoresist step. Thus, a Figure 8C Status shown.

[0067] The interlayer insulating layer 106 is formed (step S10). Fig. 9A A portion of the interlayer insulating layer 106 is formed on the gate electrode 122 , and the other portion of the interlayer insulating layer 106 is formed on the first gate insulating layer 102 .

[0068] Contact holes 1131 and 1141 of the polysilicon layer 111 and contact holes 1231 and 1241 of the oxide semiconductor layer 121 are formed (step S11). The contact holes 1131 and 1141 are holes extending from the upper surface of the interlayer insulating layer 106 to the upper surface of the polysilicon layer 111. The contact holes 1231 and 1241 are holes extending from the upper surface of the interlayer insulating layer 106 to the upper surface of the oxide semiconductor layer 121.

[0069] The source 113 and drain 114 of the first transistor 11 and the source 123 and drain 124 of the second transistor 12 are formed on the interlayer insulating layer 106 (step S12). The source 113 and the drain 114 are connected to the polysilicon layer 111 via contact holes 1131 and 1141, respectively. The source 123 and the drain 124 are connected to the oxide semiconductor layer 121 via contact holes 1231 and 1241, respectively. In step S12, the third metal layer 107 is deposited using a sputtering method or the like. The third metal layer 107 is made of molybdenum (Mo) or an alloy of molybdenum such as molybdenum tantalum (MoTa), molybdenum tungsten (MoW), etc. Thereafter, the source 113, the drain 114, the source 123, and the drain 124 are formed by a photoresist step. Thus, a Fig. 9B Status shown.

[0070] As described above, since the scan line SL is part of the first metal layer 103, the scan line SL is formed in step S3. In addition, since the lower electrode 131 of the storage capacitor 13 is part of the second metal layer 105, the lower electrode 131 is formed in step S9. In addition, since the signal line DL and the power line VL are part of the third metal layer 107, the signal line DL and the power line VL are formed in step S12. The power line VL is integrated with the drain electrode 124.

[0071] Implementation Method 2

[0072] In this embodiment, a structure in which a region with a locally high hydrogen concentration is formed near the interface between the first gate insulating layer 102 and the oxide semiconductor layer 121 is described.

[0073] FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11C and FIG. 12A to FIG. 12B 1 is a cross-sectional view showing a manufacturing process of the semiconductor device 110 according to the second embodiment. As in the first embodiment, a polysilicon layer 111 ( Fig. 10A ), and then, a first gate insulating layer 102 is formed on the insulating substrate 101 and the polysilicon layer 111 ( Fig. 10B In Embodiment 2, the first gate insulating layer 102 is made of SiO x constitute.

[0074] The gate 112 of the first transistor 11 is formed on the first gate insulating layer 102, and the same steps S4 and S5 as above are performed, and then a hydrogenation step ( Fig. 10C In the hydrogenation step, the treatment temperature was 390°C, the hydrogen pressure was 400 Pa, and the RF power density was 1.3 W / cm 2 The hydrogen plasma was irradiated for 15 minutes or 30 minutes.

[0075] After the hydrogenation step, IGZO as the oxide semiconductor layer 121 is sputtered and patterned to form an IGZO layer. In this embodiment, IGZO as the oxide semiconductor layer 121 is deposited to have a film thickness of 70 nm by sputtering. Thereafter, annealing is performed at 400° C. for 1 hour ( Fig.11A ).like Fig.11A As shown in FIG. 1 , a region with a high hydrogen concentration is formed near the interface of the first gate insulating layer 102 or the oxide semiconductor layer 121 on a plane where the gate 112 and the layers at the same level as the gate 112 do not exist. It is speculated that such a layer structure is generated because the gate 112 and the layers at the same level as the gate 112 are difficult to pass through hydrogen plasma.

[0076] The region with high hydrogen concentration is composed of the first gate insulating layer 211 with high hydrogen concentration and the oxide semiconductor layer 212 with high hydrogen concentration. Here, the first gate insulating layer 211 with high hydrogen concentration is formed near the interface with the oxide semiconductor layer 121 in the first gate insulating layer 102, indicating a region (layer) where the hydrogen concentration is locally maximum (locally maximized). In addition, the oxide semiconductor layer 212 with high hydrogen concentration is formed near the interface with the first gate insulating layer 102 in the oxide semiconductor layer 121, indicating a region (layer) where the hydrogen concentration is locally maximum (locally maximized).

[0077] Note that the region with high hydrogen concentration may be formed of either the first gate insulating layer 211 with high hydrogen concentration or the oxide semiconductor layer 212 with high hydrogen concentration, depending on the material of the first gate insulating layer 102 , the material of the oxide semiconductor layer 121 , and the conditions of hydrogenation treatment.

[0078] Next, the second gate insulating layer 104 ( Fig. 11B ), and forming a gate 122 of the second transistor 12 on the second gate insulating layer 104 ( Fig. 11C ).

[0079] In addition, an interlayer insulating layer 106 ( Fig. 12A ), and forming the source 113 and the drain 114 of the first transistor 11 and the source 123 and the drain 124 of the second transistor 12 on the interlayer insulating layer 106 ( Fig. 12B ).

[0080] In order to clarify the detailed distribution of hydrogen concentration, the inventors measured the hydrogen concentration distribution in the depth direction from the surface of the oxide semiconductor layer 121 toward the first gate insulating layer 102 after the hydrogenation step by secondary ion mass spectrometry (SIMS). The SIMS analysis device used for measurement is PHI ADEPT1010. For analysis, an ion beam based on Cs ions (Cs+) accelerated to 3keV is used.

[0081] FIG. 13A to FIG. 13C A graph showing analysis results of element concentrations in the depth direction based on SIMS analysis is shown. Fig.13A This is the analysis result of a sample in which the hydrogen plasma treatment time is zero, which is shown as a comparative example. Fig. 13B This indicates that the sample was treated with hydrogen plasma for 15 minutes. Fig. 13C The horizontal axis in each graph represents the distance from the surface in the depth direction, the vertical axis on the left represents the hydrogen concentration, and the vertical axis on the right represents the counts of Si and InO. The distribution of Si and InO counts can distinguish the IGZO layer from the SiO x Therefore, it can be inferred that there is an IGZO layer and a SiO layer at a depth near where the Si count and the InO count intersect each other. x The interface of the layer. Near the surface, hydrogen, Si, and InO all show high values. This may be caused by contamination during measurement, so it is excluded from the following description.

[0082] Hydrogenated Fig. 13B and Fig. 13C The hydrogen concentration is greater than or equal to 1×10 20 cm -3 The peak value is a peak value with extremely high hydrogen concentration. In addition, it is obvious that the peak exists at a thickness exceeding 40nm. The peak value is greater than or equal to that of, for example, an IGZO layer or SiO x The typical hydrogen concentration value in the layer (1×10 20 cm -3 ~2×10 20 cm -3 ) times the value of .

[0083] In addition, the peak value of the hydrogen concentration corresponds to the depth near the region where the counts of Si and InO intersect. Therefore, the oxide semiconductor layer 212 (IGZO layer) with a high hydrogen concentration and the first gate insulating layer 211 (SiO layer) with a high hydrogen concentration have a high hydrogen concentration. x The region near the interface of the layer has a high hydrogen concentration. It was further found that the peak of the distribution of hydrogen concentration in the depth direction exists at a thickness of about 40 nm near the maximum value.

[0084] On the other hand, the unhydrogenated Fig.13A The oxide semiconductor layer 212 (IGZO layer) and the first gate insulating layer 102 (SiO x There is no peak in hydrogen concentration near the interface with the first gate insulating layer 211 and the second gate insulating layer 212 (layers), and therefore there is neither the first gate insulating layer 211 with high hydrogen concentration nor the oxide semiconductor layer 212 with high hydrogen concentration.

[0085] In addition, the sheet resistance of the oxide semiconductor layers (including the oxide semiconductor layer with a high hydrogen concentration) in these samples was measured. As a result, the sheet resistance of the sample not subjected to hydrogenation treatment was 1.90×10 8 Ω / sq, the sheet resistance of the sample subjected to hydrogenation treatment for 15 minutes is 8.09×10 7 Ω / sq, the sheet resistance of the sample subjected to hydrogenation treatment for 30 minutes is 3.33×10 6 Ω / sq. From these results, it can be seen that as the hydrogenation treatment time increases, the sheet resistance decreases.

[0086] The possible reasons for the decrease in sheet resistance of the oxide semiconductor layer are as follows. Due to the reduction effect of hydrogen, oxygen vacancies are formed in the oxide semiconductor layer 212 with a high hydrogen concentration. As a result, it can be inferred that carriers are generated in the oxide semiconductor layer 212 with a high hydrogen concentration, so that the sheet resistance is reduced. Therefore, the sheet resistance can change according to the hydrogen concentration.

[0087] Measured at FIG. 13A to FIG. 13C The Id-Vg characteristics of the IGZO-TFT prepared under the processing conditions are obtained Fig.13A and Fig. 13B Under the condition of , the drain current (Id) at about 0V starts to increase (the transistor is turned on) when the gate voltage gradually increases. On the other hand, under Fig. 13C Under the condition of , the characteristics of the transistor being turned on at a gate voltage of about -7V are obtained. Fig. 13C The TFT characteristics under the conditions are mainly caused by the generation of excess carriers in the oxide semiconductor layer with a high hydrogen concentration.

[0088] In the Fig. 13C When a transistor prepared under the conditions of is used as a switching element, the drain current value when the gate voltage is 0 V is too high to ensure a sufficient on / off ratio of the transistor. Therefore, such a transistor is difficult to use as a switching element.

[0089] The following findings were obtained from additional experiments. In the hydrogen concentration distribution in the depth direction observed by SIMS measurement, when the peak value of the hydrogen concentration is greater than or equal to 1×10 22 cm -3When the gate voltage at which the TFT starts to turn on is less than or equal to -15V, the TFT cannot be used as a switching element.

[0090] Under the present conditions, in order for the polysilicon (LTPS) TFT as the first transistor 11 to operate in a preferred manner, the time required for the hydrogenation treatment is greater than or equal to 15 minutes. Fig.13A The first transistor 11 prepared under the conditions of Fig. 13B and Fig. 13C The first transistor 11 prepared under the conditions has preferred TFT characteristics.

[0091] Therefore, in order to use the polysilicon thin film transistor as the first transistor 11 and the IGZO-TFT as the second transistor 12 as switching elements, it is desirable that SiO x The peak value of hydrogen concentration near the interface between the layer and the IGZO layer is greater than or equal to 1×10 21 cm -3 and less than 1×10 22 cm -3 When the basic hydrogen concentration is constant (1×10 20 cm -3 ), desirably, the peak value of the hydrogen concentration is greater than or equal to 10 times and less than 100 times.

[0092] More preferably, SiO x The peak value of the hydrogen concentration near the interface between the layer and the IGZO layer is desirably greater than or equal to 1×10 21 cm -3 and less than 8×10 21 cm -3 When the basic hydrogen concentration is constant (1×10 20 cm -3 ), the peak value of the hydrogen concentration is desirably greater than or equal to 10 times and less than 80 times. When the peak value of the hydrogen concentration is under the aforementioned conditions, the TFT characteristics of both the first transistor 11 and the second transistor 12 can be made preferable.

[0093] According to this embodiment, the following effects are achieved. After the hydrogenation step (step S6) included in the step of forming the first transistor 11, an oxide semiconductor layer 121 serving as a channel of the second transistor 12 is formed (step S7). This can reduce the possibility of the oxide semiconductor layer 121 being exposed to hydrogen plasma. If the oxide semiconductor layer 121 is exposed to hydrogen plasma, the oxygen contained in the oxide semiconductor layer 121 reacts with hydrogen. Then, the amount of oxygen contained in the oxide semiconductor layer 121 is reduced. This reduces the resistance of the oxide semiconductor layer 121, so that the second transistor 12 has a normally-on characteristic. However, according to this embodiment, the possibility of the oxide semiconductor layer 121 being exposed to hydrogen plasma is reduced, thereby suppressing the degradation of the characteristics of the oxide semiconductor layer 121. Therefore, it is possible to suppress the second transistor 12 from having a normally-on characteristic. In the case where the oxide thin film transistor is used for a non-preferred purpose of normally-on, a device showing a normally-on characteristic will be a defective product. However, according to this embodiment, the second transistor 14 can be prevented from having a normally-on characteristic, which suppresses the decrease in the productivity of the semiconductor device 110.

[0094] Implementation method 3 (old implementation method 2)

[0095] This embodiment mode relates to a structure in which a second interlayer insulating layer 1041 is formed between the first gate insulating layer 102 and the second gate insulating layer 1042 . Fig.14 1 is a plan view showing a structural example of a semiconductor device 110 included in a pixel driving circuit. Fig.15 is along Fig.14 The sectional view taken along the section line XV-XV. Fig.14 and Fig.15 In, with Figure 3 and Figure 4 Components similar to those of Embodiment 1 shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here.

[0096] In this embodiment, if Fig.15 As shown, a second interlayer insulating layer 1041 is formed on the first gate insulating layer 102 and the first metal layer 103. An oxide semiconductor layer 121 is formed on the second interlayer insulating layer 1041. A second gate insulating layer 1042 is formed on the second interlayer insulating layer 1041 and the oxide semiconductor layer 121. In addition, a second metal layer 105 is formed on the second gate insulating layer 1042. The oxide semiconductor layer 121 in the second transistor 12 is formed on the second interlayer insulating layer 1041. The oxide semiconductor layer 121 and the source 123 are electrically connected to each other via the contact hole 1231. The oxide semiconductor layer 121 and the drain 124 are electrically connected to each other via the contact hole 1241. In this embodiment, the second transistor 12 is a top-gate planar self-aligned thin film transistor.

[0097] Now, the manufacturing process of the semiconductor device 110 will be described. Fig.16 1 is a flowchart showing the manufacturing process of the semiconductor device 110 . FIG. 17A to FIG. 17D , 18A to 18C and FIG. 19A to FIG. 19B It is a cross-sectional view showing the manufacturing process of the semiconductor device 110 . FIG. 17A to FIG. 17D , 18A to 18C and FIG. 19A to FIG. 19B The cross section and Fig.15 The cross section in is similar. Fig.16 In, with Figure 6 Similar processes are indicated by the same step numbers and will not be described again. FIG. 17A to FIG. 17D , 18A to 18C and FIG. 19A to FIG. 19B , no further explanation will be given here. 7A to 7C , FIG. 8A to FIG. 8C and FIG. 9A to FIG. 9B Similar details.

[0098] In this embodiment, after the polysilicon layer 111 included in the first transistor 11 is hydrogenated (step S6), the second interlayer insulating layer 1041 is formed (step S13). Fig.17D Status shown.

[0099] The oxide semiconductor layer 121 is formed on the second interlayer insulating layer 1041 (step S7). Fig.18A The state shown in FIG. A second gate insulating layer 1042 is formed (step S8). Thus, Fig.18B Execute steps S10 to S11 to achieve Fig.19B Status shown.

[0100] In addition to the effects produced in Embodiment 1, this embodiment achieves the following effects. After the polysilicon layer 111 is hydrogenated (step S6), the second interlayer insulating layer 1041 is formed (step S13). Even if hydrogen used for hydrogenation remains by, for example, adhering to the surface of the first gate insulating layer 102, the hydrogen is blocked by the second interlayer insulating layer 1041. As a result, hydrogen hardly diffuses into the oxide semiconductor layer 121. This can suppress the degradation of the characteristics of the oxide semiconductor layer 121.

[0101] Implementation 4

[0102] Embodiment 4 is a specific example based on Embodiment 2. In this embodiment, the first gate insulating layer 112 and the interlayer insulating layer 106 are made of SiO x constitute. Fig.16 The specific processing conditions of the hydrogenation step (step S6) in the process are as follows: the processing temperature is 390°C, the hydrogen pressure is 400Pa, and the RF power density is 1.3W / cm2 The hydrogen plasma irradiation time (hydrogenation treatment time) was set to 15 minutes.

[0103] Fig. 20 1 is a cross-sectional view showing a structural example of a semiconductor device 110 according to Embodiment 4. Fig. 20 As shown, a region where the hydrogen concentration is locally high is formed as a first gate insulating layer 213 with a high hydrogen concentration between the first gate insulating layer 102 and the second interlayer insulating layer 1041 .

[0104] The details of the hydrogen concentration and structure of the first gate insulating layer 213 with a high hydrogen concentration are studied by the following experiments and analysis. In the experiment, SiO is deposited on the insulating substrate 101. x After the film is formed as the first gate insulating layer 102, the gate 112 is formed, impurities are injected, and an activation step is performed. Then, a hydrogenation step is performed. Next, after cleaning with pure water, SiO is deposited by plasma CVD at a substrate temperature of 200°C. x As the second interlayer insulating layer 1041, a film having a thickness of 200 nm was deposited.

[0105] The first gate insulating layer 213 with a high hydrogen concentration is also observed in a region where the gate electrode 112 and a layer at the same level as the gate electrode 112 are not present.

[0106] Using the sample prepared as described above, SIMS was used to measure the x The surface of the second interlayer insulating layer 1041 is made of SiO x The hydrogen concentration distribution in the depth direction of the first gate insulating layer 102 is constructed to find that a region with a locally high hydrogen concentration exists in the interface region between the first gate insulating layer 102 and the second interlayer insulating layer 1041 .

[0107] It was found that the peak value of hydrogen concentration in this region was equivalent to greater than or equal to 1×10 21 cm -3 , which is greater than or equal to the first gate insulating layer 102 (SiO x ) or the second interlayer insulating layer 1041 (SiO x ) in a typical hydrogen concentration (1×10 20 cm -3 Up to 2×10 20 cm -3 ) times the value of .

[0108] According to the present embodiment, the second transistor 12 is not affected by the hydrogen concentration and can operate in a preferred manner.

[0109] Implementation method 5

[0110] In Embodiment 5, it is described that Fig.16 The manufacturing process shown is an example in which the hydrogenation step of step S6 and the step of forming the second interlayer insulating layer 1041 of step S13 are switched with each other.

[0111] Fig.21 1 is a cross-sectional view showing an example of the structure of a semiconductor device 110 according to Embodiment 5. Fig.21 As shown, a region with high hydrogen concentration exists at the interface between the second interlayer insulating layer 1041 and the oxide semiconductor layer 121. After forming the source 123 and the drain 124 of the second transistor 12, IGZO is formed as the oxide semiconductor layer 121, and then annealing is performed at 400° C. under atmospheric pressure for 1 hour.

[0112] Thus, the high hydrogen concentration second interlayer insulating layer 214 which is an interlayer insulating layer region where the hydrogen concentration is locally high, and the high hydrogen concentration oxide semiconductor layer 212 which is an oxide semiconductor region where the hydrogen concentration is locally high are formed.

[0113] SIMS analysis was performed on the contact portion between the oxide semiconductor layer 121 and the second interlayer insulating layer 1041 in this sample. As a result, it was found that the contact portion between the surface of IGZO and SiO x The hydrogen concentration distribution in the depth direction inside the film has a peak where the hydrogen concentration becomes high in the interface region between the oxide semiconductor layer 121 and the second interlayer insulating layer 1041 , and the peak hydrogen concentration is greater than or equal to 10 times the typical hydrogen concentration in the internal region of the second interlayer insulating layer 1041 and the oxide semiconductor layer 121 .

[0114] It was also found that when the peak hydrogen concentration in the interface region between the second interlayer insulating layer 1041 and the oxide semiconductor layer 121 is less than 1×10 22 cm -3 When an oxide semiconductor TFT is used, the oxide semiconductor TFT can be used as a switching element.

[0115] According to implementation mode 1, Fig. 8A As shown in step S7, it is necessary to deposit an oxide semiconductor film on the first gate insulating layer 102 on which the gate 112 is formed, and pattern the oxide semiconductor film into a desired shape. Therefore, selective etching is required to etch only the oxide semiconductor film without etching the previously formed gate. On the other hand, according to embodiment 3, an oxide semiconductor is not deposited on the second gate insulating layer 1042 on which the first metal layer 103 serving as the gate 112 has been formed. Therefore, it is not necessary to form the oxide semiconductor layer 121 by selective etching. In selective etching, the etchant may degrade the characteristics of the first metal layer 103. However, according to this embodiment, selective etching is not required, thereby suppressing the degradation of the characteristics of the first metal layer 103.

[0116] The embodiments described above are not limited to these implementations. Figure 5 The process of Embodiment Mode 1 described above, in which, after the insulating layer is subjected to the hydrogenation step, an oxide semiconductor layer is deposited thereon so as to be in contact with the insulating layer subjected to the hydrogenation step, can produce a similar effect.

[0117] That is, the local maximum hydrogen concentration in the interface region of the insulating layer or the interface region of the oxide semiconductor layer is greater than or equal to 10 times the hydrogen concentration in the inner region of the insulating layer and the inner region of the oxide semiconductor layer. 22 cm -3 , then preferred TFT characteristics of both the first transistor and the second transistor can be obtained.

[0118] The processes in Embodiments 1 to 5 are not limited to the process conditions of this embodiment. For example, a semiconductor device can be obtained by depositing an interlayer insulating layer after performing a hydrogenation step on an insulating layer and depositing an oxide semiconductor layer on the interlayer insulating layer.

[0119] That is, when the local maximum hydrogen concentration in the interface region of the insulating layer or the interface region of the interlayer insulating layer is greater than or equal to 10 times the hydrogen concentration in the inner region of the insulating layer and the inner region of the interlayer insulating layer, and the local maximum hydrogen concentration in the interface region of the insulating layer and the interface region of the interlayer insulating layer is less than 1×10 22 cm -3 When , preferred TFT characteristics of both the first transistor and the second transistor can be obtained.

[0120] The technical features (constituent elements) described in each embodiment can be combined with each other, and such combination can form new technical features. It should be understood that the various aspects of the embodiments disclosed herein are exemplary and non-restrictive. Since the scope of the present invention is limited by the appended claims and not by the previous description thereof, all changes falling within the boundaries and limits of the claims or within the equivalents of such boundaries and limits are intended to be covered by the claims.

[0121] It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

Claims

1. A semiconductor device comprising: Insulating substrate; a polysilicon layer formed on the insulating substrate; a first gate insulating layer, the first gate insulating layer being formed on the polysilicon layer; a first metal layer formed on the first gate insulating layer; an oxide semiconductor layer formed on the first gate insulating layer; a second gate insulating layer formed on the oxide semiconductor layer; a second metal layer formed on the second gate insulating layer; a first interlayer insulating layer formed on the second metal layer; a third metal layer formed on the first interlayer insulating layer; a first top-gate planar thin film transistor, wherein the first top-gate planar thin film transistor uses the polysilicon layer as a channel and has a source electrode, a drain electrode, and a gate electrode; as well as A second top-gate planar self-aligned thin film transistor, wherein the second top-gate planar self-aligned thin film transistor uses the oxide semiconductor layer as a channel and has a source electrode, a drain electrode, and a gate electrode, wherein: The gate of the first top-gate planar thin film transistor is formed by the first metal layer. The gate of the second top-gate planar self-aligned thin film transistor is formed by the second metal layer. The source and drain of the first top-gate planar thin film transistor and the source and drain of the second top-gate planar self-aligned thin film transistor are formed by the third metal layer. The source or drain of the first top-gate planar thin film transistor and the gate of the second top-gate planar self-aligned thin film transistor are electrically connected to each other, and A high hydrogen concentration region where the hydrogen concentration becomes locally maximum is formed at an interface region between the first gate insulating layer and the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein The hydrogen concentration in the high hydrogen concentration region is greater than or equal to 10 times and less than 100 times that in the inner region of the first gate insulating layer or the inner region of the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein The hydrogen concentration in the high hydrogen concentration region is greater than or equal to 1×10 21 cm -3 and less than 1×10 22 cm -3 .

4. A display device, comprising: The semiconductor device according to any one of claims 1 to 3; as well as Light-emitting element, wherein the second top-gate planar self-aligned thin film transistor supplies a driving current to the light emitting element, and The first top-gate planar thin film transistor controls a gate voltage of the second top-gate planar self-aligned thin film transistor.

5. The display device according to claim 4, comprising: a data line, wherein the data line applies a voltage to a source or a drain of the first top-gate planar thin film transistor; as well as A power line, the power line applies a power voltage to the second top-gate planar self-aligned thin film transistor, wherein: The data line and the power line are formed from the third metal layer.

6. The display device according to claim 4, comprising: A scan line, wherein the scan line applies a voltage to the gate of the first top-gate planar thin film transistor, wherein The scan line is formed by the first metal layer.

7. A method for manufacturing a semiconductor device, comprising the following steps: preparing an insulating substrate; Forming a first top-gate planar thin film transistor, the step of forming the first top-gate planar thin film transistor comprising the steps of forming a first channel semiconductor layer including polycrystalline silicon on the insulating substrate and hydrogenating the first channel semiconductor layer; as well as A second top-gate planar self-aligned thin film transistor is formed, wherein the step of forming the second top-gate planar self-aligned thin film transistor includes the step of forming a second channel semiconductor layer including an oxide semiconductor on the insulating substrate after the step of hydrogenating the first channel semiconductor layer, wherein: The step of forming the first top-gate planar thin film transistor comprises the following steps: forming a first gate insulating layer after the step of forming the first channel semiconductor layer; forming a first metal layer including a gate of the first top-gate planar thin film transistor on the first gate insulating layer; and forming a third metal layer including a source and a drain of the first top-gate planar thin film transistor after the step of hydrogenating the first channel semiconductor layer, and The step of forming the second top-gate planar self-aligned thin film transistor comprises: After the step of forming the second channel semiconductor layer, a step of forming a second metal layer is performed to form a gate of the second top-gate planar self-aligned thin film transistor; By forming the third metal layer, a source and a drain of the second top-gate planar self-aligned thin film transistor are formed; and A high hydrogen concentration region where the hydrogen concentration becomes locally maximum is formed on an interface region between the first gate insulating layer and the second channel semiconductor layer.

8. A method for manufacturing a semiconductor device, comprising the following steps: preparing an insulating substrate; Forming a first top-gate planar thin film transistor, the step of forming the first top-gate planar thin film transistor comprising the steps of forming a first channel semiconductor layer including polycrystalline silicon on the insulating substrate and hydrogenating the first channel semiconductor layer; as well as A second top-gate planar self-aligned thin film transistor is formed, wherein the step of forming the second top-gate planar self-aligned thin film transistor includes the step of forming a second channel semiconductor layer including an oxide semiconductor on the insulating substrate after the step of hydrogenating the first channel semiconductor layer, wherein: The step of forming the first top-gate planar thin film transistor includes the steps of forming a first gate insulating layer after the step of forming the first channel semiconductor layer, forming a scanning line for applying a voltage to the gate of the first top-gate planar thin film transistor, and forming a data line for applying a voltage to the source or drain of the first top-gate planar thin film transistor. The step of forming the second top-gate planar self-aligned thin film transistor includes the step of forming a power supply line for applying a power supply voltage to a source or a drain of the second top-gate planar self-aligned thin film transistor, and A high hydrogen concentration region where the hydrogen concentration becomes locally maximum is formed on an interface region between the first gate insulating layer and the second channel semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The step of forming the first top-gate planar thin film transistor comprises the following steps: forming a first metal layer including a gate of the first top-gate planar thin film transistor on the first gate insulating layer; and forming a third metal layer including a source and a drain of the first top-gate planar thin film transistor after the step of hydrogenating the first channel semiconductor layer, and The step of forming the second top-gate planar self-aligned thin film transistor comprises: After the step of forming the second channel semiconductor layer, a gate of the second top-gate planar self-aligned thin film transistor is formed by forming a second metal layer; and The step of forming the third metal layer forms the source and drain of the second top-gate planar self-aligned thin film transistor.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The data line and the power line are formed by the third metal layer, and The step of forming the data line and the step of forming the power line are included in the step of forming the third metal layer.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, wherein: The scanning line is formed by the first metal layer, and The step of forming the scan line is included in the step of forming the first metal layer.

12. The method for manufacturing a semiconductor device according to any one of claims 7 to 10, wherein: The hydrogenation step is a hydrogen plasma treatment.

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