Counting device for a single-chip microcomputer and counting method thereof

Abstract

This application provides a counting device and method for a microcontroller. The counting device includes: a multiplexer configured to process multiple received signals to select an externally input flashing pulse signal; a trigger controller configured to control a counting mode of a multi-bit counter based on the flashing pulse signal selected by the multiplexer; the multi-bit counter configured to accumulate and count the received flashing pulse signals according to a first predetermined method within the counting mode controlled by the trigger controller; and a processor configured to process the counting data recorded by the multi-bit counter to determine the number of times the flashing pulse signal has been input. The counting device and method provided in this application can reduce the number of overflow interrupts in the microcontroller and improve system performance.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more specifically to a counting device and counting method for a microcontroller. Background Technology

[0002] In the fields of radiomedicine and medical research, particularly in high-energy particle detection and nuclear medicine imaging such as positron emission tomography (PET), radioactive tracers are commonly used to study metabolic changes in diseased tissues or organs in humans or animals. In the human or animal body, the radioactive tracer undergoes β+ decay to produce a positron. This positron then combines with an electron within the body, resulting in annihilation and the production of a pair of gamma photons with the same energy but opposite directions, both with an energy value of 511 keV. Each annihilation of a positron and an electron is called an annihilation event. A scintillator detector placed outside the tissue or organ can detect the gamma photons produced by this annihilation event and convert them into scintillation pulse signals. By measuring these scintillation pulse signals, the timing, energy, and location information of the gamma photons arriving at the scintillator detector can be further analyzed. By using annihilation coincidence technology, the location of the response line where the annihilation event occurred can be obtained, and the distribution level of the radioactive tracer in the human or animal body can be calculated through two-dimensional or three-dimensional tomographic reconstruction algorithms. This allows for the observation of physiological and biochemical processes in the organism in vitro, and this method is showing an increasingly important role in oncology and the research, diagnosis and treatment of some neurological diseases.

[0003] In the aforementioned high-energy particle detection or PET detection, to detect gamma photons, the gamma photons are usually converted into visible light photons by a scintillation crystal in a scintillator detector. Then, a photoelectric conversion device coupled to the scintillation crystal in the scintillator detector is used to convert the visible light photons into scintillation pulse signals. Finally, the time, energy, and position information contained in the scintillation pulse signals are extracted by a data acquisition circuit and data processing equipment connected to the photoelectric conversion device.

[0004] Counting performance is one of the fundamental performance indicators of high-energy particle detection equipment or PET detectors, reflecting the limit of the number of annihilation events that the equipment can collect per unit time. Besides being limited by the upper limit of the signal itself, the counting performance of existing detection equipment typically does not exceed 1 MHz. In nuclear medicine imaging applications requiring high activity and high sensitivity, such as high-flux cosmic ray detection, short-half-life radioactive tracers, and dynamic scanning, even higher demands will be placed on the counting performance limits of high-energy particle detection equipment. Since gamma photons are ultimately converted into scintillation pulse signals, the number of scintillation pulse signals is usually counted to calculate annihilation events. To count scintillation pulse signals, existing technologies typically use comparators to convert the scintillation pulse signals into square wave pulse signals, which are then input into a microcontroller for counting.

[0005] There are two methods for counting the above-mentioned flashing pulse signals in the prior art: (1) using an external interrupt method, recording the number of flashing pulse signals in the external interrupt function; (2) using a timer to capture and compare interrupts, recording the number of flashing pulse signals in the interrupt function. Summary of the Invention

[0006] In the process of developing this application, the inventors discovered at least the following problems in the prior art:

[0007] When using existing counting methods to count flashing pulse signals, the microcontroller needs to perform push and pop operations on the stack for each received flashing pulse signal. Therefore, when receiving high-frequency flashing pulse signals, the microcontroller may frequently push and pop the stack, requiring the processor (CPU) to intervene and occupying system clock cycles. This greatly reduces the microcontroller's response speed to other programs, or even prevents other programs from running normally, which affects system performance.

[0008] The purpose of this application is to provide a counting device and counting method for a microcontroller to improve system performance.

[0009] To achieve the above objectives, the counting device and counting method for a microcontroller provided in this application are implemented as follows:

[0010] A counting device for a microcontroller, comprising:

[0011] A multiplexer configured to process received multiple signals to select a flash pulse signal input from an external source;

[0012] A trigger controller is configured to control the counting mode of a multi-bit counter based on the flashing pulse signal selected by the multiplexer;

[0013] The multi-bit counter is configured to accumulate and count the received flashing pulse signals in a first predetermined manner according to the counting mode controlled by the trigger controller; and

[0014] A processor is configured to process the counting data recorded by the multi-bit counter to determine the number of times the flashing pulse signal is input.

[0015] Preferably, the multiplexer is specifically configured to: identify a designated input source from which the flashing pulse signal is input from the outside according to a pre-stored matching relationship, and select the signal input from the designated input source among the multiplexed signals as the flashing pulse signal input from the outside.

[0016] Preferably, the first predetermined method includes counting upwards or counting downwards.

[0017] Preferably, the multi-bit counter is further configured to output the counting data to the processor in a second predetermined manner.

[0018] Preferably, the second predetermined method includes directly outputting the counting data or encoding the counting data in a preset encoding form before outputting the counting data.

[0019] Preferably, the second predetermined method further includes a preset period method, wherein the preset period includes the period during which the multi-digit counter is reset or the period during which the multi-digit counter completes cumulative counting.

[0020] Preferably, the multi-digit counter is further configured to store the counting data in an electrical form including voltage, current or charge, or in a magnetic form including magnetic field strength or magnetic flux.

[0021] Preferably, the counting device further includes a filter connected to the multiplexer and configured to filter externally input signals and send the filtered signals to the multiplexer.

[0022] Preferably, the counting device further includes a frequency divider connected to the trigger controller, the multi-bit counter, and the processor, and is configured to divide the flashing pulse signal sent by the trigger controller to merge multiple received flashing pulse signals and send the merged flashing pulse signal to the multi-bit counter.

[0023] Preferably, the counting device further includes a register connected to the multi-bit counter and configured to store the counting start point of the multi-bit counter.

[0024] A counting method for the above-mentioned counting device includes:

[0025] Step S1: The multiplexer processes the received multiple signals to select the flashing pulse signal input from the outside.

[0026] Step S2: The trigger controller controls the counting mode of the multi-bit counter according to the flashing pulse signal selected by the multiplexer;

[0027] Step S3, the multi-bit counter accumulates and counts the flashing pulse signal according to a first predetermined method in the counting mode controlled by the trigger controller; and

[0028] Step S4: The processor processes the counting data recorded by the multi-bit counter to determine the number of times the flashing pulse signal is input.

[0029] Preferably, step S1 includes:

[0030] The designated input source from which the flashing pulse signal is input from the outside is identified based on a pre-stored matching relationship;

[0031] The signal input through the designated input source from the multiple signals is selected as the flashing pulse signal input from the outside.

[0032] Preferably, step S2 includes:

[0033] The trigger controller controls the counting mode of the multi-bit counter to be either rising edge driven counting or falling edge driven counting based on the amplitude, frequency, and / or phase of the flashing pulse signal.

[0034] Preferably, step S3 includes:

[0035] When the received flashing pulse signal reaches the upper limit of the multi-bit counter, the multi-bit counter overflows and is interrupted. The number of overflow interrupts is recorded in the storage unit with interrupt function logic, and the multi-bit counter is reset so that it can count again.

[0036] Preferably, step S4 includes:

[0037] The processor calculates the number of times the flash pulse signal is input in the following manner:

[0038] When the multi-bit counter does not experience an overflow interrupt, the number of inputs equals the current count data of the multi-bit counter.

[0039] When the multi-bit counter experiences an overflow interruption, the number of inputs = the number of overflow interruptions of the multi-bit counter * the upper limit of the multi-bit counter + the current count data of the multi-bit counter.

[0040] Preferably, between step S3 and step S4, the method further includes:

[0041] S31, the multi-bit counter outputs the counting data to the processor according to a second predetermined method.

[0042] Preferably, the second predetermined method includes directly outputting the counting data or encoding the counting data in a preset encoding form before outputting the counting data.

[0043] Preferably, the second predetermined method further includes a preset period method, wherein the preset period includes the period during which the multi-digit counter is reset or the period during which the multi-digit counter completes cumulative counting.

[0044] Preferably, the method further includes:

[0045] S32, the multi-digit counter stores the counting data in an electrical form including voltage, current or charge, or in a magnetic form including magnetic field strength or magnetic flux.

[0046] Preferably, before step S1, the method further includes:

[0047] S0, the filter in the counting device filters the received multiple signals and sends the filtered multiple signals to the multiplexer to select the flashing pulse signal input from the outside.

[0048] Preferably, before step S3, the method further includes:

[0049] The frequency divider in the counting device divides the flashing pulse signal sent by the trigger controller and sends the divided flashing pulse signal to the multi-bit counter.

[0050] Accordingly, step S4 includes:

[0051] The processor calculates the number of flash pulse signal inputs in the following manner:

[0052] When the multi-bit counter does not experience an overflow interrupt, the number of inputs = the current count data of the multi-bit counter * the division number of the frequency divider;

[0053] When the multi-bit counter experiences an overflow interruption, the number of inputs = (the number of overflow interruptions of the multi-bit counter * the upper limit of the multi-bit counter + the current count data of the multi-bit counter) * the number of divisions by the frequency divider.

[0054] As can be seen from the technical solutions provided in the above embodiments of this application, the embodiments of this application count by using devices such as multiplexers, trigger controllers, multi-bit counters and processors inside the counting device applied to the microcontroller when a flashing pulse signal is received, without requiring the microcontroller to push and pop from the stack every time a flashing pulse signal is received. Therefore, this will not cause the microcontroller to frequently push and pop from the stack when an interrupt occurs, thus improving the CPU response speed of the microcontroller to other programs, and thereby improving system performance. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the structure of a counting device for a microcontroller provided according to an embodiment of this application;

[0057] Figure 2 This is a flowchart illustrating the counting method of the counting device provided in the embodiments of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only used to explain some embodiments of this application, and not all embodiments, and are not intended to limit the scope or claims of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0059] It should be noted that when an element is referred to as being "set on" another element, it can be directly set on the other element or there may be an intervening element. When an element is referred to as being "connected / linked" to another element, it can be directly connected / linked to the other element or there may be an intervening element. The term "connected / linked" as used herein can include electrical and / or mechanical physical connections / links. The term "including / comprises" as used herein means the presence of a feature, step, or element, but does not exclude the presence or addition of one or more other features, steps, or elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0061] The counting device and counting method for a microcontroller provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0062] like Figure 1 As shown, the counting device 10 can be housed within a microcontroller (e.g., STM32), and may include a multiplexer 11, a trigger controller 12, a multi-bit counter 13, and a processor 14 interconnected with each other. The multiplexer 11 processes received multiple signals to select externally input flashing pulse signals and sends the selected flashing pulse signals to the trigger controller 12. The trigger controller 12 controls the counting mode of the multi-bit counter 13 based on the flashing pulse signals sent by the multiplexer 11. The multi-bit counter 13 accumulates and counts the received flashing pulse signals according to a first predetermined method within the counting mode controlled by the trigger controller 12. The processor 14 processes the counting data recorded by the multi-bit counter 13 to determine the number of times the flashing pulse signals have been input.

[0063] In embodiments of this application, the multiplexer 11 may have multiple input terminals, through which it can receive signals. After receiving multiple signals, it can identify a designated input source (e.g., an external trigger pin of a microcontroller) that inputs a scintillation pulse signal from the outside according to a pre-stored matching relationship (e.g., the identifier or port number of the input source). It then selects the signal input through the designated input source from the received multiple signals as the externally input scintillation pulse signal, and sends the selected scintillation pulse signal to the trigger controller 12. The multiple signals may include scintillation pulse signals input through the designated input source, or signals sent by other devices within the microcontroller. The scintillation pulse signal may originate from a scintillation detector composed of an external scintillation crystal and photomultiplier tube or silicon photomultiplier, or a gas radiation detector composed of a Geiger counter or proportional counter.

[0064] After receiving the flashing pulse signal sent by the multiplexer 11, the trigger controller 12 can control the counting mode of the multi-bit counter 13 according to the characteristics of the flashing pulse signal, such as amplitude, frequency, and / or phase. For example, when the amplitude of the flashing pulse signal varies greatly, the trigger controller 12 can control the counting mode of the multi-bit counter 13 to be driven by the rising edge or the falling edge.

[0065] The multi-bit counter 13 can be a counter with more than two bits, such as a 4-bit counter, an 8-bit counter, a 16-bit counter, or a 32-bit counter. After receiving a flashing pulse signal from the multiplexer 11 or the trigger controller 12, the multi-bit counter 13 can accumulate and count the received flashing pulse signal according to a first preset method under the control of the trigger controller 12, and output the recorded count data to the processor 14 according to a second predetermined method. When the received flashing pulse signal reaches the upper limit of the multi-bit counter 13, the multi-bit counter 13 may experience an overflow interrupt, and the number of overflow interrupts is recorded in its memory unit with interrupt function logic. At this time, the multi-bit counter can start counting again after being reset. The multi-bit counter 13 can also save the count data while counting.

[0066] After receiving the counting data output by the multi-bit counter 13, the processor 14 can process the counting data. The processor 14 can calculate the number of inputs of the flashing pulse signal in the following manner:

[0067] When the multi-bit counter 13 does not experience an overflow interrupt, the number of inputs equals the current count data of the multi-bit counter 13.

[0068] When the multi-bit counter 13 experiences an overflow interrupt, the number of inputs = the number of overflow interrupts of the multi-bit counter 13 * the upper limit of the multi-bit counter 13 + the current count data of the multi-bit counter 13.

[0069] Based on the calculation results of processor 14, the number of times the flashing pulse signal is input can be determined.

[0070] In another embodiment of this application, the counting device 10 may further include a filter connected to a multiplexer 11, which is used to filter externally input signals and send the filtered signals to the multiplexer 11 so that the multiplexer 11 can select the flashing pulse signal.

[0071] In another embodiment of this application, the counting device 10 may further include a frequency divider connected to the trigger controller 12, the multi-bit counter 13, and the processor 14. The frequency divider divides the flashing pulse signal sent by the trigger controller 12 to merge multiple received flashing pulse signals and sends the merged flashing pulse signal to the multi-bit counter 13. This reduces the number of times the multi-bit counter 13 counts and the number of times it is interrupted. Correspondingly, the processor 14 can process the data based on the frequency divider's division count and the multi-bit counter's counting data to determine the number of input flashing pulse signals.

[0072] The processor 14 can calculate the number of times the flash pulse signal is input in the following manner:

[0073] When the multi-bit counter 13 does not experience an overflow interrupt, the number of inputs = the current count data of the multi-bit counter 13 * the division number of the frequency divider;

[0074] When the multi-bit counter 13 experiences an overflow interrupt, the number of inputs = (number of overflow interrupts of multi-bit counter 13 * upper limit of multi-bit counter 13 + current count data of multi-bit counter 13) * number of divisions by the frequency divider.

[0075] In another embodiment of this application, the counting device 10 may further include a register, which can be used to store the starting point of the timing and can send the recorded starting point data to the multi-bit counter 13 after the counting cycle ends, so that the multi-bit counter 13 can count according to the starting point data it sends. The starting point data can be used as the initial state of the multi-bit counter 13.

[0076] The counting device provided in this application directly counts the flashing pulse signals received via the internal multiplexer 11, trigger controller 12, multi-bit counter 13, and processor 14. This eliminates the need to record the number of flashing pulse signals in the external interrupt function logic and avoids the microcontroller popping and unpopping from the stack every time a flashing pulse signal is received. This prevents frequent stack popping and unpopping during overflow interrupts, thus improving the CPU's response speed to other programs and ultimately enhancing system performance. Furthermore, the multi-bit counter in this application increases the counting limit and reduces the number of overflow interrupts, thereby reducing system power consumption and allowing the CPU to execute other programs more promptly, further improving system performance.

[0077] This application also provides a method for counting using the above-described counting device, such as... Figure 2 As shown. The method includes the following steps:

[0078] S1: The multiplexer processes the received multiple signals to select the flash pulse signal input from the outside.

[0079] After receiving multiple signals, the multiplexer can identify the designated input source (e.g., the external trigger pin of the microcontroller) that receives the flashing pulse signal from the outside based on the pre-stored matching relationship (e.g., the identifier or port number of the input source). Then, it selects the signal input through the designated input source from the received multiple signals as the flashing pulse signal input from the outside, and then sends the selected flashing pulse signal to the trigger controller.

[0080] S2: The trigger controller controls the counting mode of the multi-bit counter according to the flashing pulse signal selected by the multiplexer.

[0081] Upon receiving the flashing pulse signal sent by the multiplexer, the trigger controller can control the counting mode of the multi-bit counter based on the amplitude, frequency, and / or phase characteristics of the flashing pulse signal. The counting mode includes rising-edge driven counting or falling-edge driven counting. Rising-edge driven counting means counting only when the rising edge of the flashing pulse signal arrives, and falling-edge driven counting means counting only when the falling edge of the flashing pulse signal arrives.

[0082] S3: The multi-bit counter accumulates and counts the received flashing pulse signals in the counting mode controlled by the trigger controller according to the first predetermined method.

[0083] Upon receiving a flashing pulse signal from a multiplexer or trigger controller, the multi-bit counter can accumulate the number of rising or falling edges of the received flashing pulse signal according to a first preset method in the counting mode controlled by the trigger controller. When the received flashing pulse signal reaches the upper limit of the multi-bit counter, the multi-bit counter may experience an overflow interrupt, and the number of overflow interrupts is recorded in its memory unit with interrupt function logic. At this time, the multi-bit counter can start counting again after a reset.

[0084] The first predetermined method may include counting upwards or counting downwards. For example, when a multi-bit counter receives the rising or falling edge of a flashing pulse signal, it can accumulate counts by performing addition, subtraction, or series calculations on previously recorded count data. For example, adding or subtracting 1, 2, or other fixed values ​​from the previously recorded count data, or incrementing or decrementing sequentially in binary or decimal.

[0085] The cumulative counting can refer to continuing counting based on previously recorded counting data. The previously recorded counting data can refer to the counting data recorded by the multi-bit counter from its initial state to the first reset, or it can refer to the counting data recorded by the multi-bit counter after the I-th reset and before the (I+1)-th reset, where I is a positive integer. If the multi-bit counter does not receive any flashing pulse signal, the previously recorded counting data can refer to the initial state of the multi-bit counter. The initial state of the multi-bit counter can be represented by a preset value, such as 0, 1, or other values ​​(e.g., 2). n -1, where n is the number of bits in the counter.

[0086] The counting data can correspond to the number of flashing pulse signals received by the multi-bit counter from its initial state to before the first reset, or it can correspond to the number of flashing pulse signals received by the multi-bit counter after each reset. It should be noted that the multi-bit counter returns to its initial state after being reset.

[0087] S4: The processor processes the counting data recorded by the multi-bit counter to determine the number of times the flashing pulse signal is input.

[0088] After receiving the counting data from the multi-bit counter, the processor can process the counting data. The processor can calculate the number of input flash pulse signals in the following manner:

[0089] When the multi-bit counter does not experience an overflow interrupt, the number of inputs equals the current count data of the multi-bit counter.

[0090] When a multi-bit counter experiences an overflow interrupt, the number of inputs equals the number of overflow interrupts of the multi-bit counter multiplied by the upper limit of the multi-bit counter plus the current count data of the multi-bit counter.

[0091] Based on the processor's calculations, the number of times the flashing pulse signal was input can be determined.

[0092] In another embodiment of this application, between step S3 and step S4, the method may further include:

[0093] S31, the multi-bit counter outputs the counting data to the processor according to the second predetermined method.

[0094] After the multi-bit counter records the number of rising edges or falling edges of the flash pulse signal, the multi-bit counter can output the recorded count data of the number of rising edges or falling edges of the flash pulse signal to the processor in a second predetermined manner.

[0095] The second predetermined method may include direct output or encoding the counting data in a preset code before outputting it. The second predetermined method may also include a preset period. For example, a multi-bit counter can directly output the counting data, or it can encode the counting data in binary code, binary-decimal (BCD) code, cyclic code, or other encoding forms before outputting the counting data, thereby facilitating subsequent data processing. The preset period may include the period during which the multi-bit counter is reset or the period during which the multi-bit counter completes its cumulative counting. For example, a multi-bit counter can output the counting data after each reset, or it can output the counting data after completing the cumulative counting of all data, in order to meet different application requirements. It should be noted that when outputting the counting data in a direct output or encoded output manner, it is also possible to output the data in a preset period manner.

[0096] In another embodiment of this application, the method may further include:

[0097] S32: A multi-bit counter stores the recorded counting data in a predetermined format.

[0098] A multi-bit counter can store the recorded count data in a predetermined format while or after counting the flashing pulse signal. The predetermined format may include electrical forms such as voltage, current, or charge, or magnetic forms such as magnetic field strength or magnetic flux.

[0099] In another embodiment of this application, prior to step S1, the method may further include:

[0100] S0: The filter in the counting device filters the input multi-channel pulse signal and sends the filtered multi-channel pulse signal to the multiplexer to select the flashing pulse signal input from the outside.

[0101] In another embodiment of this application, prior to step S3, the method may further include:

[0102] S21: The frequency divider in the counting device divides the flashing pulse signal sent by the trigger controller and sends the divided flashing pulse signal to the multi-bit counter.

[0103] A frequency divider can divide the flashing pulse signal sent by the trigger controller to combine multiple received flashing pulse signals and send the combined flashing pulse signal to a multi-bit counter. This reduces the number of times the multi-bit counter counts and the number of times it is interrupted.

[0104] Accordingly, step S4 may include: the processor processing the counting data output by the multi-bit counter according to the division number of the frequency divider to determine the number of input flashing pulse signals.

[0105] The processor can calculate the number of times the flash pulse signal is input in the following way:

[0106] When the multi-bit counter does not experience an overflow interrupt, the number of inputs = the current count data of the multi-bit counter * the division number of the frequency divider;

[0107] When a multi-bit counter experiences an overflow interrupt, the number of inputs = (number of overflow interrupts of the multi-bit counter * the upper limit of the multi-bit counter + the current count data of the multi-bit counter) * the number of divisions by the frequency divider.

[0108] The counting method provided in this application directly accumulates and counts the received blink pulse signals through internal multiplexers, trigger controllers, multi-bit counters, and processors upon receipt, eliminating the need to record the number of blink pulse signals in external interrupt function logic. This avoids frequent stack popping and unpopping by the microcontroller during interrupts, thus improving the CPU's response speed to other programs and ultimately enhancing system performance. Furthermore, the use of a multi-bit counter increases the counting limit and reduces the number of overflow interrupts, thereby lowering system power consumption. It also allows the CPU to execute other programs promptly, further improving system performance and increasing the upper frequency limit, for example, reaching 30MHz, significantly higher than the existing upper frequency limits of 300kHz to 400kHz.

[0109] The devices, units, or other components described in the above embodiments can be implemented by computer chips, semiconductor chips, and / or physical entities, or by products with certain functions. For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more semiconductor chips.

[0110] While this application provides the operational steps of the methods described in the above embodiments or flowcharts, the methods may include more or fewer operational steps based on conventional or non-inventive methods. For steps where there is no logically necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application.

[0111] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0112] The above embodiments are described to enable those skilled in the art to understand and use this application. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, this application is not limited to the above embodiments, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope of this application should be within the protection scope of this application.

Claims

1. A counting device for a single-chip microcomputer, characterized by comprising: The counting device includes components disposed inside the microcontroller: A multiplexer configured to process received multiple signals to select a flash pulse signal input from an external source; A trigger controller is configured to control the counting mode of a multi-bit counter based on the characteristics of the flashing pulse signal selected by the multiplexer; The multi-bit counter is configured to accumulate and count the received flashing pulse signals in a first predetermined manner under the counting mode controlled by the trigger controller. The multi-bit counter is provided with a storage unit for interrupt function logic, which is configured to record the number of times the multi-bit counter overflows and interrupts, and to reset the multi-bit counter so that it counts again. The frequency divider, which is connected to the trigger controller, the multi-bit counter and the processor, is used to divide the flash pulse signal sent by the trigger controller to merge multiple received flash pulse signals and send the merged flash pulse signal to the multi-bit counter. as well as The processor is configured to selectively process the counting data recorded by the multi-bit counter or to process the counting data recorded by the multi-bit counter, the number of overflow interrupts recorded by the storage unit, and the number of divisions by the frequency divider to determine the number of times the flashing pulse signal is input.

2. The counting device of claim 1, wherein, The multiplexer is specifically configured to: identify a designated input source from which the flashing pulse signal is input from the outside based on a pre-stored matching relationship, and select the signal input from the designated input source among the multiplexed signals as the flashing pulse signal input from the outside.

3. The counting device of claim 1, wherein, The first predetermined method includes counting upwards or counting downwards.

4. The counting device of claim 1, wherein, The multi-bit counter is also configured to output the counting data to the processor in a second predetermined manner.

5. The counting device of claim 4, wherein, The second predetermined method includes directly outputting the counting data or encoding the counting data in a preset encoding form before outputting the counting data.

6. The counting device of claim 4, wherein, The second predetermined method also includes a preset period method, wherein the preset period includes the period during which the multi-bit counter is reset or the period during which the multi-bit counter completes its cumulative counting.

7. The counting device of claim 1, wherein, The multi-bit counter is also configured to store the counting data in an electrical form including voltage, current, or charge, or in a magnetic form including magnetic field strength or magnetic flux.

8. The counting device of claim 1, wherein, The counting device further includes a filter connected to the multiplexer and configured to filter externally input signals and send the filtered signals to the multiplexer.

9. The counting device of claim 1, wherein, The counting device further includes a register connected to the multi-bit counter and configured to store the counting start point of the multi-bit counter.

10. A counting method of the counting device according to claim 1, characterized by, The counting method includes: Step S1: The multiplexer processes the received multiple signals to select the flashing pulse signal input from the outside. Step S2: The trigger controller controls the counting mode of the multi-bit counter according to the characteristics of the flashing pulse signal selected by the multiplexer; Step S3: The frequency divider is connected to the trigger controller, the multi-bit counter, and the processor. It is used to divide the flashing pulse signal sent by the trigger controller to merge multiple received flashing pulse signals and send the merged flashing pulse signal to the multi-bit counter. Step S4: The multi-bit counter accumulates and counts the flashing pulse signal according to a first predetermined method in the counting mode controlled by the trigger controller. When the received flashing pulse signal reaches the upper limit of the multi-bit counter, an overflow interrupt occurs. The number of overflow interrupts is recorded in a memory unit with interrupt function logic, and the multi-bit counter is reset to count again. Step S5: The processor selectively processes the counting data recorded by the multi-bit counter or processes the counting data recorded by the multi-bit counter and the number of overflow interrupts recorded by the storage unit together to determine the number of times the flashing pulse signal is input.

11. The counting method of claim 10, wherein, Step S1 includes: The designated input source from which the flashing pulse signal is input from the outside is identified based on a pre-stored matching relationship; The signal input through the designated input source from the multiple signals is selected as the flashing pulse signal input from the outside.

12. The counting method of claim 10, wherein, The characteristics of the scintillation pulse signal include its amplitude, frequency, and / or phase. Step S2 includes: The trigger controller controls the counting mode of the multi-bit counter to be either rising edge driven counting or falling edge driven counting based on the amplitude, frequency, and / or phase of the flashing pulse signal.

13. The counting method of claim 10, wherein, Step S5 includes: The processor calculates the number of times the flash pulse signal is input in the following manner: When the multi-bit counter does not experience an overflow interrupt, the number of inputs equals the current count data of the multi-bit counter. When the multi-bit counter experiences an overflow interruption, the number of inputs = the number of overflow interruptions of the multi-bit counter * the upper limit of the multi-bit counter + the current count data of the multi-bit counter.

14. The counting method of claim 10, wherein, Between step S4 and step S5, the method further includes: S31, the multi-bit counter outputs the counting data to the processor according to a second predetermined method.

15. The counting method of claim 14, wherein, The second predetermined method includes directly outputting the counting data or encoding the counting data in a preset encoding form before outputting the counting data.

16. The counting method according to claim 14, characterized in that, The second predetermined method also includes a preset period method, wherein the preset period includes the period during which the multi-bit counter is reset or the period during which the multi-bit counter completes its cumulative counting.

17. The counting method of claim 10, wherein, The method further includes: S32, the multi-digit counter stores the counting data in an electrical form including voltage, current or charge, or in a magnetic form including magnetic field strength or magnetic flux.

18. The counting method of claim 10, wherein, Prior to step S1, the method further includes: S0, the filter in the counting device filters the received multiple signals and sends the filtered multiple signals to the multiplexer to select the flashing pulse signal input from the outside.

19. The counting method of claim 10, wherein, Prior to step S4, the method further includes: S21, the frequency divider in the counting device divides the flashing pulse signal sent by the trigger controller and sends the divided flashing pulse signal to the multi-bit counter. Accordingly, step S5 includes: The processor calculates the number of flash pulse signal inputs in the following manner: When the multi-bit counter does not experience an overflow interrupt, the number of inputs = the current count data of the multi-bit counter * the division number of the frequency divider; When the multi-bit counter experiences an overflow interrupt, the number of inputs = (the number of overflow interrupts of the multi-bit counter * the upper limit of the multi-bit counter + the current count data of the multi-bit counter) * the number of divisions of the frequency divider.

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