Level shifter circuit with two-domain level shifting capability

By designing an improved level shifter circuit, parallel conversion of medium and high voltage levels is realized, and overlap time of capacitive coupling and bias signals is optimized, the problems of slow level conversion speed, high power consumption and current cross-conduction in the prior art are solved, and the level conversion effect with fast and low power consumption is achieved.

CN110277986BActive Publication Date: 2025-03-25STMICROELECTRONICS SRL
2 Cites 0 Cited by

Patent Information

Application Number
CN201910173172.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2018-03-15
Filing Date
2019-03-07
Publication Date
2025-03-25
Estimated Expiration
2039-03-07

AI Technical Summary

Technical Problem

Existing level shifter solutions cannot meet the requirements of fast level conversion, low power consumption and small area occupancy in storage devices, and cannot perform level shift operations in the medium and high voltage domains in parallel, resulting in problems such as current cross-conduction.

Method used

An improved level shifter circuit is designed to reduce power isolation time to improve switching speed by implementing parallel conversion of medium and high voltage levels between input stages and high level shift stages, and to optimize overlap time of capacitive coupling and bias signals using decoupling units and drive units.

Benefits of technology

Fast, low power level conversion is achieved, reducing delays between level conversions, avoiding current cross-conduction, and providing flexibility for applicable power supply voltage values.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The present disclosure relates to a level shifter circuit with two-domain level shifting capability. For example, a level shifter circuit is configured to shift an input signal switched within a first voltage range to correspondingly generate a first output signal switched within a second voltage range higher than the first voltage range. The level shifter circuit includes a latch core having: latch input and output terminals; a power line configured to be powered by a power supply voltage; and a reference line configured to be coupled to a reference voltage. A capacitive coupling element is coupled to the latch input and output terminals of the latch core. The driver stage is configured to bias the capacitive coupling element using a bias signal generated based on the input signal. The decoupling stage is configured to be driven by the driver stage through the capacitive coupling element to decouple the power line from the power supply voltage and to decouple the reference line from the reference voltage during switching of the input signal.
Need to check novelty before this filing date? Find Prior Art