A Deepin panel that separates the display and operating system

Abstract

The present invention discloses a depth panel with separated display and operating system, specifically relates to the field of oil well logging technology, including an SDDP board body, a depth combination input interface is fixedly provided at one end of the front side of the SDDP board body, other combination input interfaces are fixedly provided at one side of the depth coding input interface, a coding wheel output interface is fixedly provided at the other end of the front side of the SDDP board body, a GPIB output interface is fixedly provided at one side of the coding wheel output interface, a power supply interface is fixedly provided at one end of the front side of the SDDP board body, and a front panel connector is fixedly provided at the rear side of the SDDP board body. The present invention has the data display part handled by a serial port screen, and its operating system assumes the functions of network data collection and algorithm processing, and the data display part is handled by a serial port screen, and its operating system assumes the functions of network data collection and algorithm processing. This device separates the data display part and the operating system part into two independent units.

Description

Technical Field

[0001] The embodiment of the present invention relates to the technical field of oil well logging, and in particular to a depth panel with a separated display and operation system. Background Art

[0002] The SDDP panel is one of the important equipment in the logging system. It can be connected with various types of depth measurement sensors and tension sensors to achieve accurate depth and tension measurements. It can simultaneously receive and process two-way depth encoder signals and two-way tension signals, and improve the system's operational stability through multi-way backup. It can actively control and give real-time alarms to peripherals such as winches, and can communicate with the host in real time in multiple modes. On the one hand, it helps winch operators determine the location of logging instruments, and decelerates in time when the logging instruments are about to reach the bottom of the well and the wellhead. On the other hand, it serves as an important basis for logging software to process the uploaded data of logging instruments.

[0003] The existing technology has the following shortcomings: the collection of operating system network data is inconvenient, the data display part and the operating system part are combined together, and frequent crashes occur. Summary of the invention

[0004] To this end, an embodiment of the present invention provides a depth panel with separated display and operating system, wherein the data display part is handled by the serial port screen, and its operating system undertakes the functions of network data collection and algorithm processing. This device separates the data display part and the operating system part into two independent units, effectively solving the problem of frequent crashes of the previous depth panel, so as to solve the problems in the prior art caused by complex data processing and frequent crashes.

[0005] In order to achieve the above-mentioned purpose, the embodiment of the present invention provides the following technical solution: a depth panel with a separated display and operating system, comprising an SDDP board body, a depth combination input interface is fixedly provided at one end of the front side of the SDDP board body, other combination input interfaces are fixedly provided at one side of the depth coding input interface, a coding wheel output interface is fixedly provided at the other end of the front side of the SDDP board body, a GPIB output interface is fixedly provided at one side of the coding wheel output interface, a power supply interface is fixedly provided at one end of the front side of the SDDP board body, and a front panel connector is fixedly provided at the rear side of the SDDP board body;

[0006] An FPGA is fixedly arranged inside the SDDP board, and the FPGA is connected to the deep combination input interface through a differential receiving circuit or a single-ended receiving circuit, and a switch is fixedly arranged at the input end of the differential receiving circuit and the single-ended receiving circuit;

[0007] The output ends of the other combined input interfaces are respectively connected to a tension amplification filter circuit and an MMD amplification circuit, and the output ends of the tension amplification filter circuit and the MMD amplification circuit are both fixedly connected to a multi-way switch, and the multi-way switch is connected to the FPGA via an A / D converter;

[0008] The output end of the FPGA (8) is connected to a PCI bus, the output end of the PCI bus is connected to a network interface, a SOM-7567 is arranged inside the PCI bus, and the output end of the SOM-7567 (18) is connected to a display screen serial interface, a GPIB interface and a 485 conversion interface.

[0009] Furthermore, the SDDP board is laid flat, the length of the SDDP board is set to 220 mm, the width is set to 122 mm, and the SDDP board is fixed with six copper pillars, four copper pillars at the four corners and two copper pillars in the middle.

[0010] Furthermore, the deep combination input interface is configured to be introduced by a 12-core connector, and the switch is configured to be a control bit to control a micro relay.

[0011] Furthermore, a backup circuit is fixedly arranged between the switch and the FPGA and between other combined input interfaces and the multi-way switch.

[0012] Furthermore, the FPGA is connected to an alarm device through K5 output, the alarm device is set as a buzzer, and outputs a brake control signal through K6. The alarm signal is led out through the front panel connector, and the brake signal is led out through a 10-core connector.

[0013] Furthermore, the network interface is set as a BASE-T network interface, and both the network interface and the GPIB interface exchange data with the host through a plug-in.

[0014] Furthermore, the encoding wheel output interface is set as a 10-core interface, and the 485 conversion interface is set as a video interface.

[0015] Furthermore, the FPGA is internally provided with a jitter correction and a direction detector, the jitter correction output is connected to the direction detector input, the direction detector output is respectively connected to the round one up counter, the round one down counter, the round two up counter and the round two down counter, the FPGA is internally provided with an analog circuit, and the analog circuit output is respectively connected to the round one up counter, the round one down counter, the round two up counter and the round two down counter.

[0016] The embodiments of the present invention have the following advantages:

[0017] 1. The present invention adopts a separation design, and the serial port interface of the display screen is connected to the rear panel through the SDDP board connector and a detachable connector. The serial port screen can display the data output by the SDDP board through the serial port in a user-friendly graphical interface, and send it to the SDDP board through the serial port through the parameter setting of human-computer interaction, and perform algorithm control on it. The data display part is handled by the serial port screen, and its operating system assumes the functions of network data collection and algorithm processing. The data display part is handled by the serial port screen, and its operating system assumes the functions of network data collection and algorithm processing. This device separates the data display part and the operating system part into two independent units, which effectively solves the problem of frequent freezes of the previous Deepin panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0019] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0020] Figure 1 A schematic diagram of the overall layout structure provided by the present invention;

[0021] Figure 2 A schematic diagram of the working principle structure provided by the present invention;

[0022] Figure 3 A schematic diagram of a coding wheel signal wave provided by the present invention;

[0023] Figure 4 A circuit structure schematic diagram of a differential receiving circuit and a single-ended receiving circuit is provided for the present invention;

[0024] Figure 5 A schematic diagram of the circuit structure of the analog circuit and the alarm output is provided for the present invention;

[0025] Figure 6 Provide a schematic diagram of the FPGA logic circuit structure for the present invention;

[0026] In the figure: 1SDDP board, 2 depth combination input interface, 3 other combination input interface, 4 encoder wheel output interface, 5GPIB output interface, 6 power supply interface, 7 front panel interface, 8FPGA, 9 differential receiving circuit, 10 single-ended receiving circuit, 11 switch, 12 tension amplification filter circuit, 13MMD amplification circuit, 14 multi-way switch, 15A / D converter, 16PCI bus, 17 network interface, 18SOM-7567, 19 display screen serial interface, 20GPIB interface, 21 485 conversion interface, 22 standby circuit, 23 alarm device, 24 jitter correction, 25 direction identification, 26 round one up counter, 27 round one down counter, 28 round two up counter, 29 round two down counter, 30 analog circuit. DETAILED DESCRIPTION

[0027] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Refer to the instruction manual Figure 1-6 , a depth panel with a display and an operating system separated in this embodiment comprises an SDDP board body 1, a depth combination input interface 2 is fixedly provided at one end of the front side of the SDDP board body 1, another combination input interface 3 is fixedly provided at one side of the depth coding input interface 2, a coding wheel output interface 4 is fixedly provided at the other end of the front side of the SDDP board body 1, a GPIB output interface 5 is fixedly provided at one side of the coding wheel output interface 4, a power supply interface 6 is fixedly provided at one end of the front side of the SDDP board body 1, and a front panel connector 7 is fixedly provided at the rear side of the SDDP board body 1;

[0029] The SDDP board 1 is fixedly provided with an FPGA 8, and the FPGA 8 is connected to the depth combination input interface 2 via a differential receiving circuit 9 or a single-ended receiving circuit 10, and a switch 11 is fixedly provided at the input end of the differential receiving circuit 9 and the single-ended receiving circuit 10;

[0030] The output ends of the other combined input interfaces 3 are respectively connected to a tension amplification filter circuit 12 and an MMD amplification circuit 13, and the output ends of the tension amplification filter circuit 12 and the MMD amplification circuit 13 are fixedly connected to a multi-way switch 14, and the multi-way switch 14 is connected to the FPGA 8 via an A / D converter 15;

[0031] The output end of the FPGA8 is connected to a PCI bus 16, and the output end of the PCI bus 16 is connected to a network interface 17. A SOM-756718 is arranged inside the PCI bus 16, and the output end of the SOM-756718 is connected to a display screen serial interface 19, a GPIB interface 20 and a 485 conversion interface 21.

[0032] Furthermore, the SDDP board 1 is laid flat, the length of the SDDP board 1 is set to 220 mm, the width is set to 122 mm, and the SDDP board 1 is fixed with six copper pillars, four copper pillars at the four corners and two copper pillars in the middle, so as to facilitate the fixing of the panel.

[0033] Furthermore, the deep combination input interface 2 is configured to be introduced by a 12-pin connector, the switch 11 is configured to be a control bit control micro relay, and the control bit control micro relay model is configured to be TX2-5V.

[0034] Furthermore, a backup circuit 22 is fixedly provided between the switch 11 and the FPGA 8 and between other combined input interfaces 3 and the multi-way switch 14, and the backup circuit 22 is used to improve the stability of circuit transmission.

[0035] Furthermore, the FPGA8 is connected to an alarm device 23 through K5 output. The alarm device 23 is set as a buzzer and outputs a brake control signal through K6. The alarm signal is led out through the front panel connector and the brake signal is led out through a 10-pin connector, which is convenient for the panel to alarm and the staff to check.

[0036] Furthermore, the network interface 17 is configured as a BASE-T network interface, and both the network interface 17 and the GPIB interface 20 exchange data with the host through a plug-in, thereby improving data exchange effects and data processing effects.

[0037] Furthermore, the encoding wheel output interface 4 is set as a 10-core interface, and the 485 conversion interface 21 is set as a video interface to facilitate data transmission and video output transmission, and the wellhead display device displays the data.

[0038] Furthermore, the FPGA8 is internally provided with a jitter correction 24 and a direction detector 25, the output end of the jitter correction 24 is connected to the input end of the direction detector 25, the output end of the direction detector 25 is respectively connected to the round one upper counter 26, the round one lower counter 27, the round two upper counter 28 and the round two lower counter 29, and the FPGA8 is internally provided with an analog circuit 30, the output end of the analog circuit 30 is respectively connected to the round one upper counter 26, the round one lower counter 27, the round two upper counter 28 and the round two lower counter 29, to facilitate data recording.

[0039] The specific implementation scenario is as follows: when the panel is used in the present invention, the depth combination input interface 2 is connected to two depth encoding wheels for buffering and shaping, direction identification, and counting respectively according to the up and down directions using the wheel one upper counter 26, the wheel one lower counter 27, the wheel two upper counter 28, and the wheel two lower counter 29. The other combination input interfaces 3 are connected to the tension sensing device and the magnetic sensing device. The tension signal is filtered and amplified by the tension amplification filter circuit 12, and the magnetic sign filtering is filtered and amplified by the MMD amplification circuit 13, and converted by the A / D converter. The backup circuit 22 is set to ensure stable operation. After the data is processed by the algorithm, the data is transmitted to the host through the network port or GPIB interface 20, and the data is sent to the wellhead display device through the display serial interface 19.

[0040] Working principle: Refer to the attached Figure 1-6 When using the panel, the depth combination input interface 2 is connected to two depth encoding wheels for buffer shaping and direction identification, and the up and down directions are counted respectively by using the wheel one upper counter 26, the wheel one lower counter 27, the wheel two upper counter 28, and the wheel two lower counter 29. The other combination input interfaces 3 are connected to the tension sensing device and the magnetic sensing device. The tension signal is filtered and amplified by the tension amplification filter circuit 12, and the magnetic sign filtering is filtered and amplified by the MMD amplification circuit 13, and converted by the A / D converter. The backup circuit 22 is set to ensure stable operation. After the data is processed by the algorithm, the data is transmitted to the host through the network port or GPIB interface 20, and the data is sent to the wellhead display device through the display serial interface 19.

[0041] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made on the basis of the present invention. Therefore, these modifications or improvements made on the basis of not departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. A deep panel that separates a display and an operating system, comprising an SDDP board body (1), characterized in that: A depth combination input interface (2) is fixedly provided at one end of the front side of the SDDP board body (1), another combination input interface (3) is fixedly provided on one side of the depth coding input interface (2), a coding wheel output interface (4) is fixedly provided at the other end of the front side of the SDDP board body (1), a GPIB output interface (5) is fixedly provided on one side of the coding wheel output interface (4), a power supply interface (6) is fixedly provided at one end of the front side of the SDDP board body (1), and a front panel connector (7) is fixedly provided on the rear side of the SDDP board body (1); An FPGA (8) is fixedly arranged inside the SDDP board (1); the FPGA (8) is connected to the deep combination input interface (2) via a differential receiving circuit (9) or a single-ended receiving circuit (10); and a switch (11) is fixedly arranged at the input end of the differential receiving circuit (9) or the single-ended receiving circuit (10); The output ends of the other combined input interfaces (3) are respectively connected to a tension amplification filter circuit (12) and an MMD amplification circuit (13); the output ends of the tension amplification filter circuit (12) and the MMD amplification circuit (13) are both fixedly connected to a multi-way switch (14); and the multi-way switch (14) is connected to the FPGA (8) via an A / D converter (15); The output end of the FPGA (8) is connected to a PCI bus (16), the output end of the PCI bus (16) is connected to a network interface (17), a SOM-7567 (18) is arranged inside the PCI bus (16), and the output end of the SOM-7567 (18) is connected to a display screen serial interface (19), a GPIB interface (20) and a 485 conversion interface (21); The SDDP board (1) is laid flat, the board length of the SDDP board (1) is set to 220 mm, the board width is set to 122 mm, and the SDDP board (1) is fixed with six copper pillars, namely four copper pillars at four corners and two copper pillars in the middle; The FPGA (8) is internally provided with a jitter calibration (24) and a direction detector (25); an output end of the jitter calibration (24) is connected to an input end of the direction detector (25); an output end of the direction detector (25) is respectively connected to a first round up counter (26), a second round down counter (27), a second round up counter (28) and a second round down counter (29); an analog circuit (30) is internally provided with an analog circuit (30); an output end of the analog circuit (30) is respectively connected to a first round up counter (26), a second round down counter (27), a second round up counter (28) and a second round down counter (29).

2. The Depth Panel with separated display and operating system according to claim 1, characterized in that: The deep combination input interface (2) is configured to be introduced by a 12-core connector, and the switch (11) is configured to be a control bit control micro relay.

3. The depth panel with separated display and operating system according to claim 1, characterized in that: A backup circuit (22) is fixedly arranged between the switch (11) and the FPGA (8) and between other combined input interfaces (3) and the multi-way switch (14).

4. The depth panel with separated display and operating system according to claim 1, characterized in that: The FPGA (8) is connected to an alarm device (23) via K5 output. The alarm device (23) is configured as a buzzer and outputs a brake control signal via K6. The alarm signal is led out via a front panel connector, and the brake signal is led out via a 10-core connector.

5. The depth panel with separated display and operating system according to claim 1, characterized in that: The network interface (17) is configured as a BASE-T network interface, and both the network interface (17) and the GPIB interface (20) exchange data with a host computer via a plug-in.

6. The depth panel with separated display and operating system according to claim 1, characterized in that: The encoding wheel output interface (4) is configured as a 10-core interface, and the 485 conversion interface (21) is configured as a video interface.

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