Display Panel

Abstract

A display panel is provided. The display panel comprises: a substrate, comprising a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements located in the display area; a plurality of scan lines extending in a first direction and arranged around an edge of the opening area; a plurality of data lines extending in a second direction intersecting the first direction, and arranged around an edge of the opening area; and a plurality of emission control lines extending in the first direction and arranged around an edge of the opening area.

Description

[0001] The Korean Patent Application No. “10-2018-0133908” filed on November 2, 2018 in the Korean Intellectual Property Office and entitled “DISPLAY PANEL” is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments relate to a display panel. Background Art

[0003] In recent years, display devices have been diversified in purpose and function. In addition, as display devices have become thinner and lighter, their scope of use has gradually increased.

[0004] As the display device is variously utilized, there may be various methods in designing the shape of the display device, and further, various functions that may be combined or associated with the display device are increasing. Summary of the invention

[0005] An embodiment can be implemented by providing a display panel, which includes: a substrate, including a display area surrounding an opening area and a non-display area located between the opening area and the display area; a plurality of display elements located in the display area; a plurality of scan lines extending in a first direction and arranged around an edge of the opening area; a plurality of data lines extending in a second direction intersecting the first direction, and the plurality of data lines arranged around an edge of the opening area; and a plurality of emission control lines extending in the first direction and arranged around an edge of the opening area.

[0006] The detour portion of a first emission control line among the plurality of emission control lines may be located between detour portions of adjacent data lines among the plurality of data lines in the non-display area.

[0007] The detour portion of a first scan line among the plurality of scan lines may be located between detour portions of adjacent data lines among the plurality of data lines in the non-display area.

[0008] The detour portion of the first scan line and the detour portion of the first emission control line may be spaced apart from each other by a predetermined interval between the detour portions of the adjacent data lines.

[0009] The display panel may further include a plurality of previous scan lines extending in the first direction and detouring around an edge of the opening area, wherein one previous scan line of the plurality of previous scan lines is connected to the detouring portion of the first scan line.

[0010] A second emission control line adjacent to the first emission control line among the plurality of emission control lines may be connected to a detour portion of the first emission control line.

[0011] Each of the multiple display elements can be connected to a pixel circuit, which includes: a switching thin film transistor, connected to a scan line among a plurality of scan lines and a data line among a plurality of data lines; a driving thin film transistor, electrically connected to the switching thin film transistor, and driving current to flow through the driving thin film transistor in response to a data signal of the switching thin film transistor; and a control thin film transistor, electrically connected to the driving thin film transistor, wherein the first emission control line can be electrically connected to a gate electrode of the control thin film transistor.

[0012] The control thin film transistor may include an emission control thin film transistor connected to the driving thin film transistor and configured to transmit a driving current to a display element electrically connected to the driving thin film transistor.

[0013] The display panel may further include a plurality of voltage lines extending in the second direction and providing a driving voltage to the display element, wherein the control thin film transistor includes an operation control thin film transistor connecting the driving thin film transistor to the voltage line corresponding to the driving thin film transistor.

[0014] The first emission control line may include an extension portion passing through the display area, the display panel further includes an insulating layer located between the detour portion of the first emission control line and the extension portion, and the detour portion of the first emission control line may contact the extension portion through a contact hole of the insulating layer.

[0015] The detour portion of the first emission control line may be located on the same layer on which a pixel electrode is arranged, the pixel electrode being provided for each of the plurality of display elements.

[0016] The display panel may further include an upper insulating layer between the detour portion of the first emission control line and the plurality of data lines, wherein the detour portion of the first emission control line is located between the insulating layer and the upper insulating layer.

[0017] The display panel may further include a plurality of initialization voltage lines spaced apart from each other around the opening region.

[0018] The plurality of initialization voltage lines may be connected to each other through an electrode layer having a ring shape and located in the non-display area.

[0019] Initialization voltage lines located on the first side of the opening region among the plurality of initialization voltage lines may be connected to each other through a stripe-type electrode layer in the non-display region.

[0020] An embodiment can be implemented by providing a display panel, which includes: a substrate including an opening area, a display area surrounding the opening area, and a non-display area located between the opening area and the display area; a plurality of display elements located in the display area, each display element including a pixel electrode, a counter electrode facing the pixel electrode, and an emission layer located between the pixel electrode and the counter electrode; a plurality of first lines extending in a first direction and circling along an edge of the opening area; a plurality of second lines extending in a second direction intersecting the first direction and circling along an edge of the opening area; and a plurality of third lines extending in the first direction and circling along an edge of the opening area, wherein at least one of the plurality of third lines includes: an extension portion spaced apart from each other around the opening area; an insulating layer located on the extension portion; and a detour portion connected to the extension portion through a contact hole of the insulating layer, and wherein the detour portion is located between the detour portions of adjacent second lines in the non-display area.

[0021] Each of the plurality of first lines may include a scan line, and each of the plurality of second lines may include a data line.

[0022] Each of the plurality of third lines may include an emission control line.

[0023] The detour portion may include the same material as that of the pixel electrode.

[0024] Each of the display elements can be connected to a driving thin film transistor, a storage capacitor and a voltage line, the storage capacitor includes a first storage capacitor plate and a second storage capacitor plate, the voltage line is configured to provide a voltage to the second storage capacitor plate, and the bypass portion may include the same material as the second storage capacitor plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 shows a perspective view of a display device according to an embodiment;

[0027] Figure 2 shows a cross-sectional view of a display device according to an embodiment;

[0028] FIG. 3A to FIG. 3C shows a cross-sectional view of a display panel according to an embodiment;

[0029] FIG. 4A to FIG. 4C shows a cross-sectional view of a display panel according to another embodiment;

[0030] Figure 5 shows a plan view of a display panel according to an embodiment;

[0031] Figure 6 An equivalent circuit diagram of one pixel of a display panel according to an embodiment is shown;

[0032] Fig. 7A A plan view showing a pixel of a display panel according to an embodiment;

[0033] Figure 7B Shown along Fig. 7A A cross-sectional view taken along line AA' and line BB';

[0034] Figure 8 A plan view showing lines around an opening area in a display panel according to an embodiment;

[0035] Fig. 9 Shown along Figure 8 A sectional view taken along line IX-IX';

[0036] Fig.10 Shown along Figure 8 A cross-sectional view taken along line XX';

[0037] Fig.11 A plan view showing an emission control line and an emission control driver in a display panel according to an embodiment;

[0038] Fig.12 and Fig.13 A plan view showing lines around an opening area in a display panel according to another embodiment;

[0039] Fig.14 A plan view showing lines around an opening area in a display panel according to another embodiment;

[0040] Fig.15 Shown along Fig.14 A sectional view taken along line XV-XV';

[0041] Fig.16 A plan view showing lines around an opening area in a display panel according to another embodiment;

[0042] Fig.17 Shown along Fig.16 A cross-sectional view taken along line XVII-XVII'; and

[0043] Fig.18 A plan view showing a portion of a display panel according to another embodiment is shown. DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0045] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity. It will also be understood that when a layer or element is referred to as being "on" another layer or element, the layer or element may be directly on the other layer or element, or there may be intervening layers or elements. In addition, it will be understood that when a layer is referred to as being "below" another layer, the layer may be directly below the other layer, or there may be one or more intervening layers. In addition, it will be understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. The same reference numerals represent the same elements throughout.

[0046] As used herein, the terms "or" and "and / or" include any and all combinations of one or more of the relevant listed items. For example, "at least one of a, b, and c" can be understood as only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0047] Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0048] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component.

[0049] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] It will also be understood that the terms “comprises / includes” and / or variations thereof used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0051] When a specific embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0052] The embodiment can prevent wiring and the like arranged outside the display area from being viewed due to external light. However, it should be understood that the effects described herein should be considered in a descriptive sense only and not for limiting the disclosure.

[0053] It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, the layer, region, or component may be “directly connected” to the other layer, region, or component, or may be “indirectly connected” to the other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “connected or electrically connected” to another layer, region, or component, the layer, region, or component may be “directly connected or directly electrically connected” to the other layer, region, or component, or may be “indirectly connected or indirectly electrically connected” to the other layer, region, or component with other layers, regions, or components interposed therebetween.

[0054] Figure 1 A perspective view of a display device 1 according to an embodiment is shown.

[0055] Reference Figure 1 , the display device 1 may include a display area DA that emits light and a non-display area NDA that does not emit light. The non-display area NDA is adjacent to the display area DA. The display device 1 may provide a predetermined image by using light emitted from a plurality of pixels arranged in the display area DA.

[0056] The display device 1 may include an opening area (or first area) OA at least partially surrounded by a display area (or second area) DA. Figure 1 As shown in , the opening area OA may be completely surrounded by the display area DA. The non-display area NDA may include a first non-display area (or third area) NDA1 surrounding the opening area OA and a second non-display area (or fourth area) NDA2 surrounding the periphery of the display area DA. In an embodiment, the first non-display area NDA1 may completely surround the opening area OA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0057] In an embodiment, an organic light emitting display device is exemplarily described as a display device 1 according to an embodiment below. In an embodiment, various types of display devices such as a liquid crystal display, an inorganic light emitting display, and a quantum dot light emitting display may be used.

[0058] In an embodiment, if Figure 1 As shown in , one opening area OA may be disposed in the upper left side of the display area DA. In embodiments, the number of the opening areas OA and the positions of the opening areas OA may be variously modified.

[0059] Figure 2 A cross-sectional view of a display device 1 according to an embodiment is shown, and Figure 1 Corresponding to the cross-section taken by line II-II'.

[0060] Reference Figure 2 , the display device 1 may include a display panel 10, an input sensing layer 40 located on the display panel 10, and an optical functional layer (or anti-reflection layer) 50. These layers may be covered by a window 60. The display device 1 may include various electronic devices such as mobile phones, laptop computers, and smart watches.

[0061] The display panel 10 may display an image. The display panel 10 may include pixels arranged in a display area DA. Each pixel may include a display element and a pixel circuit connected to the display element. The display element may include a liquid crystal, an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0062] The input sensing layer 40 may obtain coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be arranged on the display panel 10. The input sensing layer 40 may sense an external input using a mutual capacitance method and / or a self capacitance method.

[0063] The input sensing layer 40 may be directly formed on the display panel 10, or may be separately formed and then bonded by using an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing layer 40 may be continuously formed after the process of forming the display panel 10. In this case, no adhesive layer may be arranged between the input sensing layer 40 and the display panel 10. In an embodiment, as shown in FIG. Figure 2 As shown in FIG. 1 , the input sensing layer 40 may be disposed between the display panel 10 and the optical function layer 50 . In an embodiment, the input sensing layer 40 may be disposed on the optical function layer 50 .

[0064] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflection of light (external light) incident from the outside through the window 60 toward the display panel 10. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal polarizer may include liquid crystals arranged in a predetermined arrangement. Each of the retarder and the polarizer may also include a protective film. The retarder and the polarizer themselves or their protective films may be defined as a substrate layer of the anti-reflection layer.

[0065] In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged by considering the color of the light emitted from the pixels of the display panel 10 respectively. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively arranged in different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may generate destructive interference, thereby reducing the reflection of external light.

[0066] The optical function layer 50 may include a lens layer. The lens layer may help improve the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of the light. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or include a plurality of layers having different refractive indices, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or include one of the anti-reflection layer and the lens layer.

[0067] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may include an opening. In this regard, Figure 2 The display panel 10, the input sensing layer 40, and the optical function layer 50 are shown to include a first opening 10H, a second opening 40H, and a third opening 50H, respectively, and the first opening 10H, the second opening 40H, and the third opening 50H of the display panel 10, the input sensing layer 40, and the optical function layer 50 are overlapped (e.g., aligned) with each other. The first opening 10H, the second opening 40H, and the third opening 50H may correspond to the opening area OA. In an embodiment, at least one of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. For example, one or two of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. In the following, the opening area OA may represent at least one of the first opening 10H, the second opening 40H, and the third opening 50H of the display panel 10, the input sensing layer 40, and the optical function layer 50. For example, in the present specification, the opening area OA may represent the first opening 10H of the display panel 10.

[0068] The component 20 may correspond to, align with, overlap, or be located in the opening area OA. Figure 2 As shown by the solid lines, the component 20 may be located inside the first opening 10H, the second opening 40H, and the third opening 50H, or as shown by the dotted lines, the component 20 may be located below the display panel 10. In an embodiment, the opening area OA may be understood as a component area.

[0069] Component 20 may include electronic components. For example, component 20 may include electronic components that use light or sound. For example, the electronic component may be a sensor such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. Electronic components that use light may use light in various bands such as visible light, infrared light, and ultraviolet light. In an embodiment, the opening area OA may be understood as a transmission area through which light and / or sound that is output from component 20 to the outside or propagates from the outside toward the electronic component can pass.

[0070] In an embodiment, when the display device 1 is used as a smart watch or a dashboard for a car, the component 20 may be a member including a clock hand or a pointer indicating predetermined information (e.g., the speed of the vehicle, etc.). When the display device 1 includes a clock hand or a pointer for a dashboard of a car, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the opening area OA.

[0071] As described above, the assembly 20 may include elements related to the function of the display panel 10 or elements such as decorations that increase the aesthetics of the display panel 10. In an embodiment, a layer including an OCA or the like may be located between the window 60 and the optical functional layer 50.

[0072] FIG. 3A to FIG. 3C A cross-sectional view of a display panel 10 according to an embodiment is shown.

[0073] Reference FIG. 3A to FIG. 3C The display panel 10 may include a display element layer 200 located on a substrate 100. The substrate 100 may include a glass material or a polymer resin. For example, the substrate 100 may include a SiO 2 A glass material as a main component, or a resin such as reinforced plastic may be included.

[0074] The display element layer 200 may correspond to the display area DA and may include a plurality of pixels. The display element layer 200 may include a pixel circuit corresponding to each pixel and a display element electrically connected to the pixel circuit. The pixel circuit may include a thin film transistor and a storage capacitor, and the display element may include an organic light emitting diode OLED (see Figure 6 ).

[0075] The display panel 10 may include an encapsulation substrate 340 facing the substrate 100 as an encapsulation member 300. A sealing material 350 may be located between the substrate 100 and the encapsulation substrate 340. The sealing material 350 may surround the display element layer 200 between the substrate 100 and the encapsulation substrate 340. For example, the sealing material 350 may surround a first edge (also referred to as an inner edge) of the display element layer 200 in the first non-display area NDA1, and surround a second edge (also referred to as an outer edge) of the display element layer 200 in the second non-display area NDA2. When viewed in a direction perpendicular to the main surface of the substrate 100, the opening area OA may be completely surrounded by the sealing material 350, and the second edge of the display element layer 200 may also be completely surrounded by the sealing material 350.

[0076] The display panel 10 may include a first opening 10H corresponding to the opening area OA. Figure 3A 2 shows that the substrate 100 and the packaging substrate 340 include through holes 100H and 340H corresponding to the opening area OA, respectively. The display element layer 200 may also include a through hole corresponding to the opening area OA.

[0077] In an embodiment, if Figure 3B As shown in , the package substrate 340 may include a through hole 340H corresponding to the opening area OA, but the substrate 100 may not include a through hole. Figure 3C As shown in , the substrate 100 and the encapsulation substrate 340 may not include a through hole corresponding to the opening area OA, respectively. The display element layer 200 may include a through hole corresponding to the opening area OA. In an embodiment, the sealing material 350 arranged in the first non-display area NDA1 of the display panel 10 may be omitted. In an embodiment, the display element layer 200 may not include a through hole corresponding to the opening area OA. A component 20 with relatively high transmittance is not required (see Figure 2 ) may be arranged in the opening area OA, and the opening area OA may be used as a transmission area that transmits light used by the component 20. Even when the display element layer 200 does not include a through hole corresponding to the opening area OA, the portion of the display element layer 200 corresponding to the opening area OA may be formed by not including a pixel circuit PC (see Figure 6 and Fig. 7A ) elements (e.g., transistors, storage capacitors, wiring, etc.) to ensure transmittance.

[0078] FIG. 4A to FIG. 4C is a cross-sectional view of a display panel 10 ′ according to another embodiment.

[0079] Reference Figure 4A, the display element layer 200 may be located on the substrate 100. The display element layer 200 may be covered by a thin film encapsulation layer as an encapsulation member 300'. The encapsulation member 300' as a thin film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, as Figure 4A As shown in FIG. 1 , there may be a first inorganic encapsulating layer 310 ′ and a second inorganic encapsulating layer 330 ′, and the organic encapsulating layer 320 ′ may be located between the first inorganic encapsulating layer 310 ′ and the second inorganic encapsulating layer 330 ′.

[0080] The first inorganic encapsulation layer 310' and the second inorganic encapsulation layer 330' may include one or more inorganic materials among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and silicon oxynitride. The organic encapsulation layer 320' may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide and polyethylene.

[0081] The substrate 100 may include a polymer resin and include a plurality of layers. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 that are sequentially stacked.

[0082] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, the first base layer 101 and the second base layer 103 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0083] Each of the first barrier layer 102 and the second barrier layer 104 may include a barrier layer configured to prevent penetration of external foreign substances and include a material including silicon nitride (SiN x , x>0), silicon oxide (SiO x , x>0) and / or a single layer or multiple layers of inorganic materials of silicon oxynitride.

[0084] In the case where the display panel 10 ′ includes the substrate 100 , which includes multiple layers, and the encapsulation member 300 ′, which is a thin film encapsulation layer, the flexibility of the display panel 10 ′ may be improved.

[0085] In an embodiment, if Figure 4AAs shown in FIG. 1 , through holes 100H and 300H' may be provided respectively penetrating the substrate 100 and the encapsulation member 300' which is a thin film encapsulation layer, and the through holes 100H and 300H' correspond to the first opening 10H of the display panel 10'. The display element layer 200 may also include a through hole corresponding to the opening area OA.

[0086] In an embodiment, if Figure 4B As shown in , the organic encapsulation layer 320' of the encapsulation member 300' which is a thin film encapsulation layer may include a through hole 320H' corresponding to the opening area OA, but the substrate 100 and the first and second inorganic encapsulation layers 310' and 330' may not include a through hole, respectively. Figure 4C As shown in , the layer of the encapsulation member 300' constituted as a thin film encapsulation layer may not include a through hole corresponding to the opening area OA. For example, the first inorganic encapsulation layer 310' and the second inorganic encapsulation layer 330' and the organic encapsulation layer 320' may cover the opening area OA. In an embodiment, in the case where the opening area OA is used as a transmission area for transmitting light, for example, in a component 20 (see FIG. 20 ) that does not require high transmittance Figure 2 ) is arranged in the opening area OA, FIG. 4A to FIG. 4C Different from that shown in FIG. 1 , the display element layer 200 may not include a through hole corresponding to the opening area OA. Even when the display element layer 200 does not include a through hole corresponding to the opening area OA, the portion of the display element layer 200 corresponding to the opening area OA may be formed by not including a pixel circuit PC (see FIG. 1 ). Figure 6 ) elements (e.g., transistors, storage capacitors, wiring, etc.) to ensure transmittance.

[0087] Figure 5 A plan view of a display panel 10 according to an embodiment is shown.

[0088] Reference Figure 5 , the display panel 10 may include a display area DA and first and second non-display areas NDA1 and NDA2 . Figure 5 It may be understood as a diagram of the substrate 100 in the display panel 10. For example, the substrate 100 may be understood as having an opening area OA, a first non-display area NDA1, and a second non-display area NDA2.

[0089] The display panel 10 may include a plurality of pixels P arranged in or on the display area DA. Each pixel P may include a display element such as an organic light emitting diode. Each pixel P may emit, for example, red light, green light, blue light, or white light through an organic light emitting diode. In this specification, as described above, a pixel P may be understood as a pixel that emits red light, green light, blue light, or white light. The opening area OA is arranged inside the display area DA, and the first non-display area NDA1 is located between the opening area OA and the display area DA.

[0090] The first non-display area NDA1 may surround the opening area OA. The first non-display area NDA1 may be an area in which a display element such as an organic light emitting diode is not arranged. Signal lines and / or power lines that provide signals to the pixels P disposed around the opening area OA may pass through the first non-display area NDA1.

[0091] Each pixel P may be electrically connected to an external circuit disposed in the second non-display area NDA2 surrounding the display area DA. The first external driving circuit 110, the second external driving circuit 120, the terminal 140, the first power line 160 and the second power line 170 may be disposed in the second non-display area NDA2.

[0092] The first external driving circuit 110 may include a scan driving circuit and a control driving circuit, and may provide a scan signal and an emission control signal to each pixel P through a scan line SWL and an emission control line EL. The second external driving circuit 120 may also include a scan driving circuit and a control driving circuit, and may be arranged side by side with the first external driving circuit 110. Similar to the first external driving circuit 110, the second external driving circuit 120 may provide a scan signal and an emission control signal to each pixel P through a scan line SWL and an emission control line EL.

[0093] The terminal 140 may be arranged on one side of the second non-display area NDA2. The terminal 140 may not be covered by the insulating layer and may be exposed and electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits a signal of a controller or a power supply to the display panel 10. The control signal generated by the controller may be transmitted to the first external driving circuit 110 and the second external driving circuit 120 respectively through the printed circuit board PCB. The controller may provide the first power ELVDD (see below) to the first power line 160 through the first connection wiring 161. Figure 6 ) and supplies the second power ELVSS to the second power line 170 through the second connection wiring 171 (see below Figure 6). A first power ELVDD (also referred to as a driving voltage) may be supplied to each pixel P through a driving voltage line PL connected to the first power line 160, and a second power ELVSS (also referred to as a common voltage) may be supplied to a counter electrode of the pixel P connected to the second power line 170.

[0094] The data driving circuit 150 may be electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each pixel P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. Figure 5 , the data driving circuit 150 is shown to be arranged on the printed circuit board PCB, but in another embodiment, the data driving circuit 150 may be arranged above the substrate 100. For example, the data driving circuit 150 may be arranged between the terminal 140 and the first power line 160.

[0095] The first power line 160 may include a first sub-line 162 and a second sub-line 163 extending side by side in the x-direction with the display area DA located therebetween. The second power line 170 may partially surround the display area DA in a ring shape with one side thereof opened.

[0096] Figure 6 An equivalent circuit diagram of one pixel P of the display panel 10 according to the embodiment is shown.

[0097] Reference Figure 6 , the pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor and a plurality of thin film transistors. The thin film transistors and the storage capacitor may be connected to the signal lines SWL, SIL, EL and DL, the initialization voltage line VL and the driving voltage line PL.

[0098] In an embodiment, if Figure 6 As shown in , each pixel P may be connected to signal lines SWL, SIL, EL and DL, initialization voltage line VL and driving voltage line PL. In an embodiment, at least one of the signal lines SWL, SIL, EL and DL, initialization voltage line VL and driving voltage line PL may be shared by adjacent pixels.

[0099] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0100] The signal line may include a scan line (Nth scan line) SWL configured to transmit a scan signal GW, a previous scan line ((N-1)th scan line) SIL configured to transmit a previous scan signal GI to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL configured to transmit an emission control signal EM to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SWL and configured to transmit a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode.

[0101] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm, and in response to the switching operation of the switching thin film transistor T2, the driving current I OLED Supply to the organic light emitting diode OLED.

[0102] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scanning line SWL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and is connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scanning signal GW transmitted through the scanning line SWL, and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0103] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SWL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1, and is connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal GW transmitted through the scan line SWL, and the driving thin film transistor T1 is diode-connected by electrically connecting the driving gate electrode G1 of the driving thin film transistor T1 to the driving drain electrode D1 of the driving thin film transistor T1.

[0104] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SIL, the first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal GI transmitted through the previous scan line SIL, and performs an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0105] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0106] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic emission diode OLED.

[0107] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal EM transmitted through the emission control line EL, so that the driving voltage ELVDD is transmitted to the organic light emitting diode OLED and the driving current I OLED Flow through the organic light emitting diode OLED.

[0108] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SIL, the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on in response to the previous scan signal GI transmitted through the previous scan line SIL to initialize the pixel electrode of the organic light emitting diode OLED.

[0109] In an embodiment, if Figure 6 As shown in , the first initialization thin film transistor T4 and the second initialization thin film transistor T7 may be connected to the previous scan line SIL. In an embodiment, the first initialization thin film transistor T4 may be connected to the previous scan line SIL and driven in response to the previous scan signal GI, and the second initialization thin film transistor T7 may be connected to a separate signal line (e.g., the next scan line or the (N+1)th scan line) and driven in response to a signal transmitted through the signal line.

[0110] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving thin film transistor T1. OLED and emits light to display images.

[0111] In an embodiment, if Figure 6 As shown in , each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may include a double gate electrode. In an embodiment, each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may include one gate electrode.

[0112] In an embodiment, if Figure 6 As shown in FIG. 1 , the pixel circuit PC may include seven thin film transistors and one storage capacitor. In an embodiment, the number of thin film transistors and the number of storage capacitors may be six or less or eight or less, and various modifications may be made according to the design. Figure 6 The pixel circuit PC shown in FIG. 1 is described below.

[0113] Fig. 7A 1 is a plan view showing one pixel P of the display panel 10 according to the embodiment, Figure 7B Shown along Fig. 7A A cross-sectional view taken along line AA' and line BB'.

[0114] Reference Fig. 7A and Figure 7B The driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6 and the second initialization thin film transistor T7 are arranged along the semiconductor layer 1130. Figure 7B As shown in , a semiconductor layer 1130 is located over a substrate 100 , and a buffer layer 2111 including an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride is formed under the semiconductor layer 1130 .

[0115] Some areas of the semiconductor layer 1130 correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. For example, it can be understood that the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 are connected to each other and bent into various shapes. Figure 7B A driving semiconductor layer 1130 a of the driving thin film transistor T1 , a compensation semiconductor layer 1130 c of the compensation thin film transistor T3 , and an emission control semiconductor layer 1130 f of the emission control thin film transistor T6 , which respectively correspond to some regions of the semiconductor layer 1130 , are shown.

[0116] The semiconductor layer 1130 may include a channel region and a source region and a drain region respectively located on two opposite sides of the channel region. The source region and the drain region may be understood as the source electrode and the drain electrode of the related thin film transistor. Hereinafter, for the convenience of description, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0117] The driving thin film transistor T1 may include a driving gate electrode G1 overlapping the driving channel region C1, and a driving source electrode S1 and a driving drain electrode D1 respectively located on two opposite sides of the driving channel region C1. The driving channel region C1 overlapping the driving gate electrode G1 may form a long length channel inside a narrow space by having a curved shape such as an Ω shape. In the case where the length of the driving channel region C1 is long, the driving range of the gate voltage becomes wide, and thus the gray level of light emitted from the organic light emitting diode OLED may be more finely controlled, thereby improving the display quality.

[0118] The switching thin film transistor T2 may include a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 respectively located on two opposite sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0119] The compensation thin film transistor T3 may be a double thin film transistor, may include a compensation gate electrode G3 overlapping two compensation channel regions C3, and may include a compensation source electrode S3 and a compensation drain electrode D3 located on two opposite sides of the compensation channel region C3, respectively. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 to be described below.

[0120] The first initialization thin film transistor T4 may be a dual thin film transistor, and may include a first initialization gate electrode G4 overlapping two first initialization channel regions, and include a first initialization source electrode S4 and a first initialization drain electrode D4 respectively located on two opposite sides of the first initialization channel region.

[0121] The operation control thin film transistor T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 respectively located on two opposite sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0122] The emission control thin film transistor T6 may include an emission control gate electrode G6 overlapping the emission control channel region and an emission control source electrode S6 and an emission control drain electrode D6 respectively located on two opposite sides of the emission control channel region. The emission control source electrode S6 may be connected to the drive drain electrode D1. The emission control thin film transistor T6 may be electrically connected to the pixel electrode 210 via the layer 2175. For example, the layer 2175 may contact the emission control drain electrode D6, and the pixel electrode 210 may contact the layer 2175 through the contact hole 1163 of the planarization insulating layer 2180.

[0123] The second initialization thin film transistor T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 respectively located on two opposite sides of the second initialization channel region.

[0124] The above-mentioned thin film transistors may be connected to the signal lines SWL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0125] Gate insulating layer 2141 (see Figure 7B) may be arranged on the semiconductor layer 1130. The scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL may be arranged on the gate insulating layer 2141. The gate insulating layer 2141 may include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride. The scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL may include a metal such as Mo, Al, Cu, Ti, and alloys thereof.

[0126] The scan line SWL may extend in the x direction. Some regions or portions of the scan line SWL may correspond to the switch gate electrode G2 and the compensation gate electrode G3, respectively. For example, regions or portions of the scan line SWL overlapping the channel regions of the switch thin film transistor T2 and the compensation thin film transistor T3 may be the switch gate electrode G2 and the compensation gate electrode G3, respectively.

[0127] The previous scan line SIL may extend in the x direction. Some regions or portions of the previous scan line SIL may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, regions or portions of the previous scan line SIL that overlap the channel regions of the first initialization thin film transistor T4 and the second initialization thin film transistor T7, respectively, may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0128] The emission control line EL may extend in the x direction. Some regions or portions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, regions or portions of the emission control line EL that overlap the channel regions of the operation control thin film transistor T5 and the emission control thin film transistor T6, respectively, may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0129] The driving gate electrode G1 is an island electrode and may be connected to the compensation thin film transistor T3 through a node connection line 1174 .

[0130] The initialization voltage line VL may extend in the x direction. The initialization voltage line VL may be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through an initialization connection line 1173 to be described below.

[0131] In an embodiment, if Figure 7B As shown in FIG. 2 , the initialization voltage line VL may be disposed on the gate insulating layer 2141. In an embodiment, the initialization voltage line VL may be disposed on the planarization insulating layer 2180 (see FIG. 2140 ) to be described below. Figure 7B ) and may include the same material as that of the pixel electrode 210 in another embodiment. In an implementation, the initialization voltage line VL may be arranged on the first interlayer insulating layer 2143 (see Figure 7B The initialization voltage line VL may include the same material as that of the second storage capacitor plate Cst2.

[0132] The electrode voltage line HL may be disposed above the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL, and includes a first interlayer insulating layer 2143 of an inorganic material (see Figure 7B ) is located therebetween.

[0133] like Fig. 7A As shown in , the electrode voltage line HL may extend in the x direction to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1, and may cooperate with the driving gate electrode G1 to form a storage capacitor Cst. For example, the driving gate electrode G1 may serve as a first storage capacitor plate Cst1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as a second storage capacitor plate Cst2 of the storage capacitor Cst.

[0134] The driving voltage line PL and the second storage capacitor plate Cst2 are electrically connected to each other. In this regard, Fig. 7A 1150 shows that the electrode voltage line HL is connected to the driving voltage line PL arranged on the electrode voltage line HL through the contact hole 1158. The electrode voltage line HL may have the same voltage level (constant voltage, such as +5V) as the driving voltage line PL. The electrode voltage line HL may be understood as a lateral driving voltage line.

[0135] The driving voltage line PL may extend in the y direction, and the electrode voltage line HL electrically connected to the driving voltage line PL may extend in the x direction crossing the y direction, and the plurality of driving voltage lines PL and the plurality of electrode voltage lines HL may constitute a grid structure in the display area DA.

[0136] The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 may be disposed on the second storage capacitor plate Cst2 and the electrode voltage line HL, and include a second interlayer insulating layer 2150 of an inorganic material (see Figure 7B ) is placed therebetween. The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 may include at least one of Al, Cu, and Ti, and may include a single layer or multiple layers. In an implementation, the driving voltage line PL and the data line DL may have a multilayer structure including Ti / Al / Ti.

[0137] The data line DL may extend in the y direction, and may be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0138] The driving voltage line PL may extend in the y direction and may be connected to the electrode voltage line HL through the contact hole 1158. In addition, the driving voltage line PL may be connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 through the contact hole 1155.

[0139] One end of the initialization connection line 1173 may be connected to the first and second initialization thin film transistors T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VL through the contact hole 1151 .

[0140] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0141] A planarization insulating layer 2180 including an organic insulating material is positioned on the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174. The pixel electrode 210 is disposed on the planarization insulating layer 2180.

[0142] Reference Figure 7B , the edge of the pixel electrode 210 may be covered by the pixel defining layer 2190 on the planarization insulating layer 2180. The central area of ​​the pixel electrode 210 may be exposed through the opening of the pixel defining layer 2190. The pixel electrode 210 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof. In an embodiment, the pixel electrode 210 may also include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 The intermediate layer 220 is disposed on a portion of the pixel electrode 210 exposed by the opening.

[0143] The intermediate layer 220 may include an emission layer 222 located on a portion of the pixel electrode 210 exposed by the opening of the pixel defining layer 2190. The emission layer 222 may include a polymer material or a low-molecular organic material that emits light of a predetermined color. Figure 7B As shown in , the intermediate layer 220 may include a first functional layer 221 located below the emission layer 222 and / or a second functional layer 223 located on the emission layer 222 .

[0144] The first functional layer 221 may include a single layer or multiple layers. For example, in the case where the first functional layer 221 includes a polymer material, the first functional layer 221 may include a hole transport layer (HTL) having a single layer structure, and may include poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In the case where the first functional layer 221 includes a low molecular organic material, the first functional layer 221 may include a hole injection layer (HIL) and the HTL.

[0145] In an embodiment, the second functional layer 223 may be omitted. For example, in the case where the first functional layer 221 and the emission layer 222 include a polymer material, the second functional layer 223 may be provided to make the characteristics of the organic light emitting diode OLED excellent. The second functional layer 223 may be a single layer or a multilayer. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0146] The counter electrode 230 is arranged to face the pixel electrode 210, and the intermediate layer 220 is located therebetween. The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. In an embodiment, the counter electrode 230 may also include a (semi) transparent layer including ITO, IZO, ZnO, or Indium on the (semi) transparent layer including the above materials. 2 O 3 layer.

[0147] In an embodiment, the display element layer 200 (eg, the layer from the buffer layer 2111 to the counter electrode 230) disposed on the substrate 100 may be FIG. 3A to FIG. 4C Description of the package component covered.

[0148] Figure 8 A plan view showing lines around an opening area OA in a display panel 10 according to an embodiment, Fig. 9 Shown along Figure 8 A cross-sectional view taken along line IX-IX', Fig.10 Shown along Figure 8 A cross-sectional view taken along line XX'. In an embodiment, Figure 8 As shown in FIG, six pixels may be arranged at each of the upper side, the lower side, the left side, and the right side of the opening area OA. In an embodiment, a greater number of pixels and / or a greater number of lines may be arranged.

[0149] Reference Figure 8, the data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6 and DL7 and the driving voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6 and PL7 may extend in the y direction. Figure 8 The driving voltage lines PL1, PL2, PL3, PL4, PL5, PL6, and PL7 in the embodiment of the present invention may be disconnected from the opening area OA. Portions of the driving voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 located at the upper side of the opening area OA may be connected to the second sub-line 163 (see FIG. Figure 5 ), portions of the driving voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 located at the lower side of the opening area OA may be connected to the first sub-line 162 (see Figure 5 ).

[0150] Some of the data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7 (e.g., the first to sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6) passing through the display area DA may be arranged around the edge of the opening area OA in the first non-display area NDA1. Figure 8 Each of the strips connecting the pixels P arranged on the upper and lower sides of the opening area OA may include a portion extending in the y direction in the display area DA and a portion surrounding the edge of the opening area OA in the first non-display area NDA1. Figure 8 As shown in , the detour portion of the data line DL may have an arc curve. In an embodiment, the detour portion may be a line bent in a zigzag shape. In an embodiment, the detour portion of each of the other lines may have an arc curve, or the detour portion may be a line bent in a zigzag shape.

[0151] exist Figure 8 , the pixels P located on the upper and lower sides of the opening area OA may be electrically connected to the first to sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6 arranged around the opening area OA, and may receive data signals through the connected data lines. The first to third data lines DL1, DL2, and DL3 among the first to sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6 may be arranged around the opening area OA on a first side (e.g., left side) of the opening area OA, and the fourth to sixth data lines DL4, DL5, and DL6 may be arranged around the opening area OA on a second side (e.g., right side) of the opening area OA.

[0152] The scan lines SWL0, SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, and SWL7 and the previous scan lines SIL0, SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, and SIL7 may extend in the x direction intersecting the y direction. Some of the scan lines SWL0, SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, and SWL7 (e.g., the first to sixth scan lines SWL1, SWL2, SWL3, SWL4, SWL5, and SWL6) and the previous scan lines SIL0, SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, and SIL7 (e.g., the first to sixth previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5, and SIL6) may be arranged around the opening area OA. For example, the first to third scan lines SWL1, SWL2 and SWL3 and the first to third previous scan lines SIL1, SIL2 and SIL3 may be arranged around the opening area OA on a third side (e.g., an upper side) of the opening area OA, and the fourth to sixth scan lines SWL4, SWL5 and SWL6 and the fourth to sixth previous scan lines SIL4, SIL5 and SIL6 may be arranged around the opening area OA on a fourth side (e.g., a lower side) of the opening area OA.

[0153] The first to sixth scan lines SWL1, SWL2, SWL3, SWL4, SWL5, and SWL6 and the first to sixth previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5, and SIL6 may be as described with reference to Fig. 7A and Figure 7B It is described as being located on the gate insulating layer 2141 in the display area DA, and even if located in the first non-display area NDA1, it may surround the opening area OA while being located on the gate insulating layer 2141.

[0154] The emission control lines EL0, EL1, EL2, EL3, EL4, EL5, EL6, and EL7 may extend in the x direction. Some of the emission control lines EL0, EL1, EL2, EL3, EL4, EL5, EL6, and EL7 (e.g., the first to sixth emission control lines EL1, EL2, EL3, EL4, EL5, and EL6) may be arranged around the opening area OA. For example, the first to third emission control lines EL1, EL2, and EL3 may be arranged around the opening area OA on the upper side of the opening area OA, and the fourth to sixth emission control lines EL4, EL5, and EL6 may be arranged around the opening area OA on the lower side of the opening area OA.

[0155] Each of the first to sixth emission control lines EL1, EL2, EL3, EL4, EL5, and EL6 includes an extension portion EL-E located in the display area DA and a detour portion EL-C located in the first non-display area NDA1. The extension portion EL-E and the detour portion EL-C may be located on different layers (e.g., at different distances from the substrate 100), respectively. Fig. 9 , the extension portion EL-E of the sixth emission control line EL6 may be located (e.g., directly located) on the gate insulating layer 2141, and the detour portion EL-C of the sixth emission control line EL6 may be located (e.g., directly located) on the planarization insulating layer 2180. The extension portion EL-E and the detour portion EL-C of the sixth emission control line EL6 may be electrically connected to each other through the first contact hole CNT1, and the middle metal ML may be located therebetween. In an embodiment, the extension portion EL-E of the sixth emission control line EL6 may be located (e.g., directly located) on the first interlayer insulating layer 2143.

[0156] The middle metal ML may be located on the second interlayer insulating layer 2150. The middle metal ML may be connected to the extension portion EL-E through the (1-1)th contact hole CNT1-1 of the first interlayer insulating layer 2143 and the second interlayer insulating layer 2150, respectively, and the detour portion EL-C may be connected to the middle metal ML through the (1-2)th contact hole CNT1-2, respectively. The middle metal ML may include an island metal disposed only in a region corresponding to the first contact hole CNT1, and include the same material as that of the data line. The detour portion EL-C on the planarizing insulating layer 2180 may include the same material as that of the reference Figure 7B The same material as the material of the pixel electrode 210 described above. Fig. 9 Similar to the structure of the sixth emission control line EL6 shown in FIG, each of the first to fifth emission control lines EL1, EL2, EL3, EL4, and EL5 may include an extending portion EL-E and a detour portion EL-C respectively arranged in different layers.

[0157] The interval between adjacent data lines in the first non-display area NDA1 (eg, the interval d between the detour portions of the adjacent data lines) may be larger than the interval D between adjacent data lines in the display area DA (see FIG. 1 ). Figure 8 ) is small. The display quality of some pixels in the display area DA may be degraded due to coupling caused between the detour portions of the data lines arranged with a relatively narrow interval d. In contrast, according to an embodiment, the detour portion EL-C may be arranged between adjacent data lines in the first non-display area NDA1, which can minimize the problem caused by the occurrence of the above-mentioned coupling.

[0158] In the first non-display area NDA1, the detour portions of the first to sixth scan lines SWL1, SWL2, SWL3, SWL4, SWL5 and SWL6 and the detour portions of the first to sixth previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5 and SIL6 may be located on a layer different from a layer on which the detour portions EL-C of the first to sixth emission control lines EL1, EL2, EL3, EL4, EL5 and EL6 are arranged. At the same time, in the first non-display area NDA1, the detour portions of the first to sixth scan lines SWL1, SWL2, SWL3, SWL4, SWL5 and SWL6 and the detour portions of the first to sixth previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5 and SIL6 can be separated from each other without overlapping with the detour portions EL-C of the first to sixth emission control lines EL1, EL2, EL3, EL4, EL5 and EL6.

[0159] For example, Fig.10 As shown in , the detour portion EL-C of the second emission control line EL2, the second scan line SWL2, and the second previous scan line SIL2 between the fourth data line DL4 and the fifth data line DL5 adjacent to each other may be spaced apart from each other. For example, when the display panel 10 is viewed from a direction perpendicular to the top surface of the substrate 100, the fourth data line DL4 may be spaced apart from the detour portion EL-C of the second emission control line EL2 (e.g., laterally) by a first interval d1, the detour portion EL-C of the second emission control line EL2 may be spaced apart from the second scan line SWL2 by a second interval d2, the second scan line SWL2 may be spaced apart from the second previous scan line SIL2 by a third interval d3, and the second previous scan line SIL2 may be spaced apart from the fifth data line DL5 by a fourth interval d4.

[0160] like Figure 8As shown in , the initialization voltage line VL of each pixel P may extend in the x direction in the display area DA, and the initialization voltage line VL that transmits the initialization voltage to the pixels arranged in the left and right sides of the opening area OA may be disconnected around the opening area OA. The initialization voltage line VL disconnected around the opening area OA may be connected to the electrode layer VL-R arranged in the first non-display area NDA1 through the second contact hole CNT2. The electrode layer VL-R may have a ring shape surrounding the opening area OA.

[0161] As mentioned above Fig. 7A and Figure 7B As described, the initialization voltage line VL may be disposed on the first interlayer insulating layer 2143, and the electrode layer VL-R may be disposed on the planarization insulating layer 2180. The electrode layer VL-R may be connected to the initialization voltage line VL through the second contact hole CNT2.

[0162] Fig.11 A plan view of emission control lines and an emission control driver in the display panel 10 according to an embodiment is shown. Fig.11 The first emission control lines EL1, EL2, EL3 and EL4 are the same as those in the above reference Figures 8 to 10 The descriptions of the first to fourth emission control lines EL1, EL2, EL3, and EL4 correspond.

[0163] The first emission control line EL1 can be Fig.11 The first emission control driver 120Aa in the second non-display area NDA2 on the right side of the opening area OA receives the emission control signal, and the relevant signal can be provided to the pixels arranged on the left and right sides of the opening area OA respectively through the extension portion EL-E, the detour portion EL-C and the other extension portion EL-E of the first emission control line EL1. Similarly, the second emission control line EL2 can be provided from the pixels located at Fig.11 The second emission control driver 120Ab in the second non-display area NDA2 on the right side receives the emission control signal, and the relevant signal can be provided to the pixels respectively arranged on the left and right sides of the opening area OA through the extending portion EL-E, the bypass portion EL-C and the other extending portion EL-E of the second emission control line EL2.

[0164] The third emission control line EL3 can be Fig.11 The third emission control driver 110Aa in the second non-display area NDA2 on the left side of the opening area OA receives the emission control signal, and the relevant signal can be provided to the pixels arranged on the left and right sides of the opening area OA respectively through the extension portion EL-E, the detour portion EL-C and the other extension portion EL-E of the third emission control line EL3. Similarly, the fourth emission control line EL4 can be provided from the pixels located at Fig.11 The fourth emission control driver 110Ab in the second non-display area NDA2 on the left side receives the emission control signal, and the relevant signal can be provided to the pixels respectively arranged on the left and right sides of the opening area OA through the extended portion EL-E, the bypass portion EL-C and the other extended portion EL-E of the fourth emission control line EL4.

[0165] In some other devices, if the first emission control lines EL1 are spaced apart from each other around the opening area OA without including the detour portion EL-C (for example, the first emission control line EL1 includes only the extension portion EL-E), a pair of first emission control drivers 120Aa are required in the second non-display area NDA2 on the left and right sides of the display area DA, respectively. Similarly, in the case where the second to fourth emission control lines EL2, EL3, and EL4 are spaced apart from each other around the opening area OA without including the detour portion EL-C, a pair of second to fourth emission control drivers 120Ab, 110Aa, and 110Ab are required in the second non-display area NDA2 on the left and right sides of the display area DA, respectively. In this case, the area of ​​the second non-display area NDA2 is increased.

[0166] On the contrary, according to the embodiment, Fig.11 As shown in FIG. 1 , each of the first to fourth emission control lines EL1, EL2, EL3, and EL4 may include a detour portion EL-C connected to the extension portion EL-E, which may reduce the number of lines arranged in the Fig.11 The number of emission control drivers in the second non-display area NDA2 and the area of ​​the second non-display area NDA2 are determined.

[0167] In an embodiment, if Fig.11 As shown in , the first to fourth emission control drivers 120Aa, 120Ab, 110Aa, and 110Ab may be alternately arranged in pairs on the left and right sides around the display area DA. In an embodiment, the first to fourth emission control drivers 120Aa, 120Ab, 110Aa, and 110Ab may be alternately arranged in the second non-display area NDA2 located on the left and right sides around the display area DA, respectively. For example, the first emission control driver 120Aa and the second emission control driver 120Ab may be arranged in the second non-display area NDA2 located on the right side of the display area DA, and the third emission control driver 110Aa and the fourth emission control driver 110Ab may be arranged in the second non-display area NDA2 located on the left side of the display area DA.

[0168] Fig.12 and Fig.13FIG. 2 is a plan view showing lines around the opening area OA in the display panel 10 according to another embodiment. Fig.12 and Fig.13 , each pixel P includes an electrode voltage line. In this regard, Fig.12 and Fig.13 First to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 are shown. For ease of description, although Fig.12 and Fig.13 Extracted and shown Figure 8 , among the lines shown in FIG. 1 , the first to sixth scan lines SWL1, SWL2, SWL3, SWL4, SWL5 and SWL6, the first to sixth previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5 and SIL6, the first to sixth emission control lines EL1, EL2, EL3, EL4, EL5 and EL6, and the first to sixth data lines DL1, DL2, DL3, DL4, DL5 and DL6 are included, but in another embodiment, Fig.12 and Fig.13 The display panel 10 may include a reference Figure 8 All components described above. Figure 8 Describes Fig.12 and Fig.13 Among the elements shown in Figure 8 The elements are the same as those of the components, so their description may be omitted, and the differences are mainly described below.

[0169] Reference Fig.12 In an embodiment, the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 of the pixel P extending in the x direction in the display area DA may be connected to each other in the first non-display area NDA1. The first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 connected to each other may be connected to a plurality of connection electrodes HL-R (or annular electrodes) surrounding the opening area OA in the first non-display area NDA1. Each connection electrode HL-R may have a ring shape.

[0170] like Fig.12 As shown in FIG. 1 , the connection electrodes HL-R may be arranged to form a concentric circle shape around the opening area OA and connected to the first to sixth electrode voltage lines HL1 , HL2 , HL3 , HL4 , HL5 , and HL6 to form a radial grid shape.

[0171] As reference Fig. 7A and Figure 7BAs described, the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 may be arranged on the first interlayer insulating layer 2143. The plurality of connection electrodes HL-R may be arranged on the same layer on which the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 are arranged, and may include the same material as the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6, and may be formed as one body with the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6.

[0172] The connection electrode HL-R having a ring shape may be located between detour portions of adjacent data lines in the first non-display area NDA1. The connection electrode HL-R having a voltage level of a constant voltage may reduce coupling between detour portions of adjacent data lines.

[0173] Reference Fig.13 In another embodiment, each of the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 may include a detour portion HL-C that detours around an edge of the opening area OA. The detour portion HL-C of each of the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 may be arranged between detour portions of adjacent data lines to reduce coupling therebetween.

[0174] Fig.14 A plan view showing lines around an opening area OA in a display panel 10 according to another embodiment, Fig.15 Shown along Fig.14 The cross-sectional view taken along the line XV-XV' of Figures 8 to 10 The lines described are compared to Fig.15 The lines of the display panel 10 are different in the stacking structure of the detour portion EL-C of the emission control line, and the description of the other lines is the same as that of the above reference Figures 8 to 10 The same description is performed.

[0175] Reference Fig.14 and Fig.15 , the detour portion EL-C may be disposed on the first interlayer insulating layer 2143. For example, the extension portion EL-E of the sixth emission control line EL6 disposed on the gate insulating layer 2141 may be connected to the detour portion EL-C located on the first interlayer insulating layer 2143 through the first contact hole CNT1. The detour portion EL-C may include the same material as that of the second storage capacitor plate Cst2.

[0176] Reference Fig.14, the display panel 10 may include an electrode voltage line. In this regard, Fig.14 First to sixth electrode voltage lines HL1 , HL2 , HL3 , HL4 , HL5 , and HL6 connected to pixels on the left and right sides around the opening area OA are shown.

[0177] The first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 may be spaced apart from each other around the opening area OA. Figure 7B As described above, the first to sixth electrode voltage lines HL1, HL2, HL3, HL4, HL5 and HL6 separated from each other may form a grid structure with the driving voltage line. Therefore, even if the electrode voltage lines HL are separated from each other around the opening area OA, the electrode voltage lines HL may maintain the same voltage level.

[0178] Reference Fig.15 The structure of the electrode voltage line described above is also applicable to Figure 8 The embodiments described and the following will refer to Fig.16 The described embodiments and / or embodiments derived therefrom.

[0179] Fig.16 A plan view showing lines around an opening area OA in a display panel 10 according to another embodiment, Fig.17 Shown along Fig.16 A cross-sectional view taken along line XVII-XVII'.

[0180] Reference Fig.16 , in the first non-display area NDA1, the scan line of one pixel in adjacent pixels may be connected to the previous scan line of the other pixel. For example, the first scan line SWL1 on the first row that transmits the scan signal to the pixels P arranged on the left and right sides of the opening area OA may be connected to the second previous scan line SIL2 on the second row in the first non-display area NDA1. For example, in the first non-display area NDA1, the second previous scan line SIL2 may be connected to a detour portion of the first scan line SWL1. On the other hand, in the first non-display area NDA1, the first scan line SWL1 may be connected to a detour portion of the second previous scan line SIL2. For example, the first scan line SWL1 and the second previous scan line SIL2 may share a detour portion. According to reference Figure 8 In the described embodiment, the detour portion of the second previous scan line SIL2 and the detour portion of the first scan line SWL1 may be detoured around the edge of the opening area OA separately. Fig.16In the embodiment shown in , the second previous scan line SIL2 and the first scan line SWL1 may detour around the edge of the opening area OA along a detour line (eg, a detour portion). For example, the number of scan lines and previous scan lines passing through the first non-display area NDA1 may be reduced.

[0181] Likewise, the second scan line SWL2 on the second row transmitting the scan signal to the pixels P arranged on the left and right sides of the opening area OA may be connected to the third previous scan line SIL3 on the third row in the first non-display area NDA1. The third scan line SWL3 on the third row may be connected to the fourth previous scan line SIL4 on the fourth row in the first non-display area NDA1, the fourth scan line SWL4 on the fourth row may be connected to the fifth previous scan line SIL5 on the fifth row in the first non-display area NDA1, and the fifth scan line SWL5 on the fifth row may be connected to the sixth previous scan line SIL6 on the sixth row in the first non-display area NDA1.

[0182] In an embodiment, if Fig.16 As shown in , the N-th previous scan line may be connected to the detour portion of the (N-1)-th scan line. In an embodiment, the (N-1)-th scan line may be connected to the detour portion of the N-th previous scan line (N is an integer).

[0183] In the first non-display area NDA1, the emission control line of one pixel of adjacent pixels may be connected to the emission control line of the other pixel. For example, the first emission control line EL1 on the first row that transmits the emission control signal to the pixels P arranged on the left and right sides of the opening area OA may be connected to the second emission control line EL2 on the second row in the first non-display area NDA1. For example, in the first non-display area NDA1, the second emission control line EL2 may be connected to the detour portion EL-C of the first emission control line EL1. According to the reference Figure 8 In the described embodiment, the detour portion EL-C of the first emission control line EL1 and the detour portion EL-C of the second emission control line EL2 are individually detour around the edge of the opening area OA. Fig.16 In the embodiment shown in FIG. 1 , the first emission control line EL1 and the second emission control line EL2 may be detoured around the edge of the opening area OA along one detour line (i.e., one detour portion EL-C). For example, the number of emission control lines may be reduced, that is, the number of detour lines of the emission control lines respectively passing through the first non-display area NDA1 may be reduced.

[0184] Likewise, the third emission control line EL3 on the third row may be connected to the fourth emission control line EL4 on the fourth row in the first non-display area NDA1, and the fifth emission control line EL5 on the fifth row may be connected to the sixth emission control line EL6 on the sixth row in the first non-display area NDA1.

[0185] In an embodiment, the Nth emission control line may be connected to a detour portion of the (N-1)th emission control line. In an embodiment, the (N-1)th emission control line may be connected to a detour portion of the Nth emission control line (N is an integer). As described above, in the case where the (N-1)th scan line and the Nth previous scan line are connected to each other, and the (N-1)th emission control line and the Nth emission control line are connected to each other, the detour portions of the scan lines connected to each other and the previous scan lines and the detour portions of the emission control lines connected to each other may be alternately arranged. Reference Fig.16 and Fig.17 , the detour portions of the emission control lines connected to each other, the detour portions of the scan line and the previous scan line connected to each other, and the detour portions of the emission control lines connected to each other may be sequentially arranged between the detour portions of adjacent data lines in a radial direction from the center of the opening area OA.

[0186] In an embodiment, if Fig.16 As shown in , the (N-1)th scan line and the N-th previous scan line may be connected to each other, and the (N-1)th emission control line and the N-th emission control line may be connected to each other. In an embodiment, the (N-1)th scan line and the N-th previous scan line may be connected to each other, and the (N-1)th emission control line and the N-th emission control line may not be connected to each other. In another embodiment, the (N-1)th emission control line and the N-th emission control line may be connected to each other, and the (N-1)th scan line and the N-th previous scan line may not be connected to each other.

[0187] In an embodiment, it may include a reference Fig.12 The ring-shaped connecting electrode HL-R described (see Fig.12 ), or both include a detour portion HL-C having an arc shape (see Fig.13 ) of the electrode voltage lines HL1, HL2, HL3, HL4, HL5 and HL6 can be set to Fig.16 , and as referenced Fig.14 As described, the electrode voltage lines HL1, HL2, HL3, HL4, HL5, and HL6 may be provided to be spaced apart from each other with the opening area OA therebetween.

[0188] Fig.18 A plan view showing a portion of a display panel 10 according to another embodiment is shown.

[0189] Reference Fig.18 , as referenced Fig.16 As described above, the first scan line SWL1 and the second previous scan line SIL2 may be connected to each other, so that a detour line (detour portion) may pass through the first non-display area NDA1, and the first emission control line EL1 and the second emission control line EL2 may be connected to each other, so that a detour line (detour portion) may pass through the first non-display area NDA1. In an embodiment, in addition to the first scan line SWL1, the second previous scan line SIL2, the first emission control line EL1 and the second emission control line EL2, the display panel 10 may further include a display panel having the same configuration as described above with reference to FIG. Fig.16 The structure of the display panel 10 is described in detail in the same way as the structure of the line.

[0190] Two or more initialization voltage lines arranged on the left side of the first non-display area NDA1 may be connected to each other. Fig.18 As shown in , the first initialization voltage line VL1 that transmits the initialization voltage to the pixels P on the first row and the second initialization voltage line VL2 that transmits the initialization voltage to the pixels P on the second row may be connected to a bar-type or linear-type electrode layer VL-CL. The electrode layer VL-CL may be arranged on a layer different from the layer on which the first initialization voltage line VL1 and the second initialization voltage line VL2 are arranged. For example, the electrode layer VL-CL arranged on the same layer as the layer on which the data line is arranged may be connected to the first initialization voltage line VL1 and the second initialization voltage line VL2 arranged thereunder through the third contact hole CNT3. In an embodiment, two or more initialization voltage lines arranged on the right side of the first non-display area NDA1 may also be electrically connected to each other through the electrode layer located on the right side of the opening area OA.

[0191] As a way of increasing various functions that can be combined or associated with a display device, one or more embodiments may provide a display panel including an opening area and an apparatus including the display panel, wherein a camera, a sensor, etc. inside the display area may be arranged in the opening area.

[0192] Embodiments may help prevent interference between lines (wiring) around an opening area (eg, coupling between adjacent data lines in a display device including an opening area (or opening)) and reduce the area of ​​non-display area occupied by lines around the opening area.

[0193] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be construed in a general and descriptive sense only, and not for purposes of limitation. In some cases, unless otherwise specifically noted, it will be clear to one of ordinary skill in the art that, as of the time of filing this application, the features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display panel, comprising: A substrate, comprising a display area surrounding an opening area and a non-display area between the opening area and the display area; A plurality of display elements are located in the display area; a plurality of scanning lines extending in a first direction and arranged around the edge of the opening area; a plurality of data lines extending in a second direction intersecting the first direction, the plurality of data lines being arranged around the edge of the opening area; and a plurality of emission control lines extending in the first direction and detouring around the edge of the opening area and including a detouring portion located in the non-display area, Wherein, two adjacent emission control lines among the plurality of emission control lines share the same detour portion.

2. The display panel according to claim 1, wherein: The detour portion of a first emission control line among the plurality of emission control lines is located between detour portions of adjacent data lines among the plurality of data lines in the non-display area.

3. The display panel according to claim 2, wherein: The detour portion of a first scan line among the plurality of scan lines is located between detour portions of adjacent data lines among the plurality of data lines in the non-display area.

4. The display panel according to claim 3, wherein: The detour portion of the first scan line and the detour portion of the first emission control line are spaced apart from each other by a predetermined interval.

5. The display panel according to claim 3, further comprising: a plurality of previous scan lines extending in the first direction and arranged around the edge of the opening area, Wherein, a previous scan line among the plurality of previous scan lines is connected to the detour portion of the first scan line.

6. The display panel according to claim 2, wherein: A second emission control line adjacent to the first emission control line among the plurality of emission control lines is connected to the detour portion of the first emission control line.

7. The display panel according to claim 2, wherein: Each of the plurality of display elements is connected to a pixel circuit, the pixel circuit comprising: a switching thin film transistor connected to one scan line among the plurality of scan lines and one data line among the plurality of data lines; a driving thin film transistor electrically connected to the switching thin film transistor and through which a driving current flows in response to a data signal of the switching thin film transistor; and a control thin film transistor, electrically connected to the driving thin film transistor, Wherein, the first emission control line is electrically connected to the gate electrode of the control thin film transistor.

8. The display panel according to claim 7, wherein: The control thin film transistor includes an emission control thin film transistor connected to the drive thin film transistor and configured to transmit the drive current to the display element electrically connected to the drive thin film transistor.

9. The display panel according to claim 7, further comprising: a plurality of voltage lines extending in the second direction and providing driving voltage to the display element, The control thin film transistor includes an operation control thin film transistor, and the operation control thin film transistor connects the driving thin film transistor with the voltage line corresponding to the driving thin film transistor.

10. The display panel according to claim 2, wherein: The first emission control line includes an extending portion passing through the display area, the display panel further includes an insulating layer located between the detour portion and the extending portion of the first emission control line, and The detour portion of the first emission control line contacts the extension portion through a contact hole of the insulating layer.

11. The display panel according to claim 10, wherein: The detour portion of the first emission control line is located on the same layer as a layer on which a pixel electrode is arranged, the pixel electrode being provided for each of the plurality of display elements.

12. The display panel according to claim 10, further comprising: an upper insulating layer, located between the detour portion of the first emission control line and the plurality of data lines, Wherein, the detour portion of the first emission control line is located between the insulating layer and the upper insulating layer. 13 . The display panel of claim 1 , further comprising a plurality of initialization voltage lines spaced apart from each other around the opening area.

14. The display panel according to claim 13, wherein: The plurality of initialization voltage lines are connected to each other through an electrode layer having a ring shape and located in the non-display area.

15. The display panel according to claim 13, wherein: Initialization voltage lines located on a first side of the opening region among the plurality of initialization voltage lines are connected to each other in the non-display region through a stripe-type electrode layer.

16. A display panel, comprising: A substrate, comprising an opening area, a display area surrounding the opening area, and a non-display area between the opening area and the display area; A plurality of display elements are located in the display area, each display element comprising a pixel electrode, a counter electrode facing the pixel electrode, and an emission layer located between the pixel electrode and the counter electrode; A plurality of first lines extending in a first direction and circumferentially along an edge of the opening area; a plurality of second lines extending in a second direction intersecting the first direction and circling around the edge of the opening area; as well as a plurality of third lines extending in the first direction and circumscribing along the edge of the opening area, wherein at least one of the plurality of third lines comprises: an extension portion spaced apart from each other around the opening region; an insulating layer located on the extension portion; and a detour portion connected to the extension portion through a contact hole of the insulating layer, wherein the detour portion is located between the detour portions of adjacent second lines in the non-display area, and Wherein, two adjacent third lines among the plurality of third lines share the same detour portion.

17. The display panel according to claim 16, wherein: Each of the plurality of first lines comprises a scan line, and Each of the plurality of second lines includes a data line.

18. The display panel according to claim 17, wherein: Each of the plurality of third lines includes an emission control line.

19. The display panel according to claim 16, wherein: The detour portion includes a same material as that of the pixel electrode.

20. The display panel according to claim 16, wherein: Each of the plurality of display elements is connected to a driving thin film transistor, a storage capacitor and a voltage line, the storage capacitor includes a first storage capacitor plate and a second storage capacitor plate, the voltage line is configured to provide a voltage to the second storage capacitor plate, and The detour portion comprises the same material as the second storage capacitor plate.

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