Clock duty cycle calibration circuit and calibration method

Abstract

The embodiment of the present invention provides a clock duty cycle calibration circuit and calibration method, the circuit includes a delay chain group having at least three delay chains connected in series, the delay chain group generates a delay signal for adjusting the duty cycle of the clock signal through each delay chain according to the received clock signal; the delay accuracy of the delay signal output by the delay chain at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain at the tail end can make the duty cycle of the input clock signal reach 50%±1%; the clock generator is used to receive the input clock signal and the delay signal output by the delay chain at the tail end and send out an output clock signal; the duty cycle detector is used to detect the duty cycle of the output clock signal and adjust the length of each delay chain according to the duty cycle. The embodiment of the present invention can quickly and accurately adjust the duty cycle of the clock signal to 50%±1% at any clock signal frequency by setting multiple delay chains with different adjustment accuracy.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a clock duty cycle calibration circuit and a calibration method. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the invention recited in the claims. No admission is made that the description herein is prior art by inclusion in this section.

[0003] In the field of DRAM (Dynamic Random Access Memory), DDR (Double Data Rate SDRAM) technology triggers data reading at both the upper and lower edges of the clock, so a clock with a good duty cycle is even more important in the DRAM field. Since the working clock signal frequency of DDR4 memory chips will change within a relatively large range, for example, it may be in the range of 666.5MHz to 1600MHz, and in test mode, it may even be lower than 666.5MHz. Regardless of the frequency of the DRAM clock signal, the DRAM needs to adjust the duty cycle of its internal clock signal as quickly as possible to ensure the correctness of the entire DRAM read data.

[0004] However, the existing clock duty cycle calibration circuit has a fixed delay chain design delay accuracy. For different frequency clock signals, the size of 1% of the clock cycle in the duty cycle accuracy of 50%±1% required by the SPEC (Specification) will change with the working clock signal frequency. Therefore, when the frequency variation range is large, the overall duty cycle calibration cycle will be very long. Summary of the invention

[0005] The embodiments of the present invention provide a clock duty cycle calibration circuit and a calibration method to at least alleviate or solve one or more technical problems in the prior art.

[0006] In a first aspect, an embodiment of the present invention provides a clock duty cycle calibration circuit, comprising:

[0007] A delay chain group, comprising at least three delay chains connected in series, wherein the delay chain group generates a delay signal for adjusting the duty cycle of the input clock signal through each delay chain according to the received input clock signal; wherein the delay accuracy of the delay signal output by the delay chain at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain at the tail end can make the duty cycle of the input clock signal reach 50%±1%;

[0008] A clock generator, used for receiving an input clock signal and a delayed signal output by a delay chain at a tail end, and sending an output clock signal;

[0009] The duty cycle detector is connected to the clock generator and is used to detect the duty cycle of the output clock signal and adjust the length of each delay chain according to the duty cycle of the output clock signal.

[0010] In some embodiments, it further comprises:

[0011] A decoder, connected to the register, obtains the current clock signal frequency of the clock signal according to the encoding value in the register;

[0012] The control unit is connected between the decoder and the delay chain group, and is used to adjust the initial length of the delay chain at the head end to a length position roughly close to half the current clock signal frequency; and is also used to adjust the initial length of the remaining delay chains to an intermediate length position.

[0013] In some embodiments, the control unit is further connected to a duty cycle detector for adjusting the length of each delay chain according to a signal output by the duty cycle detector.

[0014] In some embodiments, the control unit includes multiple counters, and the number of counters corresponds to the number of delay chains; the counters are used to count the current length of the corresponding delay chain and adjust the length of the corresponding delay chain according to the signal output by the duty cycle detector.

[0015] In some embodiments, the signal output by the duty cycle detector includes an increase signal and a decrease signal;

[0016] When the counter receives an increase signal, the length of the delay chain is increased; when the counter receives a decrease signal, the length of the delay chain is decreased.

[0017] In some implementations, the clock signal frequency includes a frequency between 1600 MHz and 666.5 MHz.

[0018] In some embodiments, the delay chain group includes three delay chains connected in series, the delay chain at the head end is used to adjust the delay signal to a first precision, the delay chain at the middle is used to adjust the delay signal adjusted to the first precision to a second precision, and the delay chain at the tail end is used to adjust the delay signal adjusted to the second precision to a third precision.

[0019] In some embodiments, the adjustment range of the delay chain at the head end is 200ps-3200ps, and the first precision is 187.5ps; the adjustment range of the delay chain at the middle is 0ps-200ps, and the second precision is 12.5ps; the adjustment range of the delay chain at the tail end is 0ps-16ps, and the third precision is 1ps.

[0020] In a second aspect, an embodiment of the present invention provides a calibration method for a clock duty cycle calibration circuit, comprising:

[0021] Input the input clock signal into the delay chain group, and generate a delay signal for adjusting the duty cycle of the clock signal through each series-connected delay chain in the delay chain group; wherein the delay accuracy of the delay signal output by the delay chain at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain at the tail end can make the duty cycle of the input clock signal reach 50%±1%;

[0022] Input the clock signal and the delayed signal output by the delay chain at the tail end into the clock generator, and send out the output clock signal through the clock generator;

[0023] The output clock signal is input into the duty cycle detector so that the duty cycle detector adjusts the length of each delay chain according to the duty cycle of the output clock signal.

[0024] In some embodiments, it further comprises:

[0025] Obtain the encoded value in the register read by the decoder to obtain the current clock signal frequency of the clock signal;

[0026] According to the current clock signal frequency, the control unit adjusts the initial length of the delay chain at the head end to a length roughly close to half the current clock signal frequency; and is also used to adjust the initial lengths of the remaining delay chains to an intermediate length.

[0027] In some implementations, according to the signal output by the duty cycle detector, each counter of the control unit adjusts and records the length of the corresponding delay chain.

[0028] In a third aspect, an embodiment of the present invention provides a semiconductor memory, comprising a clock duty cycle calibration circuit as described in the first aspect.

[0029] The embodiment of the present invention adopts the above technical solution, which has the following advantages: by adjusting the delay lengths of multiple delay chains with different precisions, it is possible to quickly and accurately calibrate the duty cycle of the input clock signal at any clock signal frequency, thereby ensuring that the duty cycle of the final output clock signal is 50%±1%.

[0030] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present invention and should not be regarded as limiting the scope of the present invention.

[0032] Figure 1 FIG. 4 is a schematic diagram of a clock duty cycle calibration circuit according to an embodiment of the present invention.

[0033] Figure 2 The figure is a flow chart of a calibration method of a clock duty cycle calibration circuit according to an embodiment of the present invention.

[0034] Figure 3 The figure is a flow chart of a calibration method of a clock duty cycle calibration circuit according to another embodiment of the present invention.

[0035] Reference numerals:

[0036] 100-delay chain group; 101-delay chain; 200-clock generator;

[0037] 300-duty cycle detector; 400-decoder; 500-register;

[0038] 600-control unit; 601-counter. DETAILED DESCRIPTION

[0039] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0040] The embodiment of the present invention provides a clock duty cycle calibration circuit, such as Figure 1 As shown, including:

[0041] The delay chain group 100 includes at least three delay chains 101 connected in series. The delay chain group 100 generates a delay signal for adjusting the duty cycle of the clock signal through each delay chain 101. Among them, the delay chain 101 located at the head end receives the input clock signal, and the delay chain 101 located at the tail end outputs the final delayed clock signal. The latter delay chain 101 is used to re-adjust the accuracy of the delay signal output by the previous delay chain. Among them, the adjustment accuracy of each delay chain 101 is different. The delay accuracy of the delay signal output by the delay chain 101 at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain 101 at the tail end can make the duty cycle of the input clock signal reach 50%±1%. Because the memory chip switches the clock signal frequency during operation. For example, the DDR chip can operate at a frequency of 1600MHz or at a frequency of 666.5MHz. Therefore, if the memory chip switches the working clock signal frequency, it is necessary to quickly and accurately adjust the length of each delay chain 101 according to the working clock signal frequency of the current clock signal to ensure that the circuit can work normally.

[0042] The clock generator 200 is connected to the delay chain 101 at the tail end. The clock generator 200 is used to receive the delay signal output by the delay chain 101 at the tail end and the input clock signal, and send out an output clock signal.

[0043] The duty cycle detector 300 is arranged between the control unit 600 and the clock generator 200. The duty cycle detector 300 is used to adjust the length of each delay chain 101 according to the output clock signal. The duty cycle detector 300 adjusts the length of each delay chain 101 in three ways: increase, decrease or maintain. The length of the delay chain 101 increases during the increase operation, and the length of the delay chain 101 decreases during the decrease operation.

[0044] In one embodiment, the accuracy of each delay chain 101 is improved from the head end to the tail end, so that when the clock signal frequency of the chip changes arbitrarily, the duty cycle of the clock can still be calibrated quickly and accurately through multiple delay chains 101 in series, ensuring that the duty cycle of the final output clock signal is 50%±1%.

[0045] In one embodiment, if Figure 1 As shown, it also includes:

[0046] The decoder 400 is used to connect the register 500 to obtain the current clock signal frequency of the clock signal according to the code value in the register 500. The register 500 needs to set different tCCD_L (low frequency cycle number) and tCWL (high frequency cycle number) under different clock signal frequencies. The parameters (code values) of tCCD_L and tCWL mainly reflect the current working clock signal frequency of the memory chip, and can include all working clock signal frequencies of the memory chip, that is, the frequency range under the wide band.

[0047] The control unit 600 is connected between the decoder 400 and the delay chain group 100. The control unit 600 is used to adjust the initial length of the delay chain 101 at the head end to a length position roughly close to half the current clock signal frequency. It is also used to adjust the initial length of the remaining delay chains 101 to an intermediate length position (i.e., half the length of the delay chain). In order to achieve rapid adjustment of the length of the delay chain 101, after obtaining the clock signal frequency (T), the initial length of the delay chain 101 is first adjusted to a position corresponding to half the clock signal frequency (T / 2) or half the length of the delay chain 101 itself, so that the delay chain 101 can be adjusted more quickly in a shorter time according to the signal output by the duty cycle detector 300.

[0048] In an application example, since the clock signal frequency of the DDR chip can reach up to 1600MHz, but may also be lower than 666.5MHz, when the clock signal frequency becomes lower, the delay chain accuracy of the high-frequency circuit needs to be appropriately adjusted. When the clock signal frequency changes from 1600MHz to lower than 666.5MHz, generally in test mode, the clock signal frequency at this time may be only 200MHz. Taking this as an example, when the delay time of the delay unit is 6.25ps, the clock cycle changes from 625ps to greater than or equal to 5ns. The longer cycle means that the number of delay units in a delay chain must be increased from the original 50 to at least 400. At this time, the delay chain connected to the circuit is obviously much more than before. Therefore, knowing the approximate range of the clock signal frequency in advance and being able to select the appropriate delay chain accuracy plays an important role in improving the calibration speed.

[0049] Preferably, register 500 may adopt an MRS (Mode Register Setting) circuit. The setting of tCCD_L in the MRS circuit mainly reflects the range of the low-speed clock frequency (f≤1200MHz), while the setting of CWL in the MRS circuit mainly reflects the high-speed clock frequency (800MHz~1600MHz). The output signals of the encoding circuits of the two are integrated and connected to the clock duty cycle calibration circuit of the embodiment of the present invention, so that the duty cycle calibration circuit can still work normally when the chip clock is at any frequency that meets the SPEC requirements, thereby ensuring that the duty cycle of the final output clock signal is 50%±1%.

[0050] In DRAM, the data of tCCD_L can directly reflect the low-frequency range of the chip (as shown in Table 1), which enables timely information to be obtained at the beginning of frequency conversion, so as to adjust the length of the delay chain and the capacitor in the duty cycle detection circuit to ensure that the duty cycle of the detection result is 50% ± 1%. The data of CWL (CAS Write Latency) can directly reflect the high-frequency range of the chip, which enables timely information to be obtained at the beginning of frequency conversion, so as to adjust the length of the delay chain and the capacitor in the duty cycle detection circuit to ensure that the duty cycle of the detection result is 50% ± 1%. Through tCCD_L and CWL, the approximate range of the frequency change of the clock signal can be predicted in advance. As long as the appropriate delay chain length is adjusted for different frequency ranges, the calibration time of the clock duty cycle can be reduced.

[0051] Table 1

[0052]

[0053]

[0054] For example: In the Mode Register Setting of DDR4JEDEC SPEC, MR6 has the setting of tCCD_L under different clock signal frequencies (for example, f≤1200MHz) to be set to the number of cycles that meet the spec requirements. Therefore, the clock signal frequency range of the current chip can be obtained from the setting code of different tCCD_L, which can accelerate the calibration quality of DCC from two aspects: 1. Setting an initial adjustment value close to T / 2 for the delay chain 101 can reduce the calibration time. 2. Determine the minimum charge required to identify the clock duty cycle in the duty cycle detector 300, thereby determining the number of variable capacitors connected to the circuit, thereby improving the accuracy of the duty cycle detection circuit.

[0055] In one embodiment, the control unit 600 is further connected to the duty cycle detector 300 , and is configured to adjust the length of each delay chain 101 according to a signal output by the duty cycle detector 300 .

[0056] In one embodiment, the control unit 600 includes a plurality of counters 601, and the number of the counters 601 corresponds to the number of the delay chains 101. The counters 601 are used to count the current length of the corresponding delay chain 101, and adjust the length of the corresponding delay chain 101 according to the signal output by the duty cycle detector 300.

[0057] In one specific embodiment, the signal output by the duty cycle detector 300 includes an increase signal and a decrease signal;

[0058] When the counter 601 receives an increase signal, the length of the corresponding delay chain 101 is increased. When the counter 601 receives a decrease signal, the length of the corresponding delay chain 101 is decreased.

[0059] In a variable embodiment, the counter 601 has two input terminals, which are respectively connected to the two output terminals of the duty cycle detector 300, and are respectively used to receive an increase signal and a decrease signal, so as to adjust the length of the delay chain 101 through the two input terminals. Each counter 601 is also connected to the decoder 400, and is used to adjust the initial length of the corresponding delay chain 101 according to the code value of the register 500 obtained by the decoder 400.

[0060] In one embodiment, the clock signal frequency includes frequencies between 1600 MHz and 666.5 MHz.

[0061] In one embodiment, the delay chain group 100 includes three delay chains 101 connected in series, the delay chain 101 at the head end is used to adjust the delay signal to a first precision, the delay chain 101 at the middle end is used to adjust the delay signal adjusted to the first precision to a second precision, and the delay chain 101 at the tail end is used to adjust the delay signal adjusted to the second precision to a third precision. Preferably, the first precision is at least 187.5ps, the second precision is at least 12.5ps, and the third precision is at least 1ps.

[0062] In an application example, the duty cycle detector 300 receives the output clock signal of the clock generator 200. If the accuracy of the duty cycle of the detected output clock signal does not meet 50%±1%, each counter 601 is controlled to adjust the length of each delay chain 101 in the delay chain group 100, thereby adjusting the delay signal, and adjusting the duty cycle of the input clock signal again through the delay signal, until the duty cycle detector 300 detects that the accuracy of the duty cycle of the output clock signal meets 50%±1%, and then outputs the output clock signal as the final calibrated clock signal.

[0063] In an application example, the first delay chain 101 is a low-frequency delay chain, and the delay length adjustment range corresponding to the low-frequency delay chain is 200-3200ps, and the adjustment accuracy is 187.5ps. The second delay chain 101 is an intermediate frequency delay chain, and the delay length adjustment range corresponding to the intermediate frequency delay chain is 0-200ps, and the adjustment accuracy is 12.5ps. The third delay chain 101 is a high-frequency delay chain, and the delay length adjustment range corresponding to the high-frequency delay chain is 0-16ps, and the adjustment accuracy is 1ps. Among them, the first delay chain 101 is used to adjust the duty cycle to approximately 50%, and the second delay chain 101 and the third delay chain 101 are used to further adjust the duty cycle to 50%±1%. Depending on the adjustment accuracy, the duty cycle can be adjusted to 50%±1% only by the second delay chain 101, or the duty cycle can be adjusted to 50%±1% by the second delay chain 101 and the third delay chain 101 together.

[0064] According to the different clock signal frequencies of the memory chip, the number of delay chains 101 used can be selected by using the adjustment accuracy shown in Table 2.

[0065] Table 2

[0066]

[0067]

[0068] For example, when the clock signal frequency read by the decoder 400 from the register 500 is 5000ps, 50% of the clock signal frequency is 2500ps, corresponding to the adjustment range of the first delay chain 101, so the duty cycle is adjusted to roughly close to 50% through the first delay chain 101. 1% of the clock signal frequency is 50ps, corresponding to the adjustment range of the second delay chain 101, so the duty cycle is further adjusted to 50%±1% through the second delay chain 101, thereby achieving the accuracy of the delay signal adjusted to 12.5ps using the first delay chain 101 and the second delay chain 101. That is, the duty cycle of the calibrated clock signal is adjusted to 50%±1%, and the accuracy of the duty cycle detector is adjusted to 12.5ps.

[0069] When the clock signal frequency read by the decoder 400 from the register 500 is 625ps, 50% of the clock signal frequency is 312.5ps, corresponding to the adjustment range of the first delay chain 101, so the duty cycle is adjusted to roughly close to 50% through the first delay chain 101. 1% of the clock signal frequency is 6.25ps, corresponding to the adjustment range of the second delay chain 101 and the third delay chain 101, so the duty cycle is further adjusted to 50%±1% through the second delay chain 101 and the third delay chain 101, so that the accuracy of the delay signal is adjusted to 1ps using the first delay chain 101, the second delay chain 101 and the third delay chain 101. That is, the duty cycle of the calibrated clock signal is adjusted to 50%±1%, and the accuracy of the duty cycle detector is adjusted to 1ps.

[0070] In an application example, register 500 sends 6-bit data related to the clock signal frequency to decoder 400. Decoder 400 processes the data and obtains 4-bit data which are sent to each counter 601 respectively, so that each counter 601 can adjust its corresponding delay chain 101. Delay chain 101 adjusts its own delay chain length according to the obtained 4-bit data.

[0071] The embodiment of the present invention provides a calibration method for a clock duty cycle calibration circuit, such as Figure 2 As shown, including:

[0072] S100: Input the input clock signal into the delay chain group, and generate a delay signal for adjusting the duty cycle of the clock signal through each series-connected delay chain in the delay chain group; wherein, the delay accuracy of the delay signal output by the delay chain at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain at the tail end can make the duty cycle of the input clock signal reach 50%±1%.

[0073] S200: Input the clock signal and the delayed signal output by the delay chain at the tail end into the clock generator, and send out an output clock signal through the clock generator.

[0074] S300: Input the output clock signal into the duty cycle detector, so that the duty cycle detector adjusts the length of each delay chain according to the duty cycle of the output clock signal.

[0075] In one embodiment, if Figure 3 As shown, it also includes:

[0076] S400: Obtain the code value in the register read by the decoder to obtain the current clock signal frequency.

[0077] S500: According to the current clock signal frequency, the control unit adjusts the initial length of the delay chain at the head end to a length position roughly close to half the current clock signal frequency; and is also used to adjust the initial lengths of the remaining delay chains to an intermediate length position.

[0078] In one embodiment, if Figure 3 As shown, it also includes:

[0079] S600: According to the signal output by the duty cycle detector, each counter of the control unit adjusts and records the length of the corresponding delay chain.

[0080] An embodiment of the present invention provides a semiconductor memory, comprising the clock duty cycle calibration circuit as described in the first aspect above.

[0081] The embodiments of the present invention have the following advantages: 1. As the clock signal frequency of the chip changes, the important delay chain in the clock duty cycle detection circuit is adjusted accordingly in real time, thereby improving the calibration result and ensuring that the final clock signal quality is in good compliance with the DRAM SPEC design requirements. 2. The reliability and accuracy of the clock duty cycle detection circuit are improved. 3. By setting multiple delay chains with different adjustment precisions, the clock duty cycle can be calibrated quickly and accurately at any clock signal frequency, ensuring that the duty cycle of the final output clock signal is 50%±1%.

[0082] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0083] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0084] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0085] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0086] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0087] The disclosure above provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described above. Of course, they are merely examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art may appreciate the application of other processes and / or the use of other materials.

Claims

1. A clock duty cycle calibration circuit, characterized in that: include: A delay chain group, comprising at least three delay chains connected in series, wherein the delay chain group generates a delay signal for adjusting the duty cycle of the input clock signal through each delay chain according to the received input clock signal; wherein the delay accuracy of the delay signal output by the delay chain at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain at the tail end can make the duty cycle of the input clock signal reach 50%±1%; A clock generator, used for receiving the input clock signal and the delayed signal output by the delay chain at the tail end, and sending out an output clock signal; A duty cycle detector, connected to the clock generator, for detecting the duty cycle of the output clock signal and adjusting the length of each delay chain according to the duty cycle of the output clock signal; A decoder, connected to the register, wherein the decoder obtains the current clock signal frequency of the clock signal according to the encoding value in the register; A control unit is connected between the decoder and the delay chain group, and is used to adjust the initial length of the delay chain at the head end to a length position roughly close to half the current clock signal frequency; and is also used to adjust the initial length of the remaining delay chains to an intermediate length position.

2. The clock duty cycle calibration circuit according to claim 1, characterized in that: The control unit is also connected to the duty cycle detector and is used to adjust the length of each delay chain according to a signal output by the duty cycle detector.

3. The clock duty cycle calibration circuit according to claim 2, characterized in that: The control unit includes a plurality of counters, the number of the counters corresponding to the number of the delay chains; the counters are used to count the current length of the corresponding delay chain and adjust the length of the corresponding delay chain according to the signal output by the duty cycle detector.

4. The clock duty cycle calibration circuit according to claim 3, characterized in that: The signal output by the duty cycle detector includes an increase signal and a decrease signal; When the counter receives the increase signal, the length of the delay chain is increased; when the counter receives the decrease signal, the length of the delay chain is decreased.

5. The clock duty cycle calibration circuit according to claim 1, wherein: The clock signal frequency includes a frequency between 1600 MHz and 666.5 MHz.

6. The clock duty cycle calibration circuit according to claim 1, characterized in that: The delay chain group includes three delay chains connected in series, the delay chain located at the head end is used to adjust the delay signal to a first precision, the delay chain located in the middle is used to adjust the delay signal adjusted to the first precision to a second precision, and the delay chain located at the tail end is used to adjust the delay signal adjusted to the second precision to a third precision.

7. The clock duty cycle calibration circuit according to claim 6, characterized in that: The adjustment range of the delay chain at the head end is 200ps-3200ps, and the first precision is 187.5ps; the adjustment range of the delay chain in the middle is 0ps-200ps, and the second precision is 12.5ps; the adjustment range of the delay chain at the tail end is 0ps-16ps, and the third precision is 1ps.

8. A calibration method for a clock duty cycle calibration circuit, characterized in that: include: Inputting an input clock signal into a delay chain group, and generating a delay signal for adjusting the duty cycle of the clock signal through each series-connected delay chain in the delay chain group; wherein the delay accuracy of the delay signal output by the delay chain at the head end can make the duty cycle of the input clock signal roughly close to 50%, and the delay accuracy of the delay signal output by the delay chain at the tail end can make the duty cycle of the input clock signal reach 50%±1%; Input the clock signal and the delayed signal output by the delay chain at the tail end into a clock generator, and send out an output clock signal through the clock generator; Inputting the output clock signal into a duty cycle detector so that the duty cycle detector adjusts the length of each delay chain according to the duty cycle of the output clock signal; Also includes: Obtaining the encoding value in the register read by the decoder to obtain the current clock signal frequency of the clock signal; According to the current clock signal frequency, the control unit adjusts the initial length of the delay chain at the head end to a length roughly close to half the current clock signal frequency; and is also used to adjust the initial length of the remaining delay chains to an intermediate length.

9. The calibration method of the clock duty cycle calibration circuit according to claim 8, characterized in that: According to the signal output by the duty cycle detector, each counter of the control unit adjusts and records the length of the corresponding delay chain.

10. A semiconductor memory, characterized in that: The method comprises a clock duty cycle calibration circuit as claimed in any one of claims 1 to 7.

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