Display device and inspection method thereof

Abstract

A display device and an inspection method thereof are provided. The display device includes: sub-pixels arranged in a display area and arranged along the first to eighth columns; first to fourth wiring pads arranged in a non-display area and arranged on one side of the display area, wherein the non-display area is a peripheral area of ​​the display area; a crack sensing line arranged in the non-display area; first to fourth fan-out lines connecting the sub-pixels arranged along the first to eighth columns and the first to fourth wiring pads; and an inspection unit arranged between the first to fourth wiring pads and the display area and electrically connected to the crack sensing line and the first to fourth fan-out lines, the inspection unit being configured to apply a test voltage to the first to fourth fan-out lines to inspect short circuits and disconnections of the first to fourth fan-out lines, and to apply a test voltage to the crack sensing line to inspect damage to the crack sensing line.

Description

Technical Field

[0001] The present disclosure relates to a display device and an inspection method thereof. Background Art

[0002] With the development of the information society, the requirements for display devices for displaying images are increasing in various forms. For example, display devices are suitable for various electronic devices such as smart phones, digital cameras, laptops, navigators, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device (Liquid Crystal Display Device), a field emission display device (Field Emission Display Device), a light emitting display device (Light Emitting Display Device), etc. In such a flat panel display device, the light emitting display device includes a light emitting element in which each pixel of the display panel can emit light by itself, so that an image can be displayed without a backlight unit that provides light to the display panel.

[0003] The light-emitting display device may include a plurality of pixels, each of which may include: a light-emitting element; a driving transistor for adjusting the amount of driving current supplied to the light-emitting element according to the voltage of the gate electrode; and a scanning transistor for supplying a data voltage of a data line to the gate electrode of the driving transistor in response to a scanning signal of the scanning line. Such a display device requires lighting inspection, crack inspection, and spider wiring inspection for transmitting the output of the driver IC. Summary of the invention

[0004] The problem to be solved by the present disclosure is to provide a display device capable of performing lighting inspection, crack inspection, and spider-web wiring inspection, and an inspection method thereof.

[0005] The subject of the present disclosure is not limited to the subject mentioned above, and those skilled in the art can clearly understand other technical subjects not mentioned through the following description.

[0006] A display device of an embodiment for solving the above-mentioned problem comprises: sub-pixels arranged in a display area and arranged along a first column, a second column, a third column, a fourth column, a fifth column, a sixth column, a seventh column and an eighth column; a first wiring pad, a second wiring pad, a third wiring pad and a fourth wiring pad arranged in a non-display area and arranged on one side of the display area, wherein the non-display area is a peripheral area of ​​the display area; a crack sensing line arranged in the non-display area; a first fan-out line, a second fan-out line, a third fan-out line and a fourth fan-out line connected along the first fan-out line; The sub-pixels arranged in the 1st to 8th columns and the 1st to 4th wiring pads; and an inspection unit, which is arranged between the 1st to 4th wiring pads and the display area and is electrically connected to the crack sensing line and the 1st to 4th fan-out lines, the inspection unit being configured to apply a test voltage to the 1st to 4th fan-out lines to inspect short circuits and broken wires from the 1st to 4th fan-out lines, and to apply a test voltage to the crack sensing line to inspect damage to the crack sensing line.

[0007] The first fan-out line and the third fan-out line may be arranged in the same layer, the second fan-out line and the fourth fan-out line may be arranged in the same layer, and the first fan-out line and the third fan-out line and the second fan-out line and the fourth fan-out line may be arranged in different layers.

[0008] The inspection unit may include: a first switch, a second switch, a third switch and a fourth switch; a first control line, supplying a first inspection control signal to respective gates of the first switch and the second switch; a second control line, supplying a second inspection control signal to respective gates of the third switch and the fourth switch; and a data voltage line, supplying a test voltage to respective first terminals of the first switch to the fourth switch.

[0009] The second terminal of the first switch may be connected to the first fan-out line, the second terminal of the second switch may be connected to the second fan-out line, the second terminal of the third switch may be connected to the third fan-out line, and the second terminal of the fourth switch may be connected to the fourth fan-out line.

[0010] It may be that the display device further includes: a first data line connected to the sub-pixels arranged along the first column; a second data line connected to the sub-pixels arranged along the second column; a third data line connected to the sub-pixels arranged along the third column; a fourth data line connected to the sub-pixels arranged along the fourth column; a fifth data line connected to the sub-pixels arranged along the fifth column; a sixth data line connected to the sub-pixels arranged along the sixth column; a seventh data line connected to the sub-pixels arranged along the seventh column; and an eighth data line connected to the sub-pixels arranged along the eighth column. The display device further comprises: a demultiplexing section, which is arranged in the non-display area and located between the display area and the inspection section, the first data line and the second data line are connected to the first fan-out line through the demultiplexing section, the third data line and the fourth data line are connected to the second fan-out line through the demultiplexing section, the fifth data line and the sixth data line are connected to the third fan-out line through the demultiplexing section, and the seventh data line and the eighth data line are connected to the fourth fan-out line through the demultiplexing section.

[0011] It may be that the demultiplexing unit includes: a 5th switch, a 6th switch, a 7th switch, an 8th switch, a 9th switch, a 10th switch, an 11th switch and a 12th switch; a 3rd control line, supplying a 1st demultiplexing control signal to respective gates of the 5th switch, the 7th switch, the 9th switch and the 11th switch; and a 4th control line, supplying a 2nd demultiplexing control signal to respective gates of the 6th switch, the 8th switch, the 10th switch and the 12th switch.

[0012] It may be that the first terminals of the fifth switch and the sixth switch are connected to the first fan-out line, the first terminals of the seventh switch and the eighth switch are connected to the second fan-out line, the first terminals of the ninth switch and the tenth switch are connected to the third fan-out line, and the first terminals of the eleventh switch and the twelfth switch are connected to the fourth fan-out line.

[0013] It may be that the second terminal of the fifth switch is connected to the first data line, the second terminal of the sixth switch is connected to the second data line, the second terminal of the seventh switch is connected to the third data line, the second terminal of the eighth switch is connected to the fourth data line, the second terminal of the ninth switch is connected to the fifth data line, the second terminal of the tenth switch is connected to the sixth data line, the second terminal of the eleventh switch is connected to the seventh data line, and the second terminal of the twelfth switch is connected to the eighth data line.

[0014] The display device may further include a lighting circuit unit disposed between the display area and the demultiplexing unit.

[0015] The lighting circuit unit may further include a lighting inspection signal line that supplies a white data voltage to the second data line, the fourth data line, the sixth data line, and the eighth data line.

[0016] It may be that the test voltage is a black data voltage.

[0017] It may be that the sub-pixels include: red sub-pixels and blue sub-pixels, which are alternately arranged in the first column, the third column, the fifth column and the seventh column; and green sub-pixels, which are arranged in the second column between the first column and the third column, the fourth column between the third column and the fifth column, the sixth column between the fifth column and the seventh column, and the eighth column arranged outside the seventh column, and in the third column and the seventh column, the red sub-pixels and the blue sub-pixels are alternately arranged in the opposite order to the first column and the fifth column.

[0018] The first to fourth switches may be formed of transistors, the gate may be a gate electrode, the first terminal may be a drain electrode, and the second terminal may be a source electrode.

[0019] A display device according to another embodiment for solving the above-mentioned problem includes: a sub-pixel arranged in a display area; a display driving circuit arranged in a non-display area and located at the lower side of the display area, wherein the non-display area is a peripheral area of ​​the display area; a crack sensing line arranged in the non-display area; a fan-out line connecting the sub-pixel and the display driving circuit; and an inspection unit arranged between the display area and the display driving circuit and adjacent to the display driving circuit and electrically connected to the crack sensing line and the fan-out line, wherein the inspection unit is configured to apply a test voltage to the fan-out line to inspect the short circuit and the break of the fan-out line, and to apply a test voltage to the crack sensing line to inspect the damage of the crack sensing line.

[0020] The display device may further include: a wiring pad electrically connected to the fan-out line; the display driving circuit includes a bump and a driving integrated circuit; and the driving integrated circuit is connected to the wiring pad via the bump.

[0021] Alternatively, the display device further includes: a display pad, which is arranged outside the display driving circuit and is attached with a circuit board.

[0022] The display device may further include: a lighting circuit unit, which is arranged between the display area and the inspection unit and is disposed adjacent to the display area.

[0023] It may be that the display device further includes: a first data line, a second data line, a third data line and a fourth data line, which are connected to the sub-pixels, and the fan-out lines include a first fan-out line, a second fan-out line, a third fan-out line and a fourth fan-out line, the first data line is connected to the first fan-out line, the second data line is connected to the second fan-out line, the third data line is connected to the third fan-out line, and the fourth data line is connected to the fourth fan-out line.

[0024] The sub-pixels may be arranged along a plurality of columns in a stripe form, with sub-pixels of the same color being arranged in the same column.

[0025] An inspection method for a display device of one embodiment for solving the above-mentioned problem is as follows: the display device comprises: a sub-pixel arranged in a display area; a display driving circuit arranged in a non-display area and located at the lower side of the display area, wherein the non-display area is a peripheral area of ​​the display area; a crack sensing line arranged in the non-display area; a fan-out line connecting the sub-pixel and the display driving circuit; and an inspection unit arranged between the display area and the display driving circuit and adjacent to the display driving circuit and electrically connected to the crack sensing line and the fan-out line, wherein the inspection unit comprises: a step of applying a test voltage to the fan-out line to inspect the short circuit and disconnection of the fan-out line; and a step of applying a test voltage to the crack sensing line to inspect the damage of the crack sensing line.

[0026] Details of other embodiments are included in the detailed description and drawings.

[0027] Public Effect

[0028] According to the display device and the inspection method thereof of the embodiment, crack inspection and spider-web wiring inspection can be realized by one inspection unit, thereby removing the circuit unit for spider-web wiring inspection and reducing the dead space.

[0029] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a display device according to an embodiment.

[0031] Figure 2 is a top view showing a display device according to an embodiment.

[0032] Figure 3 is a block diagram showing a display device according to an embodiment.

[0033] Figure 4is a circuit diagram illustrating a sub-pixel according to an embodiment in detail.

[0034] Figure 5 It is shown that the Figure 4 Waveform diagram of signals of the k-1th scan line, the kth scan line, the k+1th scan line and the kth light emitting line.

[0035] Figures 6 to 9 It is used to illustrate Figure 5 A circuit diagram of a driving method of the first sub-pixel in the first period to the fourth period.

[0036] Fig.10 is a diagram showing a circuit structure of a display device according to an embodiment.

[0037] Fig.11 as well as Fig.12 is a timing diagram for explaining a fan-out line inspection in a display device according to an embodiment.

[0038] Fig.13 is a timing chart for explaining crack inspection in a display device according to an embodiment.

[0039] Fig.14 is a diagram showing a circuit structure of a display device according to another embodiment.

[0040] Fig.15 as well as Fig.16 is a timing diagram for explaining a fan-out line inspection in a display device according to another embodiment.

[0041] Fig.17 is a timing chart for explaining crack inspection in a display device according to another embodiment.

[0042] Fig.18 is a diagram showing a circuit structure of a display device according to another embodiment.

[0043] Fig.19 as well as Fig. 20 is a timing diagram for explaining a fan-out line inspection in a display device according to another embodiment.

[0044] Fig.21 is a timing chart for explaining crack inspection in a display device according to another embodiment.

[0045] Fig. 22 is a diagram showing a circuit structure of a display device according to another embodiment.

[0046] Fig.23 as well as Fig.24 is a timing diagram for explaining a fan-out line inspection in a display device according to another embodiment.

[0047] Fig.25 is a timing chart for explaining crack inspection in a display device according to another embodiment.

[0048] Fig.26 is a diagram showing a circuit structure of a display device according to another embodiment.

[0049] Fig. 27 as well as Fig.28 is a timing diagram for explaining a fan-out line inspection in a display device according to another embodiment.

[0050] Fig.29 is a timing chart for explaining crack inspection in a display device according to another embodiment.

[0051] Fig.30 is a diagram showing a circuit structure of a display device according to another embodiment.

[0052] Fig.31 as well as Fig.32 is a timing diagram for explaining a fan-out line inspection in a display device according to another embodiment.

[0053] Fig.33 is a timing chart for explaining crack inspection in a display device according to another embodiment.

[0054] Description of Reference Numerals

[0055] 150: Inspection unit 151: First control line

[0056] 153: second control line 155: data voltage line

[0057] 160: Demultiplexing unit 161: Third control line

[0058] 163: 4th control line 170: lighting circuit part

[0059] 171: 5th control line 173: 6th control line

[0060] 175: 7th control line 177: 1st lighting check signal line

[0061] 178: 2nd lighting check signal line 179: 3rd lighting check signal line

[0062] DP1: 1st wiring pad DP2: 2nd wiring pad

[0063] DP3: 3rd wiring pad DP4: 4th wiring pad

[0064] FOL1: 1st fan-out line FOL2: 2nd fan-out line

[0065] FOL3: 3rd fan-out line FOL4: 4th fan-out line DETAILED DESCRIPTION

[0066] Reference and attachment Figure 1 The advantages and features of the present disclosure and the methods for realizing them will become clear from the embodiments described below. However, the present disclosure is not limited to the embodiments disclosed below, and can be implemented in various forms different from each other. The embodiments are provided only to make the disclosure of the present disclosure complete and to fully convey the scope of the disclosure to people with common knowledge in the technical field to which the present disclosure belongs. The present disclosure is limited only by the scope of the claims.

[0067] Reference to an element or layer being "on" another element or layer includes all situations where the element is directly on top of the other element or has another layer or other element in between. Throughout the specification, the same reference numerals refer to the same constituent elements. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings used to illustrate the embodiments are exemplary, and thus the present disclosure is not limited to the matters illustrated.

[0068] The first, second, etc. are used to describe various constituent elements, but it is obvious that these constituent elements are not limited to these terms. These terms are used only to distinguish one constituent element from other constituent elements. Therefore, it is obvious that the first constituent element mentioned below can also be the second constituent element within the technical concept of the present disclosure.

[0069] The various features of the many embodiments of the present disclosure may be combined or combined with each other in part or as a whole, may be technically linked and driven in various ways, and the various embodiments may be implemented independently of each other or together in an associated relationship.

[0070] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0071] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 is a top view showing a display device according to an embodiment. Figure 3 is a block diagram showing a display device according to an embodiment.

[0072] In this specification, "upper", "top", and "top surface" refer to the upper direction based on the display panel 100, that is, the Z-axis direction, and "lower", "bottom", and "bottom surface" refer to the lower direction based on the display panel 100, that is, the opposite direction of the Z-axis direction. In addition, "left", "right", "upper", and "lower" refer to directions when the display panel 100 is observed on a plane. For example, "left" refers to the opposite direction of the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Y-axis direction, and "lower" refers to the opposite direction of the Y-axis direction.

[0073] Reference Figures 1 to 3 The display device 10 is a device for displaying dynamic images or still images. It is not only a portable electronic device such as a mobile phone, a smart phone, a tablet PC (tablet personal computer), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a PMP (portable multimedia player), a navigator, an UMPC (Ultra Mobile PC), etc., but can also be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT).

[0074] The display device 10 may be an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro light emitting diode (LED)). Below, the description is centered on the case where the display device 10 is an organic light-emitting display device, but the present disclosure is not limited to this.

[0075] The display device 10 includes a display panel 100 , a display driving circuit 200 and a circuit board 300 .

[0076] The display panel 100 may be formed as a plane in the form of a rectangle having a short side in the first direction (X-axis direction) and a long side in the second direction (Y-axis direction) intersecting the first direction (X-axis direction). The corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be formed as a circle to have a predetermined curvature or as a right angle. The plane form of the display panel 100 is not limited to a quadrilateral, and may be formed as other polygons, a circle or an ellipse. The display panel 100 may be formed flat, but is not limited thereto, and may include a curved portion formed at the left and right ends and having a fixed curvature or having a variable curvature. In addition, the display panel 100 may be formed flexibly so as to be able to be bent, curved, bent, folded or curled.

[0077] The display panel 100 may include a display area DA in which sub-pixels SP are formed and images are displayed, and a peripheral area of ​​the display area DA, i.e., a non-display area NDA. In the display area DA, not only sub-pixels SP but also scan lines SL, light lines ELL, data lines DL, and first drive voltage lines VDDL connected to the sub-pixels SP may be configured. The scan lines SL and the light lines ELL may be formed side by side in a first direction (X-axis direction), and the data lines DL may be formed side by side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The first drive voltage lines VDDL may be formed side by side in the second direction (Y-axis direction) in the display area DA. The first drive voltage lines VDDL formed side by side in the second direction (Y-axis direction) in the display area DA may be connected to each other in the non-display area NDA.

[0078] Each pixel SP may be connected to at least any one of the scanning lines SL, any one of the data lines DL, at least one of the light emitting lines ELL, and the first driving voltage line VDDL. Figure 2 In the example, each sub-pixel SP is connected to two scan lines SL, one data line DL, one light emitting line ELL and the first driving voltage line VDDL, but the present invention is not limited thereto. For example, each sub-pixel SP may be connected to three scan lines SL instead of two scan lines SL.

[0079] Each sub-pixel SP may include a driving transistor, at least one transistor, a light emitting element, and a capacitor. The transistor is turned on when a scan signal is applied from the scan line SL, so that the data voltage of the data line DL can be applied to the driving transistor DT (refer to Figure 4 ) gate electrode. The driving transistor DT can supply a driving current to the light-emitting element according to the data voltage applied to the gate electrode to emit light. The driving transistor DT and at least one transistor ST can be a thin film transistor. The light-emitting element can emit light according to the driving current of the driving transistor DT. The light-emitting element can be an organic light emitting diode including a first electrode, an organic light-emitting layer and a second electrode. The capacitor can play a role in constantly maintaining the voltage applied to the driving transistor DT (refer to Figure 4 )'s gate electrode data voltage.

[0080] The non-display area NDA may be defined as a region from the outside of the display area DA to the edge of the display panel 100. A scan driving circuit for applying a scan signal to the scan line SL may be disposed in the non-display area NDA.

[0081] Between the data line DL and the display driving circuit 200, there can be configured a lighting circuit unit 170 for checking whether the pixel is defective, a demultiplexing unit 160, an inspection unit 150 for checking the generation of cracks in the display panel 100 and defects in the spider web wiring, and a spider web wiring (hereinafter referred to as a fan-out line FOL) for transmitting the output of the display driving circuit 200.

[0082] In some embodiments, the odd-numbered fan-out lines FOL1, FOL3, ..., FOLm-1 and the even-numbered fan-out lines FOL2, FOL4, ..., FOLm may be arranged in different layers with at least one insulating film placed in the middle. For example, the odd-numbered fan-out lines FOL1, FOL3, ..., FOLm-1 may be arranged adjacent to each other in the lower layer, at least one insulating film may be formed above the odd-numbered fan-out lines FOL1, FOL3, ..., FOLm-1, and the even-numbered fan-out lines FOL2, FOL4, ..., FOLm may be arranged adjacent to the layer above the at least one insulating film. At this time, the even-numbered fan-out lines FOL2, FOL4, ..., FOLm may be arranged between the odd-numbered fan-out lines FOL1, FOL3, ..., FOLm-1. As another example, the even-numbered fan-out lines FOL2, FOL4, ..., FOLm may be arranged adjacent to each other in the lower layer, at least one insulating film may be formed above the even-numbered fan-out lines FOL2, FOL4, ..., FOLm, and the odd-numbered fan-out lines FOL1, FOL3, ..., FOLm-1 may be arranged adjacent to each other in the layer above the at least one insulating film. However, this is not limited to this, and in some embodiments, the fan-out lines FOL1 to FOLm may also be arranged in the same layer.

[0083] The fan-out lines FOL1 to FOLm are formed like a spider web at intervals of 5 to 10 micrometers (um). Short circuits or open circuits often occur due to foreign matter after the process. Therefore, it is necessary to inspect whether the fan-out lines FOL1 to FOLm are defective.

[0084] The demultiplexer 160 connects the data lines DL and the fan-out lines FOL1 to FOLm between the data lines DL and the fan-out lines FOL1 to FOLm. The demultiplexer 160 transmits a plurality of signals transmitted through the fan-out lines FOL1 to FOLm to the corresponding data lines DL through a plurality of switches.

[0085] A display pad PAD connected to the display driving circuit 200 may be disposed in the non-display area NDA. The display driving circuit 200 and the display pad PAD may be disposed at one side edge of the display panel 100. The display pad PAD may be disposed closer to one side edge of the display panel 100 than the display driving circuit 200.

[0086] The scan driving circuit may be connected to the display driving circuit 200 through a plurality of scan control lines. The scan driving circuit may receive an input scan control signal SCS and a light emission control signal ECS from the display driving circuit 200 through the plurality of scan control lines.

[0087] like Figure 3 As shown, the scan driving circuit SDC may include a scan driving part 410 and a light emission control driving part 420 .

[0088] The scan driving unit 410 may generate a scan signal according to the scan control signal SCS and sequentially output the scan signal to the scan lines SL. The light control driving unit 420 may generate a light control signal according to the light control signal ECS and sequentially output the light control signal to the light lines ELL.

[0089] like Figure 3 As shown, the display driving circuit 200 may include a timing control section 210 , a data driving section 220 and a power supply section 230 .

[0090] The timing control section 210 receives input digital video data DATA and a timing signal from the circuit board 300. The timing control section 210 may generate a scan control signal SCS for controlling the operation timing of the scan driving section 410, a light emission control signal ECS for controlling the operation timing of the light emission control driving section 420, and a data control signal DCS for controlling the operation timing of the data driving section 220 according to the timing signal. The timing control section 210 may output the scan control signal SCS to the scan driving section 410 and the light emission control signal ECS to the light emission control driving section 420 through a plurality of scan control lines. The timing control section 210 may output the digital video data DATA and the data control signal DCS to the data driving section 220.

[0091] The data driving unit 220 converts the digital video data DATA into analog positive / negative data voltages and outputs them to the data lines DL through the fan-out lines FOL. The sub-pixels SP are selected by the scan signals of the scan driving circuit SDC, and the data voltages are supplied to the selected sub-pixels SP.

[0092] The power supply unit 230 may generate a first driving voltage and supply it to the first driving voltage line VDDL. In addition, the power supply unit 230 may generate a second driving voltage and supply it to the cathode electrode of the organic light emitting diode of each sub-pixel SP. The first driving voltage may be a high potential voltage for driving the organic light emitting diode, and the second driving voltage may be a low potential voltage for driving the organic light emitting diode. That is, the first driving voltage may have a higher potential than the second driving voltage.

[0093] The display driving circuit 200 may be formed as an integrated circuit (IC) and attached to the display panel 100 in a COP (chip on plastic) manner, but is not limited thereto. In some embodiments, the display driving circuit 200 may also be formed as an integrated circuit (IC) and attached to the display panel 100 in a COG (chip on glass) manner, a COP (chip on plastic) manner, or an ultrasonic bonding manner. In some embodiments, the display driving circuit 200 may be attached to the circuit board 300. Below, the case where the display driving circuit 200 is formed as an integrated circuit (IC) and attached to the display panel 100 in a COP (chip on plastic) manner is described as an example.

[0094] In some embodiments, the display driving circuit 200 may include a driving integrated circuit and a plurality of bumps. The driving integrated circuit may be connected to the Fig.10 Multiple wiring pads DP1, DP2, DP3, and DP4 are shown.

[0095] The circuit board 300 can be attached to the display pad PAD using an anisotropic conductive film. Thus, the leads of the circuit board 300 can be electrically connected to the display pad PAD. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0096] In some embodiments, the lighting inspection, crack inspection, and fan-out line FOL1 to FOLm inspection of the display panel 100 may be performed before attaching the circuit board 300. When performing the lighting inspection, crack inspection, and fan-out line FOL1 to FOLm inspection of the display panel 100, the inspection circuit board may be attached to the display pad PAD. The inspection circuit board may supply signals required for the lighting inspection, crack inspection, and fan-out line FOL1 to FOLm inspection of the display panel 100.

[0097] A crack sensing line CDL may be disposed in the non-display area NDA. The crack sensing line CDL may be disposed in a form surrounding the periphery of the display area DA, and the crack sensing line CDL may be connected to the inspection unit 150. For example, one end and the other end of the crack sensing line CDL may be connected to the inspection unit 150, respectively. Whether a crack of the display panel 100 is generated may be sensed by a resistance change based on damage of the crack sensing line CDL.

[0098] In addition, one end of the fan-out lines FOL1 to FOLm may be connected to the data line DL, and the other end of the fan-out lines FOL1 to FOLm may be connected to the inspection unit 150. The inspection unit 150 may inspect whether the fan-out lines FOL1 to FOLm are defective due to a short circuit or an open circuit. In this way, the inspection unit 150 may inspect whether the crack sensing line CDL is damaged and whether the fan-out lines FOL1 to FOLm are defective. The inspection of the crack sensing line CDL and the fan-out lines FOL1 to FOLm by the inspection unit 150 will be described in more detail later.

[0099] Figure 4 is a circuit diagram illustrating a sub-pixel according to an embodiment in detail.

[0100] Reference Figure 4 , the sub-pixel SP can be connected to the k-1th (k is a positive integer greater than 2) scanning line Sk-1, the kth scanning line Sk, the k+1th scanning line Sk+1, and the jth (j is a positive integer) data line Dj. In addition, the sub-pixel SP can be connected to the first driving voltage line VDDL supplying the first driving voltage, the initialization voltage line VIL supplying the initialization voltage Vini, and the second driving voltage line VSSL supplying the second driving voltage.

[0101] The sub-pixel SP includes a driving transistor DT, a light emitting element (LE), a switching element, a capacitor C, etc. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

[0102] The driving transistor DT controls the drain-source current Ids (hereinafter referred to as "driving current") according to the data voltage applied to the gate electrode. As shown in Mathematical Formula 1, the driving current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the gate-source voltage difference Vsg of the driving transistor DT and the threshold voltage.

[0103] (Mathematical formula 1)

[0104] Ids = k' × (Vsg - Vth) 2

[0105] In Mathematical Formula 1, k′ means a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vsg means a gate-source voltage of the driving transistor DT, and Vth means a threshold voltage of the driving transistor.

[0106] The light emitting element EL emits light according to the driving current Ids. The amount of light emitted by the light emitting element EL may be proportional to the driving current Ids.

[0107] The light emitting element EL may be an organic light emitting diode including an anode electrode, a cathode electrode, and an organic light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be a quantum dot light emitting element including an anode electrode, a cathode electrode, and a quantum dot light emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be a micro light emitting diode.

[0108] The anode electrode of the light emitting element EL may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second driving voltage line VSSL. A parasitic capacitor Cel may be formed between the anode electrode and the cathode electrode of the light emitting element EL.

[0109] The first transistor ST1 is turned on by the scanning signal of the kth scanning line Sk to connect the first electrode of the driving transistor DT and the jth data line Dj. The gate electrode of the first transistor ST1 is connected to the kth scanning line Sk, the first electrode is connected to the first electrode of the driving transistor DT, and the second electrode is connected to the data line Dj.

[0110] The second transistor ST2 may be formed by a double transistor including a 2-1 transistor ST2-1 and a 2-2 transistor ST2-2. The 2-1 transistor ST2-1 and the 2-2 transistor ST2-2 are turned on by the scan signal of the k-th scan line Sk so that the gate electrode of the driving transistor DT and the second electrode are connected. That is, when the 2-1 transistor ST2-1 and the 2-2 transistor ST2-2 are turned on, the gate electrode of the driving transistor DT and the second electrode are connected, so the driving transistor DT is driven by a diode. The gate electrode of the 2-1 transistor ST2-1 may be connected to the k-th scan line Sk, the first electrode may be connected to the second electrode of the 2-2 transistor ST2-2, and the second electrode may be connected to the gate electrode of the driving transistor DT. The gate electrode of the 2-2 transistor ST2-2 may be connected to the k-th scan line Sk, the first electrode may be connected to the second electrode of the driving transistor DT, and the second electrode may be connected to the first electrode of the 2-1 transistor ST2-1.

[0111] The third transistor ST3 may be formed by a double transistor including a 3-1 transistor ST3-1 and a 3-2 transistor ST3-2. The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 are turned on by the scan signal of the k-1 scan line Sk-1 to connect the gate electrode of the driving transistor DT to the initialization voltage line VIL. The gate electrode of the driving transistor DT may be discharged with the initialization voltage of the initialization voltage line VIL. The gate electrode of the 3-1 transistor ST3-1 may be connected to the k-1 scan line Sk-1, the first electrode may be connected to the gate electrode of the driving transistor DT, and the second electrode may be connected to the first electrode of the 3-2 transistor ST3-2. The gate electrode of the 3-2 transistor ST3-2 may be connected to the k-1 scan line Sk-1, the first electrode may be connected to the second electrode of the 3-1 transistor ST3-1, and the second electrode may be connected to the initialization voltage line VIL.

[0112] The fourth transistor ST4 is turned on by the scanning signal of the k+1 scanning line Sk+1 to connect the anode electrode of the light emitting element EL and the initialization voltage line VIL. The anode electrode of the light emitting element EL can be discharged with the initialization voltage. The gate electrode of the fourth transistor ST4 is connected to the k+1 scanning line Sk+1, the first electrode is connected to the anode electrode of the light emitting element EL, and the second electrode is connected to the initialization voltage line VIL.

[0113] The fifth transistor ST5 is turned on by the light emitting control signal of the k-th light emitting line Ek to connect the first electrode of the driving transistor DT and the first driving voltage line VDDL. The gate electrode of the fifth transistor ST5 is connected to the k-th light emitting line Ek, the first electrode is connected to the first driving voltage line VDDL, and the second electrode is connected to the first electrode of the driving transistor DT.

[0114] The sixth transistor ST6 is connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element EL. The sixth transistor ST6 is turned on by the light emitting control signal of the k-th light emitting line Ek to connect the second electrode of the driving transistor DT and the anode electrode of the light emitting element EL. The gate electrode of the sixth transistor ST6 is connected to the k-th light emitting line Ek, the first electrode is connected to the second electrode of the driving transistor DT, and the second electrode is connected to the anode electrode of the light emitting element EL. When the fifth transistor ST5 and the sixth transistor ST6 are both turned on, the driving current Ids can be supplied to the light emitting element EL.

[0115] The capacitor C is formed between the gate electrode of the driving transistor DT and the first driving voltage line VDDL. One electrode of the capacitor C may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first driving voltage line VDDL. The capacitor C plays a role in maintaining the voltage of the gate electrode of the driving transistor DT during one frame period.

[0116] When the first electrode of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT is a source electrode, the second electrode may be a drain electrode. Alternatively, when the first electrode of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT is a drain electrode, the second electrode may be a source electrode.

[0117] The active layers of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may also be formed of any one of polysilicon, amorphous silicon and an oxide semiconductor. When the semiconductor layers of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT are formed of polysilicon, the process used to form them may be a low temperature polysilicon (LTPS) process.

[0118] In addition, Figure 4In the description, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT are mainly formed by P-type MOSFET (Meta-Loxide Semiconductor Field Effect Transistor), but the present invention is not limited thereto and they may also be formed by N-type MOSFET. When the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT are formed by N-type MOSFET, the following should be modified: Figure 5 The timing diagram is designed to suit the characteristics of N-type MOSFET.

[0119] The first driving voltage of the first driving voltage line VDDL, the second driving voltage of the second driving voltage line VSSL, and the initialization voltage of the initialization voltage line Vini may be set in consideration of the characteristics of the driving transistor DT, the characteristics of the light emitting element EL, etc. For example, the voltage difference between the initialization voltage and the data voltage supplied to the source electrode of the driving transistor DT may be set to be smaller than the threshold voltage of the driving transistor DT.

[0120] Figure 5 It is shown that the Figure 4 Waveform diagram of signals of the k-1th scan line, the kth scan line, the k+1th scan line and the kth light emitting line.

[0121] Reference Figure 5 , the k-1th scanning signal SCANk-1 applied to the k-1th scanning line Sk-1 is a signal for controlling the on / off of the third transistor ST3. The k-1th scanning signal SCANk applied to the k-1th scanning line Sk is a signal for controlling the on / off of the first transistor ST1 and the second transistor ST2. The k+1th scanning signal SCANk+1 applied to the k+1th scanning line Sk+1 is a signal for controlling the on / off of the fourth transistor ST4. The k-th light emitting signal EMk is a signal for controlling the fifth transistor ST5 and the sixth transistor ST6.

[0122] The k-1th scanning signal SCANk-1, the kth scanning signal SCANk, the k+1th scanning signal SCANk+1, and the kth light emitting signal EMk may be generated with one frame period as a cycle. One frame period may be divided into a first period t1 to a fourth period t4. The first period t1 is a period for initializing the gate electrode of the driving transistor DT, the second period t2 is a period for supplying a data voltage to the gate electrode of the driving transistor DT and sampling the threshold voltage of the driving transistor DT, the third period t3 is a period for initializing the anode electrode of the light emitting element EL, and the fourth period t4 is a period for the light emitting element EL to emit light.

[0123] The k-1th scan signal SCANk-1, the kth scan signal SCANk, and the k+1th scan signal SCANk+1 may be output as the gate-on voltage Von in the first period t1, the second period t1, and the third period t3, respectively. For example, the k-1th scan signal SCANk-1 may have the gate-on voltage Von in the first period t1, and the gate-off voltage Voff in the remaining period. The kth scan signal SCANk may have the gate-on voltage Von in the second period t2, and the gate-off voltage Voff in the remaining period. The k+1th scan signal SCANk+1 may have the gate-on voltage Von in the third period t3, and the gate-off voltage Voff in the remaining period. Figure 5 , the period during which the k-1th scanning signal SCANk-1 has the gate-on voltage Von is shorter than the first period t1, but the period during which the k-1th scanning signal SCANk-1 has the gate-on voltage Von may be substantially the same as the first period t1. Figure 5 , the period during which the k-th scanning signal SCANk has the gate-on voltage Von is shorter than the second period t2, but the period during which the k-th scanning signal SCANk has the gate-on voltage Von may be substantially the same as the second period t2. Figure 5 2 , the period during which the k+1th scan signal SCANk+1 has the gate-on voltage Von is shorter than the third period t3 . However, the period during which the k+1th scan signal SCANk+1 has the gate-on voltage Von may be substantially the same as the third period t3 .

[0124] The kth light emitting signal EMk may have the gate-on voltage Von in the fourth period t4 and have the gate-off voltage Voff in the remaining period.

[0125] exist Figure 51, 2, and 3 are each one horizontal period. One horizontal period specifies the period during which the data voltage is supplied to each sub-pixel SP connected to a certain scanning line of the display panel 100, and thus can be defined as one horizontal line scanning period. The data voltage can be supplied to the data line DL in synchronization with the gate-on voltage Von of each scanning signal.

[0126] The gate-on voltage Von corresponds to an on-voltage that can turn on each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6. The gate-off voltage Voff corresponds to an off-voltage that can turn off each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6.

[0127] Figures 6 to 9 It is used to illustrate Figure 5 A circuit diagram of a driving method of the first sub-pixel in the first period to the fourth period.

[0128] Next, combine Figures 5 to 9 The operation of the sub-pixel SP in the first period t1 to the fourth period t4 will be described in detail.

[0129] First, in the first period t1, the k-1th scan signal SCANk-1 having the gate-on voltage Von is supplied to the k-1th scan line Sk-1. Figure 6 As shown, in the first period t1, the third transistor ST3 is turned on by the k-1th scanning signal SCANk-1 having the gate-on voltage Von. Due to the turning on of the third transistor ST3, the gate electrode of the driving transistor DT is initialized to the initialization voltage Vini of the initialization voltage line VIL.

[0130] Second, in the second period t2, the k-th scanning signal SCANk having the gate-on voltage Von is supplied to the k-th scanning line Sk. Figure 7 As shown, in the second period t2, the first transistor ST1 and the second transistor ST2 are turned on by the kth scanning signal SCANk having the gate-on voltage Von.

[0131] By turning on the second transistor ST2, the gate electrode and the second electrode of the driving transistor DT are connected to each other, and the driving transistor DT is driven by a diode. By turning on the first transistor ST1, the data voltage Vdata is supplied to the first electrode of the driving transistor DT. At this time, the voltage difference between the gate electrode and the first electrode of the driving transistor DT (Vsg = Vdata-Vini) is greater than the threshold voltage Vth, so the driving transistor DT forms a current path until the voltage difference Vsg between the gate electrode and the source electrode reaches the threshold voltage Vth. As a result, in the second period t2, the gate electrode and the second electrode of the driving transistor DT rise to the difference voltage (Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. "Vdata-Vth" can be stored in the capacitor C.

[0132] Third, in the third period t3, the k+1th scan signal SCANk+1 having the gate-on voltage Von is supplied to the k+1th scan line Sk+1. Figure 8 As shown, in the third period t3, the fourth transistor ST4 is turned on by the k+1th scanning signal SCANk+1 having the gate-on voltage Von. By turning on the fourth transistor ST4, the anode electrode of the light emitting element EL is initialized to the initialization voltage Vini of the initialization voltage line VIL.

[0133] Fourth, in the fourth period t4, the kth light emitting signal EMk having the gate-on voltage Von is supplied to the kth light emitting line Ek. Fig. 9 As shown, in the fourth period t4, the fifth transistor ST5 and the sixth transistor ST6 are turned on by the kth light emitting signal EMk having the gate-on voltage Von, respectively.

[0134] When the fifth transistor ST5 is turned on, the first electrode of the driving transistor DT is connected to the first driving voltage line VDDL. When the sixth transistor ST6 is turned on, the second electrode of the driving transistor DT is connected to the anode electrode of the light emitting element EL.

[0135] When the fifth transistor ST5 and the sixth transistor ST6 are turned on, a driving current Ids flowing according to the voltage of the gate electrode of the driving transistor DT can be supplied to the light emitting element EL. The driving current Ids can be defined as in Formula 2.

[0136] (Mathematical formula 2)

[0137] Ids=k'×(ELVDD-(Vdata-Vth)-Vth) 2

[0138] In Mathematical Formula 2, k' refers to a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vth refers to the threshold voltage of the driving transistor DT, ELVDD refers to the first driving voltage of the first driving voltage line VDDL, and Vdata refers to the data voltage. The gate voltage of the driving transistor DT is "Vdata-Vth", and the voltage of the first electrode is ELVDD. If Mathematical Formula 2 is rearranged, Mathematical Formula 3 is derived.

[0139] (Mathematical formula 3)

[0140] Ids=k′×(ELVDD-Vdata) 2

[0141] Finally, the driving current Ids does not depend on the threshold voltage Vth of the driving transistor DT as shown in Math 3. That is, the threshold voltage Vth of the driving transistor DT is compensated.

[0142] On the other hand, Fig. 9 As shown, the driving current Ids is supplied not only to the light emitting element EL but also to the parasitic capacitor Cel. However, the driving transistor DT is composed of two transistors connected in parallel and can provide a high driving current Ids, which can drive the light emitting element EL at high brightness while reducing the time to charge the parasitic capacitor Cel.

[0143] Fig.10 is a diagram showing a circuit structure of a display device according to an embodiment, Fig.11 as well as Fig.12 is a timing diagram for explaining a fan-out line inspection in a display device according to an embodiment, Fig.13 is a timing chart for explaining crack inspection in a display device according to an embodiment.

[0144] Reference Fig.10 In some embodiments, the display device 10 may include an inspection section 150 , a demultiplexing section 160 , and a lighting circuit section 170 disposed between the sub-pixel SP and the wiring pad DP.

[0145] For ease of explanation, Fig.10 Only a part of the sub-pixels SP arranged in the display device 10 is shown, and only the first data line DL1 to the eighth data line DL8 connected to the sub-pixels SP are shown.

[0146] In some embodiments, the sub-pixel SP may include a red sub-pixel R that emits red light, a blue sub-pixel B that emits blue light, and a green sub-pixel G that emits green light. The red sub-pixels R and the blue sub-pixels B may be arranged alternately in the same column, and the green sub-pixels G may be arranged in a column adjacent to the column in which the red sub-pixels R and the blue sub-pixels B are arranged. At this time, the red sub-pixels R and the blue sub-pixels B are centered on the column in which the green sub-pixels G are arranged, and the red sub-pixels R themselves and the blue sub-pixels B themselves are located in the diagonal direction and arranged in the form of a checker board. That is, the red sub-pixels R and the blue sub-pixels B may be arranged alternately so as not to be repeatedly arranged in the same column in two adjacent rows. The data line DL is configured in each column.

[0147] In some embodiments, the first data line DL1 may be connected to the first column where red sub-pixels R and blue sub-pixels B are alternately arranged, the second data line DL2 may be connected to the second column where green sub-pixels G are arranged, the third data line DL3 may be connected to the third column where red sub-pixels R and blue sub-pixels B are alternately arranged in an order opposite to that of the first column, the fourth data line DL4 may be connected to the fourth column where green sub-pixels G are arranged, the fifth data line DL5 may be connected to the fifth column where red sub-pixels R and blue sub-pixels B are alternately arranged in the same order as that of the first column, the sixth data line DL6 may be connected to the sixth column where green sub-pixels G are arranged, the seventh data line DL7 may be connected to the seventh column where red sub-pixels R and blue sub-pixels B are alternately arranged in an order opposite to that of the first column, and the eighth data line DL8 may be connected to the eighth column where green sub-pixels G are arranged.

[0148] In the embodiment of the present disclosure, the sub-pixel SP is described as being composed of a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G. However, the sub-pixel SP may also include colors other than red, green, and blue.

[0149] The wiring pad DP can be Figure 2 The driver integrated circuit is connected to the wiring pad DP through a plurality of bumps in the region where the display driver circuit 200 is arranged. The wiring pad DP may illustratively include a first wiring pad DP1 to a fourth wiring pad DP4.

[0150] The first fan-out lines FOL1 to the fourth fan-out lines FOL4 connected to the first data lines DL1 to the eighth data lines DL8 may be configured on the first wiring pad DP1 to the fourth wiring pad DP4. For example, the first fan-out line FOL1 may connect the first wiring pad DP1 to the first data line DL1 and the second data line DL2, the second fan-out line FOL2 may connect the second wiring pad DP2 to the third data line DL3 and the fourth data line DL4, the third fan-out line FOL3 may connect the third wiring pad DP3 to the fifth data line DL5 and the sixth data line DL6, and the fourth fan-out line FOL4 may connect the fourth wiring pad DP4 to the seventh data line DL7 and the eighth data line DL8.

[0151] The first fan-out line FOL1 to the fourth fan-out line FOL4 can be configured to extend in the second direction (Y-axis direction) and be separated from each other in the first direction (X-axis direction). In addition, in some embodiments, the first fan-out line FOL1 and the third fan-out line FOL3 and the second fan-out line FOL2 and the fourth fan-out line FOL4 can be configured in different layers with at least one insulating film placed between them. For example, the first fan-out line FOL1 and the third fan-out line FOL3 can be arranged adjacent to each other in the lower layer, at least one insulating film is formed above the first fan-out line FOL1 and the third fan-out line FOL3, and the second fan-out line FOL2 and the fourth fan-out line FOL4 are arranged adjacent to each other in the layer above the at least one insulating film. At this time, the second fan-out line FOL2 and the fourth fan-out line FOL4 can be arranged between the first fan-out line FOL1 and the third fan-out line FOL3. As another example, the second fan-out line FOL2 and the fourth fan-out line FOL4 may be arranged adjacent to each other in a lower layer, at least one insulating film may be formed above the second fan-out line FOL2 and the fourth fan-out line FOL4, and the first fan-out line FOL1 and the third fan-out line FOL3 may be arranged adjacent to each other in a layer above the at least one insulating film.

[0152] The inspection unit 150 , the demultiplexing unit 160 , and the lighting circuit unit 170 may be sequentially arranged between the sub-pixel SP and the first to fourth wiring pads DP1 to DP4 .

[0153] In some embodiments, the inspection unit 150 may include a first control line 151 , a second control line 153 , a data voltage line 155 , and a switch.

[0154] The first control line 151 , the second control line 153 , and the data voltage line 155 may extend in the first direction (X-axis direction) and be spaced apart from each other in the second direction (Y-axis direction).

[0155] The switches that may be the inspection unit 150 include: a first switch SW11 connected to the first fan-out line FOL1; a second switch SW12 connected to the second fan-out line FOL2; a third switch SW13 connected to the third fan-out line FOL3; and a fourth switch SW14 connected to the fourth fan-out line FOL4.

[0156] Specifically, the first switch SW11 may have a gate connected to the first control line 151 supplying the first inspection control signal MCD_GATE1, a first terminal connected to the first fan-out line FOL1, and a second terminal connected to the data voltage line 155 supplying the black data voltage VGH. The first switch SW11 may be turned on by the first inspection control signal MCD_GATE1 to connect the data voltage line 155 and the first fan-out line FOL1.

[0157] The second switch SW12 may have a gate connected to the first control line 151 supplying the first inspection control signal MCD_GATE1, a first terminal connected to the second fan-out line FOL2, and a second terminal connected to the data voltage line 155 supplying the black data voltage VGH. The second switch SW12 may be turned on by the first inspection control signal MCD_GATE1 to connect the data voltage line 155 and the second fan-out line FOL2.

[0158] The third switch SW13 may have a gate connected to the second control line 153 supplying the second inspection control signal MCD_GATE2, a first terminal connected to the third fan-out line FOL3, and a second terminal connected to the data voltage line 155 supplying the black data voltage VGH. The third switch SW13 may be turned on by the second inspection control signal MCD_GATE1 to connect the data voltage line 155 and the third fan-out line FOL3.

[0159] The fourth switch SW14 may have a gate connected to the second control line 153 supplying the second inspection control signal MCD_GATE2, a first terminal connected to the fourth fan-out line FOL4, and a second terminal connected to the data voltage line 155 supplying the black data voltage VGH. The fourth switch SW14 may be turned on by the second inspection control signal MCD_GATE2 to connect the data voltage line 155 and the fourth fan-out line FOL4.

[0160] In some embodiments, the demultiplexer 160 transmits the black data voltage VGH transmitted through the first to fourth wiring pads DP1 to DP4 to the corresponding data lines DL through a plurality of switches. The demultiplexer 160 may include a third control line 161, a fourth control line 163, and switches.

[0161] The third control line 161 and the fourth control line 163 may extend in the first direction (X-axis direction) and be spaced apart from each other in the second direction (Y-axis direction).

[0162] The switches of the demultiplexing unit 160 may include: a fifth switch SW21 and a sixth switch SW22 connected to the first fan-out line FOL1; a seventh switch SW23 and an eighth switch SW24 connected to the second fan-out line FOL2; a ninth switch SW25 and a tenth switch SW26 connected to the third fan-out line FOL3; and an eleventh switch SW27 and a twelfth switch SW28 connected to the fourth fan-out line FOL4.

[0163] Specifically, the fifth switch SW21 may have a gate connected to the third control line 161 supplying the first demultiplexing control signal CLA, a first terminal connected to the first fan-out line FOL1, and a second terminal connected to the first data line DL1. The fifth switch SW21 may be turned on by the first demultiplexing control signal CLA to connect the first fan-out line FOL1 and the first data line DL1.

[0164] The sixth switch SW22 may have a gate connected to the fourth control line 163 supplying the second demultiplexing control signal CLB, a first terminal connected to the first fan-out line FOL1, and a second terminal connected to the second data line DL2. The sixth switch SW22 may be turned on by the second demultiplexing control signal CLB to connect the first fan-out line FOL1 and the second data line DL2.

[0165] The seventh switch SW23 may have a gate connected to the third control line 161 supplying the first demultiplexing control signal CLA, a first terminal connected to the second fan-out line FOL2, and a second terminal connected to the third data line DL3. The seventh switch SW23 may be turned on by the first demultiplexing control signal CLA to connect the second fan-out line FOL2 and the third data line DL3.

[0166] The eighth switch SW24 may have a gate connected to the fourth control line 163 supplying the second demultiplexing control signal CLB, a first terminal connected to the second fan-out line FOL2, and a second terminal connected to the fourth data line DL4. The eighth switch SW24 may be turned on by the second demultiplexing control signal CLB to connect the second fan-out line FOL2 and the fourth data line DL4.

[0167] The ninth switch SW25 may have a gate connected to the third control line 161 supplying the first demultiplexing control signal CLA, a first terminal connected to the third fan-out line FOL3, and a second terminal connected to the fifth data line DL5. The ninth switch SW25 may be turned on by the first demultiplexing control signal CLA to connect the third fan-out line FOL3 and the fifth data line DL5.

[0168] The tenth switch SW26 may have a gate connected to the fourth control line 163 supplying the second demultiplexing control signal CLB, a first terminal connected to the third fan-out line FOL3, and a second terminal connected to the sixth data line DL6. The tenth switch SW26 may be turned on by the second demultiplexing control signal CLB to connect the third fan-out line FOL3 and the sixth data line DL6.

[0169] The 11th switch SW27 may have a gate connected to the third control line 161 supplying the first demultiplexing control signal CLA, a first terminal connected to the fourth fan-out line FOL4, and a second terminal connected to the seventh data line DL7. The 11th switch SW27 may be turned on by the first demultiplexing control signal CLA to connect the fourth fan-out line FOL4 and the seventh data line DL7.

[0170] The twelfth switch SW28 may have a gate connected to the fourth control line 163 supplying the second demultiplexing control signal CLB, a first terminal connected to the fourth fan-out line FOL4, and a second terminal connected to the eighth data line DL8. The twelfth switch SW28 may be turned on by the second demultiplexing control signal CLB to connect the fourth fan-out line FOL4 and the eighth data line DL8.

[0171] exist Fig.10 In the description, the case where the demultiplexing unit 160 is configured with two switches corresponding to one fan-out line FOL is described as an example, but the present invention is not limited thereto. Three or more switches may be configured corresponding to one fan-out line FOL. In this case, one fan-out line FOL may be connected to three or more data lines DL.

[0172] In some embodiments, the lighting circuit unit 170 may include a fifth control line 171, a sixth control line 173, a seventh control line 175, a first lighting check signal line 177, a second lighting check signal line 178, a third lighting check signal line 179, and a switch. The fifth control line 171, the sixth control line 173, the seventh control line 175, the first lighting check signal line 177, the second lighting check signal line 178, and the third lighting check signal line 179 may extend in the first direction (X-axis direction) and be spaced apart from each other in the second direction (Y-axis direction).

[0173] The switches of the lighting circuit unit 170 may include: a 13th switch SW31 and a 14th switch SW32 connected to the 1st data line DL1; a 15th switch SW33 connected to the 2nd data line DL2; a 16th switch SW34 and a 17th switch SW35 connected to the 3rd data line DL3; an 18th switch SW36 connected to the 4th data line DL4; a 19th switch SW37 and a 20th switch SW38 connected to the 5th data line DL5; a 21st switch SW39 connected to the 6th data line DL6; a 22nd switch SW40 and a 23rd switch SW41 connected to the 7th data line DL7; and a 24th switch SW42 connected to the 8th data line DL8.

[0174] Specifically, the 13th switch SW31 may have a gate connected to the 5th control line 171 supplying the 1st lighting check control signal TEST_GATE_R, a first terminal connected to the 1st lighting check signal line 177 supplying the 1st lighting check signal DC_R, and a second terminal connected to the 1st data line DL1. The 13th switch SW31 may be turned on by the 1st lighting check control signal TEST_GATE_R to connect the 1st lighting check signal line 177 and the 1st data line DL1.

[0175] The 14th switch SW32 may have a gate connected to the 6th control line 173 supplying the second lighting check control signal TEST_GATE_B, a first terminal connected to the second lighting check signal line 178 supplying the second lighting check signal DC_B, and a second terminal connected to the first data line DL1. The 14th switch SW32 may be turned on by the second lighting check control signal TEST_GATE_B to connect the second lighting check signal line 178 and the first data line DL1.

[0176] The 15th switch SW33 may have a gate connected to the 7th control line 175 supplying the 3rd lighting check control signal TEST_GATE_G, a first terminal connected to the 3rd lighting check signal line 179 supplying the 3rd lighting check signal DC_G, and a second terminal connected to the 2nd data line DL2. The 15th switch SW33 may be turned on by the 3rd lighting check control signal TEST_GATE_G to connect the 3rd lighting check signal line 179 and the 2nd data line DL2.

[0177] The 16th switch SW34 may have a gate connected to the 6th control line 173 supplying the second lighting check control signal TEST_GATE_B, a first terminal connected to the 1st lighting check signal line 177 supplying the first lighting check signal DC_R, and a second terminal connected to the 3rd data line DL3. The 16th switch SW34 may be turned on by the second lighting check control signal TEST_GATE_B to connect the 1st lighting check signal line 177 and the 3rd data line DL3.

[0178] The 17th switch SW35 may have a gate connected to the 5th control line 171 supplying the 1st lighting check control signal TEST_GATE_R, a 1st terminal connected to the 2nd lighting check signal line 178 supplying the 2nd lighting check signal DC_B, and a 2nd terminal connected to the 3rd data line DL3. The 17th switch SW35 may be turned on by the 1st lighting check control signal TEST_GATE_R to connect the 2nd lighting check signal line 178 and the 3rd data line DL3.

[0179] The 18th switch SW36 may have a gate connected to the 7th control line 175 supplying the 3rd lighting check control signal TEST_GATE_G, a first terminal connected to the 3rd lighting check signal line 179 supplying the 3rd lighting check signal DC_G, and a second terminal connected to the 4th data line DL4. The 18th switch SW36 may be turned on by the 3rd lighting check control signal TEST_GATE_G to connect the 3rd lighting check signal line 179 and the 4th data line DL4.

[0180] The 19th switch SW37 may have a gate connected to the fifth control line 171 supplying the first lighting check control signal TEST_GATE_R, a first terminal connected to the first lighting check signal line 177 supplying the first lighting check signal DC_R, and a second terminal connected to the fifth data line DL5. The 19th switch SW37 may be turned on by the first lighting check control signal TEST_GATE_R to connect the first lighting check signal line 177 and the fifth data line DL5.

[0181] The 20th switch SW38 may have a gate connected to the 6th control line 173 supplying the second lighting check control signal TEST_GATE_B, a first terminal connected to the 2nd lighting check signal line 178 supplying the second lighting check signal DC_B, and a second terminal connected to the 5th data line DL5. The 20th switch SW38 may be turned on by the second lighting check control signal TEST_GATE_B to connect the 2nd lighting check signal line 178 and the 5th data line DL5.

[0182] The 21st switch SW39 may have a gate connected to the 7th control line 175 supplying the 3rd lighting check control signal TEST_GATE_G, a 1st terminal connected to the 3rd lighting check signal line 179 supplying the 3rd lighting check signal DC_G, and a 2nd terminal connected to the 6th data line DL6. The 21st switch SW39 may be turned on by the 3rd lighting check control signal TEST_GATE_G to connect the 3rd lighting check signal line 179 and the 6th data line DL6.

[0183] The 22nd switch SW40 may have a gate connected to the 6th control line 173 supplying the 2nd lighting check control signal TEST_GATE_B, a first terminal connected to the 1st lighting check signal line 177 supplying the 1st lighting check signal DC_R, and a second terminal connected to the 7th data line DL7. The 22nd switch SW40 may be turned on by the 2nd lighting check control signal TEST_GATE_B to connect the 1st lighting check signal line 177 and the 7th data line DL7.

[0184] The 23rd switch SW41 may have a gate connected to the 5th control line 171 supplying the 1st lighting check control signal TEST_GATE_R, a 1st terminal connected to the 2nd lighting check signal line 178 supplying the 2nd lighting check signal DC_B, and a 2nd terminal connected to the 7th data line DL7. The 23rd switch SW41 may be turned on by the 1st lighting check control signal TEST_GATE_R to connect the 2nd lighting check signal line 178 and the 7th data line DL7.

[0185] The 24th switch SW42 may have a gate connected to the 7th control line 175 supplying the 3rd lighting check control signal TEST_GATE_G, a first terminal connected to the 3rd lighting check signal line 179 supplying the 3rd lighting check signal DC_G, and a second terminal connected to the 8th data line DL8. The 24th switch SW42 may be turned on by the 3rd lighting check control signal TEST_GATE_G to connect the 3rd lighting check signal line 179 and the 8th data line DL8.

[0186] The first switch SW11 to the fourth switch SW14, the fifth switch SW21 to the twelfth switch SW28, and the thirteenth switch SW31 to the twenty-fourth switch SW42 may be implemented by transistors. In this case, the gate, the first terminal, and the second terminal of the first switch SW11 to the fourth switch SW14, the fifth switch SW21 to the twelfth switch SW28, and the thirteenth switch SW31 to the twenty-fourth switch SW42 may correspond to the gate electrode, the first electrode, and the second electrode of the transistor, respectively, and the first electrode and the second electrode may be the source electrode or the drain electrode.

[0187] Will Fig.10 , Fig.11 as well as Fig.12 The inspection of the fan-out lines FOL will be described with reference to the above. Failure detection between adjacent fan-out lines ( FOL1 and FOL3 , FOL2 and FOL4 , etc.) on the same layer can be performed by the inspection unit 150 .

[0188] The lighting circuit section 170 may be inactive during the inspection of the fan-out line FOL. For example, a high-level lighting inspection control signal TEST_GATE_R / G / B and a lighting inspection signal DC_R / G / B may be applied to the lighting circuit section 170 .

[0189] Reference Fig.11 The inspection unit 150 may be activated during the inspection period of the fan-out line FOL. For example, the low-level first inspection control signal MCD_GATE1 is applied to the gates of the first switch SW11 and the second switch SW12, and the first switch SW11 and the second switch SW12 are turned on. Thus, the first fan-out line FOL1 and the second fan-out line FOL2 may be connected to the data voltage line 155.

[0190] The black data voltage VGH may be input to the data voltage line 155. However, the present invention is not limited thereto, and data voltages of other gray levels may be input. The first switch SW11 and the second switch SW12 may be turned on, and the black data voltage VGH may be applied to the first fan-out line FOL1 and the second fan-out line FOL2.

[0191] In addition, the high-level second inspection control signal MCD_GATE2 is applied to the gates of the third switch SW13 and the fourth switch SW14, and the third switch SW13 and the fourth switch SW14 maintain the off state. As a result, the black data voltage VGH is not applied to the third fan-out line FOL3 and the fourth fan-out line FOL4. In this way, different signals can be applied to the first fan-out line FOL1 and the third fan-out line FOL3 adjacent to each other in the same layer. That is, the black data voltage VGH is applied to the first fan-out line FOL1, and the black data voltage VGH is not applied to the third fan-out line FOL3. In addition, different signals can be applied to the second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer. That is, the black data voltage VGH is applied to the second fan-out line FOL2, and the black data voltage VGH is not applied to the fourth fan-out line FOL4.

[0192] The demultiplexing unit 160 may be activated during the inspection period of the fan-out line FOL. For example, the low-level first demultiplexing control signal CLA and the second demultiplexing control signal CLB are applied to the gates of the fifth switch SW21 to the twelfth switch SW28, and the fifth switch SW21 to the twelfth switch SW28 are turned on.

[0193] The first fan-out line FOL1 can be connected to the first data line DL1 and the second data line DL2 respectively by turning on the fifth switch SW21 and the sixth switch SW22, the second fan-out line FOL2 can be connected to the third data line DL3 and the fourth data line DL4 respectively by turning on the seventh switch SW23 and the eighth switch SW24, the third fan-out line FOL3 can be connected to the fifth data line DL5 and the sixth data line DL6 respectively by turning on the ninth switch SW25 and the tenth switch SW26, and the fourth fan-out line FOL4 can be connected to the seventh data line DL7 and the eighth data line DL8 respectively by turning on the eleventh switch SW27 and the twelfth switch SW28.

[0194] Thus, the sub-pixel SP connected to the 1st data line DL1 and the 2nd data line DL2 connected to the 1st fan-out line FOL1 displays black, the sub-pixel SP connected to the 3rd data line DL3 and the 4th data line DL4 connected to the second fan-out line FOL2 displays black, the sub-pixel SP connected to the 5th data line DL5 and the 6th data line DL6 connected to the 3rd fan-out line FOL3 displays white, and the sub-pixel SP connected to the 7th data line DL7 and the 8th data line DL8 connected to the 4th fan-out line FOL4 displays white.

[0195] The adjacent 1st fan-out line FOL1 and 3rd fan-out line FOL3 in the same layer are applied with voltages of different gray levels, so the defectiveness of the 1st fan-out line FOL1 and the 3rd fan-out line FOL3 can be judged by the lighting state of the sub-pixel SP connected to the 1st fan-out line FOL1 and the 3rd fan-out line FOL3. For example, when the 1st fan-out line FOL1 and the 3rd fan-out line FOL3 are short-circuited (Short), the sub-pixel SP connected to the 3rd fan-out line FOL3 displays black or generates dark lines, so it is easy to judge whether the 1st fan-out line FOL1 and the 3rd fan-out line FOL3 are short-circuited or not. When the 1st fan-out line FOL1 is broken (Open), the sub-pixel SP connected to the 1st fan-out line FOL1 displays white, so it is easy to judge whether the 1st fan-out line FOL1 is broken or not.

[0196] The second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer are applied with voltages of different gray levels, so the defectiveness of the second fan-out line FOL2 and the fourth fan-out line FOL4 can be judged by the lighting state of the sub-pixel SP connected to the second fan-out line FOL2 and the fourth fan-out line FOL4. For example, when the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited (Short), the sub-pixel SP connected to the fourth fan-out line FOL4 displays black or generates dark lines, so it is easy to judge whether the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited or not. When the second fan-out line FOL2 is broken (Open), the sub-pixel SP connected to the second fan-out line FOL2 displays white, so it is easy to judge whether the second fan-out line FOL2 is broken or not.

[0197] Reference Fig.12 The inspection unit 150 may be activated during the inspection of the fan-out line FOL. For example, the second inspection control signal MCD_GATE2 of a low level is applied to the gates of the third switch SW13 and the fourth switch SW14, and the third switch SW13 and the fourth switch SW14 are turned on. Thus, the third fan-out line FOL3 and the fourth fan-out line FOL4 may be connected to the data voltage line 155.

[0198] The black data voltage VGH may be input to the data voltage line 155. However, the present invention is not limited thereto, and data voltages of other gray levels may be input. The third switch SW13 and the fourth switch SW14 may be turned on to apply the black data voltage VGH to the third fan-out line FOL3 and the fourth fan-out line FOL4.

[0199] In addition, the high-level first inspection control signal MCD_GATE1 is applied to the gates of the first switch SW11 and the second switch SW12, and the first switch SW11 and the second switch SW12 maintain the off state. As a result, the black data voltage VGH is not applied to the first fan-out line FOL1 and the second fan-out line FOL2. In this way, different signals can be applied to the first fan-out line FOL1 and the third fan-out line FOL3 adjacent to each other in the same layer. That is, the black data voltage VGH may not be applied to the first fan-out line FOL1, and the black data voltage VGH may be applied to the third fan-out line FOL3. In addition, different signals can be applied to the second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer. That is, the black data voltage VGH may not be applied to the second fan-out line FOL2, and the black data voltage VGH may be applied to the fourth fan-out line FOL4.

[0200] The demultiplexing unit 160 may be activated during the inspection period of the fan-out line FOL. For example, the low-level first demultiplexing control signal CLA and the second demultiplexing control signal CLB are applied to the gates of the fifth switch SW21 to the twelfth switch SW28, and the fifth switch SW21 to the twelfth switch SW28 are turned on.

[0201] The first fan-out line FOL1 can be connected to the first data line DL1 and the second data line DL2 respectively by turning on the fifth switch SW21 and the sixth switch SW22, the second fan-out line FOL2 can be connected to the third data line DL3 and the fourth data line DL4 respectively by turning on the seventh switch SW23 and the eighth switch SW24, the third fan-out line FOL3 can be connected to the fifth data line DL5 and the sixth data line DL6 respectively by turning on the ninth switch SW25 and the tenth switch SW26, and the fourth fan-out line FOL4 can be connected to the seventh data line DL7 and the eighth data line DL8 respectively by turning on the eleventh switch SW27 and the twelfth switch SW28.

[0202] Thus, the sub-pixel SP connected to the 1st data line DL1 and the 2nd data line DL2 connected to the 1st fan-out line FOL1 displays white, the sub-pixel SP connected to the 3rd data line DL3 and the 4th data line DL4 connected to the second fan-out line FOL2 displays white, the sub-pixel SP connected to the 5th data line DL5 and the 6th data line DL6 connected to the 3rd fan-out line FOL3 displays black, and the sub-pixel SP connected to the 7th data line DL7 and the 8th data line DL8 connected to the 4th fan-out line FOL4 displays black.

[0203] The adjacent 1st fan-out line FOL1 and 3rd fan-out line FOL3 in the same layer are applied with voltages of different gray levels, so the defectiveness of the 1st fan-out line FOL1 and the 3rd fan-out line FOL3 can be judged by the lighting state of the sub-pixel SP connected to the 1st fan-out line FOL1 and the 3rd fan-out line FOL3. For example, when the 1st fan-out line FOL1 and the 3rd fan-out line FOL3 are short-circuited (Short), the sub-pixel SP connected to the 1st fan-out line FOL1 displays black or generates dark lines, so it is easy to judge whether the 1st fan-out line FOL1 and the 3rd fan-out line FOL3 are short-circuited or not. In addition, when the 3rd fan-out line FOL3 is broken (Open), the sub-pixel SP connected to the 3rd fan-out line FOL3 displays white, so it is easy to judge whether the 1st fan-out line FOL1 or the 3rd fan-out line FOL3 is broken or not.

[0204] The second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer are applied with voltages of different gray levels, so the defectiveness of the second fan-out line FOL2 and the fourth fan-out line FOL4 can be judged by the lighting state of the sub-pixel SP connected to the second fan-out line FOL2 and the fourth fan-out line FOL4. For example, when the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited (Short), the sub-pixel SP connected to the second fan-out line FOL2 displays the set black or generates a dark line, so it is easy to judge whether the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited. In addition, when the fourth fan-out line FOL4 is broken (Open), the sub-pixel SP connected to the fourth fan-out line FOL4 displays white, so it is easy to judge whether the fourth fan-out line FOL4 is broken.

[0205] Reference Fig.13 During the crack inspection, the lighting circuit unit 170 may be inactive. For example, a high-level lighting inspection control signal TEST_GATE_R / G / B and a lighting inspection signal DC_R / G / B may be applied to the lighting circuit unit.

[0206] The demultiplexing unit 160 may be activated during crack inspection. For example, a low-level first demultiplexing control signal CLA and a second demultiplexing control signal CLB are applied to the gates of the fifth switch SW21 to the twelfth switch SW28, and the fifth switch SW21 to the twelfth switch SW28 are turned on.

[0207] The inspection unit 150 may be activated during the crack inspection. For example, the low-level first inspection control signal MCD_GATE1 and the second inspection control signal MCD_GATE2 are applied to the gates of the first switch SW11 to the fourth switch SW14, and the first switch SW11 to the fourth switch SW14 are turned on. Thus, the first fan-out line FOL1 to the fourth fan-out line FOL4 may be connected to the data voltage line 155.

[0208] A test voltage may be input to the data voltage line 155. For example, in some embodiments, the test voltage may be a black data voltage VGH. In some embodiments, the sub-pixels (R, G, B) may also be voltages that cause the sub-pixels (R, G, B) to display the lowest gray level. The test voltage may be cyclic. Figure 2The crack sensing line CDL is connected to the first fan-out line FOL1 to the fourth fan-out line FOL4. At this time, when the crack sensing line CDL is not damaged, the voltage applied to the first fan-out line FOL1 to the fourth fan-out line FOL4 will be substantially the same as the test voltage. For example, when the test voltage is the black data voltage VGH, the sub-pixels SP connected to the first fan-out line FOL1 to the fourth fan-out line FOL4 can display black. When the crack sensing line CDL is damaged, the resistance of the crack sensing line CDL increases, and the voltage that circulates the crack sensing line CDL and is applied to the first fan-out line FOL1 to the fourth fan-out line FOL4 will be a voltage smaller than the test voltage. For example, when the test voltage is the black data voltage VGH, a bright line can be identified in the sub-pixels SP connected to the first fan-out line FOL1 to the fourth fan-out line FOL4. Such a bright line can be used to easily determine whether a crack of the display panel 100 has occurred.

[0209] Thus, according to this embodiment, the defect inspection of the fan-out line FOL and the crack inspection of the display panel 100 can be performed by one inspection unit 150. Therefore, it is not necessary to separately configure circuit units for defect inspection of the fan-out line FOL and crack inspection of the display panel 100, so the invalid area of ​​the display device 10 can be effectively reduced.

[0210] Fig.14 is a diagram showing a circuit structure of a display device according to another embodiment, Fig.15 as well as Fig.16 is a timing diagram for explaining a fan-out line check in a display device according to another embodiment, Fig.17 is a timing chart for explaining crack inspection in a display device according to another embodiment. Figures 14 to 17 Examples and Figures 10 to 13 The difference between the embodiment of the present invention is that the seventh control line of the lighting circuit unit 170_1 is composed of the seventh control line 175a and the seventh control line 175b. Figures 10 to 13 The description of the embodiments is repeated, and the differences are mainly described.

[0211] Reference Figures 14 to 17 In some embodiments, the lighting circuit portion 170_1 may include a fifth control line 171, a sixth control line 173, a seventh control line 175a, a seventh control line 175b, a first lighting check signal line 177, a second lighting check signal line 178, a third lighting check signal line 179, and a switch. The fifth control line 171, the sixth control line 173, the seventh control line 175a, the seventh control line 175b, the first lighting check signal line 177, the second lighting check signal line 178, and the third lighting check signal line 179 may extend in the first direction (X-axis direction) and be spaced apart from each other in the second direction (Y-axis direction).

[0212] The switches of the lighting circuit unit 170_1 may include: a 13th switch SW31 and a 14th switch SW32 connected to the 1st data line DL1; a 15th switch SW33 connected to the 2nd data line DL2; a 16th switch SW34 and a 17th switch SW35 connected to the 3rd data line DL3; an 18th switch SW36 connected to the 4th data line DL4; a 19th switch SW37 and a 20th switch SW38 connected to the 5th data line DL5; a 21st switch SW39 connected to the 6th data line DL6; a 22nd switch SW40 and a 23rd switch SW41 connected to the 7th data line DL7; and a 24th switch SW42 connected to the 8th data line DL8.

[0213] The connection structure of the 13th switch SW31, the 14th switch SW32, the 16th switch SW34, the 17th switch SW35, the 19th switch SW37, the 20th switch SW38, the 22nd switch SW40, and the 23rd switch SW41 is the same as Fig.10 The embodiments are the same as those of the present invention, so repeated description is omitted.

[0214] The 15th switch SW33 may have a gate connected to the 7a control line 175a supplying the 3_1st lighting inspection control signal TEST_GATE_G1, a first terminal connected to the 3rd lighting inspection signal line 179 supplying the 3rd lighting inspection signal DC_G, and a second terminal connected to the 2nd data line DL2. The 15th switch SW33 may be turned on by the 3_1st lighting inspection control signal TEST_GATE_G1 to connect the 3rd lighting inspection signal line 179 and the 2nd data line DL2.

[0215] The 18th switch SW36 may have a gate connected to the 7a control line 175a supplying the 3_1st lighting inspection control signal TEST_GATE_G1, a first terminal connected to the 3rd lighting inspection signal line 179 supplying the 3rd lighting inspection signal DC_G, and a second terminal connected to the 4th data line DL4. The 18th switch SW36 may be turned on by the 3_1st lighting inspection control signal TEST_GATE_G1 to connect the 3rd lighting inspection signal line 179 and the 4th data line DL4.

[0216] The 21st switch SW39 may have a gate connected to the 7b control line 175b supplying the 3_2nd lighting inspection control signal TEST_GATE_G2, a first terminal connected to the 3rd lighting inspection signal line 179 supplying the 3rd lighting inspection signal DC_G, and a second terminal connected to the 6th data line DL6. The 21st switch SW39 may be turned on by the 3_2nd lighting inspection control signal TEST_GATE_G2 to connect the 3rd lighting inspection signal line 179 and the 6th data line DL6.

[0217] The 24th switch SW42 may have a gate connected to the 7b control line 175b supplying the 3_2nd lighting inspection control signal TEST_GATE_G2, a first terminal connected to the 3rd lighting inspection signal line 179 supplying the 3rd lighting inspection signal DC_G, and a second terminal connected to the 8th data line DL8. The 24th switch SW42 may be turned on by the 3_2nd lighting inspection control signal TEST_GATE_G2 to connect the 3rd lighting inspection signal line 179 and the 8th data line DL8.

[0218] Thus, the 15th switch SW33 and the 18th switch SW36 may be turned on by the 3_1st lighting inspection control signal TEST_GATE_G1, and the 21st switch SW39 and the 24th switch SW42 may be turned on by the 3_2nd lighting inspection control signal TEST_GATE_G2.

[0219] Will Fig.14 , Fig.15 as well as Fig.16 The inspection of the fan-out lines FOL will be described with reference to the above. Failure detection between adjacent fan-out lines ( FOL1 and FOL3 , FOL2 and FOL4 , etc.) on the same layer can be performed by the inspection unit 150 .

[0220] The lighting circuit section 170_1 may be activated during the inspection period of the fan-out line FOL. For example, the 3_1st lighting inspection control signal TEST_GATE_G1 and the 3_2nd lighting inspection control signal TEST_GATE_G2 of low level may be applied to the 7ath control line 175a and the 7bth control line 175b. Fig.15 The 3_2nd lighting inspection control signal TEST_GATE_G2 of low level is applied to the gates of the 21st switch SW39 and the 24th switch SW42, and the 21st switch SW39 and the 24th switch SW42 are turned on. Thus, the 6th data line DL6 and the 8th data line DL8 can be connected to the 3rd lighting inspection signal line 179.

[0221] The third lighting inspection signal DC_G applied to the third lighting inspection signal line 179 may be a white data voltage, but is not limited thereto, and may be a data voltage of another grayscale distinguishable from the black data voltage.

[0222] The demultiplexing unit 160 may be activated during the inspection period of the fan-out line FOL. For example, the low-level first demultiplexing control signal CLA and the second demultiplexing control signal CLB are applied to the gates of the fifth switch SW21 to the twelfth switch SW28, and the fifth switch SW21 to the twelfth switch SW28 are turned on.

[0223] The inspection unit 150 may be activated during the inspection period of the fan-out line FOL. For example, a low-level first inspection control signal MCD_GATE1 is applied to the gates of the first switch SW11 and the second switch SW12, and the first switch SW11 and the second switch SW12 are turned on. Thus, the first fan-out line FOL1 and the second fan-out line FOL2 may be connected to the data voltage line 155.

[0224] Thus, the sub-pixel SP connected to the 1st data line DL1 and the 2nd data line DL2 connected to the 1st fan-out line FOL1 displays black, the sub-pixel SP connected to the 3rd data line DL3 and the 4th data line DL4 connected to the second fan-out line FOL2 displays black, the sub-pixel SP connected to the 5th data line DL5 and the 6th data line DL6 connected to the 3rd fan-out line FOL3 displays white, and the sub-pixel SP connected to the 7th data line DL7 and the 8th data line DL8 connected to the 4th fan-out line FOL4 displays white.

[0225] In addition, a white data voltage is applied to the sixth data line DL6 and the eighth data line DL8 by applying the third lighting inspection signal DC_G to the third lighting inspection signal line 179. Thus, when performing a defect inspection, the brightness of the sub-pixel SP connected to the sixth data line DL6 and the eighth data line DL8 can be adjusted. Thus, when the first fan-out line FOL1 and the third fan-out line FOL3 adjacent to each other in the same layer are short-circuited (Short), the dark line generated in the sub-pixel SP connected to the third fan-out line FOL3 can be easily distinguished, and when the second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer are short-circuited (Short), the dark line generated in the sub-pixel SP connected to the fourth fan-out line FOL4 can be easily distinguished.

[0226] Reference Fig.16 The low level 3_1 lighting inspection control signal TEST_GATE_G1 is applied to the gates of the 15th switch SW33 and the 18th switch SW36 , and the 15th switch SW33 and the 18th switch SW36 are turned on. Thus, the second data line DL2 and the fourth data line DL4 can be connected to the third lighting inspection signal line 179 .

[0227] The second check control signal MCD_GATE2 of low level is applied to the gates of the third switch SW13 and the fourth switch SW14 , turning on the third switch SW13 and the fourth switch SW14 , thereby connecting the third fan-out line FOL3 and the fourth fan-out line FOL4 to the data voltage line 155 .

[0228] Thus, the sub-pixel SP connected to the 1st data line DL1 and the 2nd data line DL2 connected to the 1st fan-out line FOL1 displays white, the sub-pixel SP connected to the 3rd data line DL3 and the 4th data line DL4 connected to the second fan-out line FOL2 displays white, the sub-pixel SP connected to the 5th data line DL5 and the 6th data line DL6 connected to the 3rd fan-out line FOL3 displays black, and the sub-pixel SP connected to the 7th data line DL7 and the 8th data line DL8 connected to the 4th fan-out line FOL4 displays black.

[0229] In addition, a white data voltage is applied to the second data line DL2 and the fourth data line DL4 by applying the third lighting inspection signal DC_G to the third lighting inspection signal line 179. Thus, when performing a defect inspection, the brightness of the sub-pixel SP connected to the second data line DL2 and the fourth data line DL4 can be adjusted. Thus, when the adjacent first fan-out line FOL1 and the third fan-out line FOL3 in the same layer are short-circuited (Short), the dark line generated in the sub-pixel SP connected to the first fan-out line FOL1 can be easily distinguished, and when the adjacent second fan-out line FOL2 and the fourth fan-out line FOL4 in the same layer are short-circuited (Short), the dark line generated in the sub-pixel SP connected to the second fan-out line FOL3 can be easily distinguished.

[0230] Reference Fig.17 During the crack inspection period, the lighting circuit unit 170_1 may be inactive. For example, the 3_1st lighting inspection control signal TEST_GATE_G1 and the 3_2nd lighting inspection control signal TEST_GATE_G2 of high level may be applied to the 7a control line 175a and the 7b control line 175b. The rest of the crack inspection contents are the same as Fig.13 The same, so repeated description is omitted.

[0231] Fig.18 is a diagram showing a circuit structure of a display device according to another embodiment, Fig.19 as well as Fig. 20 is a timing diagram for explaining a fan-out line check in a display device according to another embodiment, Fig.21 is a timing chart for explaining crack inspection in a display device according to another embodiment. Figures 18 to 21 Examples and Figures 10 to 13 The difference between the embodiments is that the demultiplexing unit ( Fig.10 160). Omit Figures 10 to 13 The description of the embodiments is repeated, and the differences are mainly described.

[0232] Reference Fig.18The inspection unit 150 and the lighting circuit unit 170 may be disposed between the sub-pixel SP and the wiring pads DP1, DP2, DP3, and DP4. For example, the inspection unit 150 may be disposed adjacent to the sub-pixel SP, and the lighting circuit unit 170 may be disposed between the inspection unit 150 and the wiring pads DP1, DP2, DP3, and DP4.

[0233] The connection relationship between the inspection unit 150 and the lighting circuit unit 170 is as follows: Fig.10 The same, so repeated description is omitted.

[0234] Fig.18 The embodiment omits Fig.10 The demultiplexing section ( Fig.10 '160'), the fan-out lines FOL1, FOL2, FOL3, FOL4 and the data lines DL1, DL2, DL3, DL4 are connected one to one. For example, the first fan-out line FOL1 connects the first wiring pad DP1 to the first data line DL1, the second fan-out line FOL2 connects the second wiring pad DP2 to the second data line DL2, the third fan-out line FOL3 connects the third wiring pad DP3 to the third data line DL3, and the fourth fan-out line FOL4 connects the fourth wiring pad DP4 to the fourth data line DL4.

[0235] Reference Fig.19 During the inspection of the fan-out line FOL, a low-level first inspection control signal MCD_GATE1 is applied to the gates of the first switch SW11 and the second switch SW12, the first switch SW11 and the second switch SW12 are turned on, and the black data voltage VGH is applied to the first fan-out line FOL1 and the second fan-out line FOL2.

[0236] During the inspection period of the fan-out line FOL, the second inspection control signal MCD_GATE2 of high level is applied to the gates of the third switch SW13 and the fourth switch SW14 , and the black data voltage VGH is not applied to the third fan-out line FOL3 and the fourth fan-out line FOL4 .

[0237] Thus, black is displayed in the sub-pixel SP connected to the first data line DL1 connected to the first fan-out line FOL1 and the sub-pixel SP connected to the second data line DL2 connected to the second fan-out line FOL2, and white is displayed in the sub-pixel SP connected to the third data line DL3 connected to the third fan-out line FOL3 and the sub-pixel SP connected to the fourth data line DL4 connected to the third fan-out line FOL3.

[0238] When the first fan-out line FOL1 and the third fan-out line FOL3 are short-circuited (Short), the sub-pixel SP connected to the third fan-out line FOL3 displays black or generates dark lines, so it is easy to determine whether the first fan-out line FOL1 and the third fan-out line FOL3 are short-circuited. When the first fan-out line FOL1 is open (Open), the sub-pixel SP connected to the first fan-out line FOL1 displays white, so it is easy to determine whether the first fan-out line FOL1 is open.

[0239] When the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited (Short), the sub-pixel SP connected to the fourth fan-out line FOL4 displays black or generates a dark line, so it is easy to determine whether the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited. When the second fan-out line FOL2 is open (Open), the sub-pixel SP connected to the second fan-out line FOL2 displays white, so it is easy to determine whether the second fan-out line FOL2 is open.

[0240] Reference Fig. 20 During the inspection of the fan-out line FOL, the low-level second inspection control signal MCD_GATE2 is applied to the gates of the third switch SW13 and the fourth switch SW14, the third switch SW13 and the fourth switch SW14 are turned on, and the black data voltage VGH is applied to the third fan-out line FOL3 and the fourth fan-out line FOL4.

[0241] During the inspection period of the fan-out line FOL, the first inspection control signal MCD_GATE1 of a high level is applied to the gates of the first switch SW11 and the second switch SW12 , and the black data voltage VGH is not applied to the first fan-out line FOL1 and the second fan-out line FOL2 .

[0242] Thus, white is displayed in the sub-pixel SP connected to the first data line DL1 connected to the first fan-out line FOL1 and the sub-pixel SP connected to the second data line DL2 connected to the second fan-out line FOL2, and black is displayed in the sub-pixel SP connected to the third data line DL3 connected to the third fan-out line FOL3 and the sub-pixel SP connected to the fourth data line DL4 connected to the fourth fan-out line FOL4.

[0243] When the first fan-out line FOL1 and the third fan-out line FOL3 are short-circuited (Short), the sub-pixel SP connected to the first fan-out line FOL1 displays black or generates dark lines, so it is easy to determine whether the first fan-out line FOL1 and the third fan-out line FOL3 are short-circuited. When the third fan-out line FOL3 is open (Open), the sub-pixel SP connected to the third fan-out line FOL1 displays white, so it is easy to determine whether the third fan-out line FOL3 is open.

[0244] When the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited (Short), the sub-pixel SP connected to the second fan-out line FOL2 displays black or generates dark lines, so it is easy to determine whether the second fan-out line FOL2 and the fourth fan-out line FOL4 are short-circuited. When the fourth fan-out line FOL2 is open (Open), the sub-pixel SP connected to the fourth fan-out line FOL4 displays white, so it is easy to determine whether the fourth fan-out line FOL2 is open.

[0245] Reference Fig.21 During the crack inspection, the lighting circuit unit 170 may be inactive. For example, a high level lighting inspection control signal TEST_GATE_R / G / B and a lighting inspection signal DC_R / G / B may be applied to the lighting circuit unit. Fig.10 Except for the point where "160" is omitted, the contents of crack inspection are the same as Fig.13 The same, so repeated description is omitted.

[0246] Fig. 22 is a diagram showing a circuit structure of a display device according to another embodiment, Fig.23 as well as Fig.24 is a timing diagram for explaining a fan-out line check in a display device according to another embodiment, Fig.25 is a timing chart for explaining crack inspection in a display device according to another embodiment. Figure 22 to Figure 25 Examples and Figures 18 to 21 The difference between the embodiment of FIG. 1 and FIG. 2 is that the seventh control line of the lighting circuit unit 170_1 is composed of the seventh control line 175a and the seventh control line 175b. Figures 18 to 21 The description of the embodiments is repeated, and the differences are mainly described.

[0247] Reference Figure 22 to Figure 24 In some embodiments, the lighting circuit portion 170_1 may include a fifth control line 171, a sixth control line 173, a seventh control line 175a, a seventh control line 175b, a first lighting check signal line 177, a second lighting check signal line 178, a third lighting check signal line 179, and a switch. The fifth control line 171, the sixth control line 173, the seventh control line 175a, the seventh control line 175b, the first lighting check signal line 177, the second lighting check signal line 178, and the third lighting check signal line 179 may extend in the first direction (X-axis direction) and be spaced apart from each other in the second direction (Y-axis direction).

[0248] The switches of the lighting circuit unit 170_1 may include: a 13th switch SW31 and a 14th switch SW32 connected to the 1st data line DL1; a 15th switch SW33 connected to the 2nd data line DL2; a 16th switch SW34 and a 17th switch SW35 connected to the 3rd data line DL3; and an 18th switch SW36 connected to the 4th data line DL4.

[0249] The connection structure of the 13th switch SW31, the 14th switch SW32, the 16th switch SW34, and the 17th switch SW35 is the same as Fig.10 The embodiments are the same as those of the present invention, so repeated description is omitted.

[0250] The 15th switch SW33 may have a gate connected to the 7a control line 175a supplying the 3_1st lighting inspection control signal TEST_GATE_G1, a first terminal connected to the 3rd lighting inspection signal line 179 supplying the 3rd lighting inspection signal DC_G, and a second terminal connected to the 2nd data line DL2. The 15th switch SW33 may be turned on by the 3_1st lighting inspection control signal TEST_GATE_G1 to connect the 3rd lighting inspection signal line 179 and the 2nd data line DL2.

[0251] The 18th switch SW36 may have a gate connected to the 7b control line 175b supplying the 3_2 lighting inspection control signal TEST_GATE_G2, a first terminal connected to the 3rd lighting inspection signal line 179 supplying the 3rd lighting inspection signal DC_G, and a second terminal connected to the 4th data line DL4. The 18th switch SW36 may be turned on by the 3_2 lighting inspection control signal TEST_GATE_G2 to connect the 3rd lighting inspection signal line 179 and the 4th data line DL4.

[0252] Thus, the 15th switch SW33 may be turned on by the 3_1st lighting inspection control signal TEST_GATE_G1, and the 18th switch SW36 may be turned on by the 3_2nd lighting inspection control signal TEST_GATE_G2.

[0253] Will Fig. 22 , Fig.23 as well as Fig.24 The inspection of the fan-out lines FOL will be described with reference to the above. Failure detection between adjacent fan-out lines ( FOL1 and FOL3 , FOL2 and FOL4 , etc.) on the same layer can be performed by the inspection unit 150 .

[0254] The lighting circuit portion 170_1 may be activated during the inspection period of the fan-out line FOL. For example, the 3_1st lighting inspection control signal TEST_GATE_G1 and the 3_2nd lighting inspection control signal TEST_GATE_G2 of a low level may be applied to the 7ath control line 175a and the 7bth control line 175b.

[0255] Reference Fig.23 During the inspection period of the fan-out line FOL, the 3_2nd lighting inspection control signal TEST_GATE_G2 of low level is applied to the gate of the 18th switch SW36, and the 18th switch SW36 is turned on. Thus, the 4th data line DL4 can be connected to the 3rd lighting inspection signal line 179.

[0256] The third lighting inspection signal DC_G applied to the third lighting inspection signal line 179 may be a white data voltage, but is not limited thereto, and may be a data voltage of another grayscale distinguishable from the black data voltage.

[0257] During the inspection period of the fan-out line FOL, a low-level first inspection control signal MCD_GATE1 is applied to the gates of the first switch SW11 and the second switch SW12, the first switch SW11 and the second switch SW12 are turned on, and the black data voltage VGH is applied to the first fan-out line FOL1 and the second fan-out line FOL2.

[0258] During the inspection period of the fan-out line FOL, the second inspection control signal MCD_GATE2 of high level is applied to the gates of the third switch SW13 and the fourth switch SW14 , and the black data voltage VGH is not applied to the third fan-out line FOL3 and the fourth fan-out line FOL4 .

[0259] Thus, black is displayed in the sub-pixel SP connected to the first data line DL1 connected to the first fan-out line FOL1 and the sub-pixel SP connected to the second data line DL2 connected to the second fan-out line FOL2, and white is displayed in the sub-pixel SP connected to the third data line DL3 connected to the third fan-out line FOL3 and the sub-pixel SP connected to the fourth data line DL4 connected to the fourth fan-out line FOL4.

[0260] In addition, a white data voltage is applied to the fourth data line DL4 by the third lighting inspection signal DC_G applied to the third lighting inspection signal line 179. Thus, when performing a defect inspection, the brightness of the sub-pixel SP connected to the fourth data line DL4 can be adjusted. When the second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer are short-circuited, it is easier to distinguish the dark line generated in the sub-pixel SP connected to the fourth fan-out line FOL4.

[0261] Reference Fig.24The 3_1st lighting inspection control signal TEST_GATE_G1 of low level is applied to the gate of the 15th switch SW33, and the 15th switch SW33 is turned on. Thus, the second data line DL2 can be connected to the third lighting inspection signal line 179.

[0262] During the inspection period of the fan-out line FOL, the low-level second inspection control signal MCD_GATE2 is applied to the gates of the third switch SW13 and the fourth switch SW14, the third switch SW13 and the fourth switch SW14 are turned on, and the black data voltage VGH is applied to the third fan-out line FOL3 and the fourth fan-out line FOL4.

[0263] During the inspection period of the fan-out line FOL, the first inspection control signal MCD_GATE1 of a high level is applied to the gates of the first switch SW11 and the second switch SW12 , and the black data voltage VGH is not applied to the first fan-out line FOL1 and the second fan-out line FOL2 .

[0264] Thus, white is displayed in the sub-pixel SP connected to the first data line DL1 connected to the first fan-out line FOL1 and the sub-pixel SP connected to the second data line DL2 connected to the second fan-out line FOL2, and black is displayed in the sub-pixel SP connected to the third data line DL3 connected to the third fan-out line FOL3 and the sub-pixel SP connected to the fourth data line DL4 connected to the fourth fan-out line FOL4.

[0265] In addition, a white data voltage is applied to the second data line DL2 by the third lighting inspection signal DC_G applied to the third lighting inspection signal line 179. Thus, when performing a defect inspection, the brightness of the sub-pixel SP connected to the second data line DL2 can be adjusted. Thus, when the second fan-out line FOL2 and the fourth fan-out line FOL4 adjacent to each other in the same layer are short-circuited (Short), the dark line generated in the sub-pixel SP connected to the second fan-out line FOL2 can be more easily identified.

[0266] Reference Fig.25 During the crack inspection period, the lighting circuit unit 170_1 may be inactive. For example, the 3_1st lighting inspection control signal TEST_GATE_G1 and the 3_2nd lighting inspection control signal TEST_GATE_G2 of high level may be applied to the 7a control line 175a and the 7b control line 175b. The rest of the crack inspection contents are the same as Fig.13 The same, so repeated description is omitted.

[0267] Fig.26 is a diagram showing a circuit structure of a display device according to another embodiment, Fig. 27 as well as Fig.28is a timing diagram for explaining a fan-out line check in a display device according to another embodiment, Fig.29 is a timing chart for explaining crack inspection in a display device according to another embodiment. Figure 26 to Figure 29 Examples and Figures 10 to 13 The difference between the embodiment of FIG. 1 and FIG. 2 is that the sub-pixels are arranged in a stripe form and the lighting circuit section 170_2 is composed of a lighting inspection control line TGL. Figures 10 to 13 The description of the embodiments is repeated, and the differences are mainly described.

[0268] Reference Fig.26 In some embodiments, the sub-pixel SP may include a red sub-pixel R emitting red light, a blue sub-pixel B emitting blue light, and a green sub-pixel G emitting green light. The red sub-pixel R, the blue sub-pixel B, and the green sub-pixel G may be in the form of strips arranged in different columns. For example, the red sub-pixel R may be arranged in the first column, the green sub-pixel G may be arranged in the second column, and the blue sub-pixel B may be arranged in the third column, and the first to third columns may be repeated in the first direction (X-axis direction). A data line DL is arranged in each column.

[0269] In some embodiments, the first data line DL1 may be connected to the first column where red sub-pixels R are arranged, the second data line DL2 may be connected to the second column where green sub-pixels G are arranged, the third data line DL3 may be connected to the third column where blue sub-pixels B are arranged, the fourth data line DL4 may be connected to the fourth column where red sub-pixels R are arranged, the fifth data line DL5 may be connected to the fifth column where green sub-pixels G are arranged, the sixth data line DL6 may be connected to the sixth column where blue sub-pixels B are arranged, the seventh data line DL7 may be connected to the seventh column where red sub-pixels R are arranged, and the eighth data line DL8 may be connected to the eighth column where green sub-pixels G are arranged.

[0270] In the embodiment of the present disclosure, the sub-pixel SP is described as being composed of a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G. However, the sub-pixel SP may also include colors other than red, green, and blue.

[0271] In some embodiments, the lighting circuit unit 170_2 may include a lighting check control line TGL, a first lighting check signal line 177, a second lighting check signal line 178, a third lighting check signal line 179, and a switch. The lighting check control line TGL, the first lighting check signal line 177, the second lighting check signal line 178, and the third lighting check signal line 179 may extend in the first direction (X-axis direction) and be spaced apart from each other in the second direction (Y-axis direction).

[0272] The switches of the lighting circuit unit 170_2 may include: a 13th switch SW31 connected to the 1st data line DL1; a 14th switch SW32 connected to the 2nd data line DL2; a 15th switch SW33 connected to the 3rd data line DL3; a 16th switch SW34 connected to the 4th data line DL4; a 17th switch SW35 connected to the 5th data line DL5; an 18th switch SW36 connected to the 6th data line DL6; a 19th switch SW37 connected to the 7th data line DL7; and a 20th switch SW28 connected to the 8th data line DL8.

[0273] Specifically, the 13th switch SW31 may have a gate connected to the lighting check control line TGL supplying the lighting check control signal TEST_GATE, a first terminal connected to the first lighting check signal line 177 supplying the first lighting check signal DC_R, and a second terminal connected to the first data line DL1. The 13th switch SW31 may be turned on by the lighting check control signal TEST_GATE to connect the first lighting check signal line 177 and the first data line DL1.

[0274] The 14th switch SW32 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the third lighting inspection signal line 179 supplying the third lighting inspection signal DC_G, and a second terminal connected to the second data line DL2. The 14th switch SW32 may be turned on by the lighting inspection control signal TEST_GATE to connect the third lighting inspection signal line 179 and the second data line DL2.

[0275] The 15th switch SW33 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the second lighting inspection signal line 178 supplying the second lighting inspection signal DC_B, and a second terminal connected to the third data line DL3. The 15th switch SW33 may be turned on by the lighting inspection control signal TEST_GATE to connect the second lighting inspection signal line 178 and the third data line DL3.

[0276] The 16th switch SW34 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the first lighting inspection signal line 177 supplying the first lighting inspection signal DC_R, and a second terminal connected to the fourth data line DL4. The 16th switch SW34 may be turned on by the lighting inspection control signal TEST_GATE to connect the first lighting inspection signal line 177 and the fourth data line DL4.

[0277] The 17th switch SW35 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the third lighting inspection signal line 179 supplying the third lighting inspection signal DC_G, and a second terminal connected to the fifth data line DL5. The 17th switch SW35 may be turned on by the lighting inspection control signal TEST_GATE to connect the third lighting inspection signal line 179 and the fifth data line DL5.

[0278] The 18th switch SW36 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the second lighting inspection signal line 178 supplying the second lighting inspection signal DC_B, and a second terminal connected to the sixth data line DL6. The 18th switch SW36 may be turned on by the lighting inspection control signal TEST_GATE to connect the second lighting inspection signal line 178 and the sixth data line DL6.

[0279] The 19th switch SW37 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the first lighting inspection signal line 177 supplying the first lighting inspection signal DC_R, and a second terminal connected to the seventh data line DL7. The 19th switch SW37 may be turned on by the lighting inspection control signal TEST_GATE to connect the first lighting inspection signal line 177 and the seventh data line DL7.

[0280] The 20th switch SW38 may have a gate connected to the lighting inspection control line TGL supplying the lighting inspection control signal TEST_GATE, a first terminal connected to the third lighting inspection signal line 179 supplying the third lighting inspection signal DC_G, and a second terminal connected to the eighth data line DL8. The 20th switch SW38 may be turned on by the lighting inspection control signal TEST_GATE to connect the third lighting inspection signal line 179 and the eighth data line DL8.

[0281] In this way, when the sub-pixels SP are arranged in a stripe form, there is an advantage that the structure of the lighting inspection circuit unit 170_2 is simplified. Fig.10 The same, so repeated description is omitted.

[0282] Reference Figure 27 to Figure 29 , the lighting circuit unit 170_2 may be inactive during the inspection of the fan-out line FOL and the crack inspection period. For example, the lighting inspection control signal TEST_GATE and the lighting inspection signal DC_R / G / B at a high level may be applied to the lighting circuit unit 170_2. The contents of the inspection of the fan-out line FOL and the crack inspection are similar to those of Figures 11 to 13 The same, so repeated description is omitted.

[0283] Fig.30 is a diagram showing a circuit structure of a display device according to another embodiment, Fig.31 as well as Fig.32 is a timing diagram for explaining a fan-out line check in a display device according to another embodiment, Fig.33 is a timing chart for explaining crack inspection in a display device according to another embodiment. Figure 30 to Figure 33 Examples and Figure 26 to Figure 29 The difference between the embodiments is that the demultiplexing unit ( Fig.26 160). Omit Figure 26 to Figure 29 The description of the embodiments is repeated, and the differences are mainly described.

[0284] Reference Fig.30 The inspection unit 150 and the lighting circuit unit 170_2 may be disposed between the sub-pixel SP and the wiring pads DP1, DP2, DP3, and DP4. For example, the inspection unit 150 may be disposed adjacent to the sub-pixel SP, and the lighting circuit unit 170_2 may be disposed between the inspection unit 150 and the wiring pads DP1, DP2, DP3, and DP4.

[0285] The connection relationship between the inspection unit 150 and the lighting circuit unit 170_2 is as follows: Fig.26 The same, so repeated description is omitted.

[0286] Fig.30 The embodiment omits Fig.26 The demultiplexing section ( Fig.26 160), the fan-out lines FOL, FOL2, FOL3, FOL4 and the data lines DL1, DL2, DL3, DL4 are connected one to one. For example, the first fan-out line FOL1 connects the first wiring pad DP1 to the first data line DL1, the second fan-out line FOL2 connects the second wiring pad DP2 to the second data line DL2, the third fan-out line FOL3 connects the third wiring pad DP3 to the third data line DL3, and the fourth fan-out line FOL4 connects the fourth wiring pad DP4 to the fourth data line DL4.

[0287] Reference Figure 31 to Figure 33 , the lighting circuit unit 170_2 may be inactive during the inspection of the fan-out line FOL and the crack inspection period. For example, the lighting inspection control signal TEST_GATE and the lighting inspection signal DC_R / G / B at a high level may be applied to the lighting circuit unit 170_2. The contents of the inspection of the fan-out line FOL and the crack inspection are similar to those of Figures 19 to 21 The same, so repeated description is omitted.

[0288] Thus, according to this embodiment, the defect inspection of the fan-out line FOL and the crack inspection of the display panel 100 can be performed by one inspection unit 150. Therefore, it is not necessary to separately configure circuit units for defect inspection of the fan-out line FOL and crack inspection of the display panel 100, so the invalid area of ​​the display device 10 can be effectively reduced.

[0289] The embodiments of the present disclosure are described above with reference to the attached drawings, but it can be understood that a person with general knowledge in the technical field to which the present disclosure belongs can implement it in other specific forms without changing the technical concept or essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are illustrative in all aspects and not restrictive.

Claims

1. A display device, wherein: include: The sub-pixels are disposed in the display area and arranged along the first column, the second column, the third column, the fourth column, the fifth column, the sixth column, the seventh column, and the eighth column; The first wiring pad, the second wiring pad, the third wiring pad and the fourth wiring pad are arranged in a non-display area and arranged on one side of the display area, and the non-display area is a peripheral area of ​​the display area; A first fan-out line, a second fan-out line, a third fan-out line, and a fourth fan-out line connecting sub-pixels arranged along the first column to the eighth column and the first wiring pad to the fourth wiring pad; and an inspection unit disposed between the first wiring pad to the fourth wiring pad and the display area and electrically connected to the first fan-out line to the fourth fan-out line, The inspection unit is configured to apply a test voltage to the first fan-out line to the fourth fan-out line to inspect the first fan-out line to the fourth fan-out line for short circuit and disconnection. The inspection unit includes: a first switch, a second switch, a third switch, and a fourth switch; a first control line, which supplies a first inspection control signal to each gate of the first switch and the second switch; a second control line, which supplies a second inspection control signal to each gate of the third switch and the fourth switch; and a data voltage line, which supplies a test voltage to each first terminal of the first switch to the fourth switch. The second terminal of the first switch is connected to the first wiring pad and the first fan-out line. The second terminal of the second switch is connected to the second wiring pad and the second fan-out line. The second terminal of the third switch is connected to the third wiring pad and the third fan-out line. The second terminal of the fourth switch is connected to the fourth wiring pad and the fourth fan-out line.

2. The display device according to claim 1, wherein: The first fan-out line and the third fan-out line are arranged in the same layer, the second fan-out line and the fourth fan-out line are arranged in the same layer, and the first fan-out line and the third fan-out line and the second fan-out line and the fourth fan-out line are arranged in different layers.

3. The display device according to claim 1, wherein: The display device further includes: a first data line connected to the sub-pixels arranged along the first column; a second data line connected to the sub-pixels arranged along the second column; a third data line connected to the sub-pixels arranged along the third column; a fourth data line connected to the sub-pixels arranged along the fourth column; a fifth data line connected to the sub-pixels arranged along the fifth column; a sixth data line connected to the sub-pixels arranged along the sixth column; a seventh data line connected to the sub-pixels arranged along the seventh column; and an eighth data line connected to the sub-pixels arranged along the eighth column. The display device further includes: a demultiplexing unit, which is arranged in the non-display area and located between the display area and the inspection unit. The first data line and the second data line are connected to the first fan-out line through the demultiplexing part, the third data line and the fourth data line are connected to the second fan-out line through the demultiplexing part, the fifth data line and the sixth data line are connected to the third fan-out line through the demultiplexing part, and the seventh data line and the eighth data line are connected to the fourth fan-out line through the demultiplexing part.

4. The display device according to claim 3, wherein: The demultiplexing unit includes: a 5th switch, a 6th switch, a 7th switch, an 8th switch, a 9th switch, a 10th switch, an 11th switch and a 12th switch; a 3rd control line, supplying a 1st demultiplexing control signal to respective gates of the 5th switch, the 7th switch, the 9th switch and the 11th switch; and a 4th control line, supplying a 2nd demultiplexing control signal to respective gates of the 6th switch, the 8th switch, the 10th switch and the 12th switch.

5. The display device according to claim 4, wherein: The first terminals of the fifth switch and the sixth switch are connected to the first fan-out line, the first terminals of the seventh switch and the eighth switch are connected to the second fan-out line, the first terminals of the ninth switch and the tenth switch are connected to the third fan-out line, and the first terminals of the eleventh switch and the twelfth switch are connected to the fourth fan-out line.

6. The display device according to claim 5, wherein: The second terminal of the fifth switch is connected to the first data line, the second terminal of the sixth switch is connected to the second data line, the second terminal of the seventh switch is connected to the third data line, the second terminal of the eighth switch is connected to the fourth data line, the second terminal of the ninth switch is connected to the fifth data line, the second terminal of the tenth switch is connected to the sixth data line, the second terminal of the eleventh switch is connected to the seventh data line, and the second terminal of the twelfth switch is connected to the eighth data line.

7. The display device according to claim 6, wherein: The display device further includes a lighting circuit unit disposed between the display area and the demultiplexing unit.

8. The display device according to claim 7, wherein: The lighting circuit unit further includes a lighting inspection signal line that supplies a white data voltage to the second data line, the fourth data line, the sixth data line, and the eighth data line.

9. The display device according to claim 1, wherein: The test voltage is a black data voltage.

10. The display device according to claim 1, wherein: The sub-pixel comprises: The red sub-pixels and the blue sub-pixels are alternately arranged in the first column, the third column, the fifth column, and the seventh column; and Green sub-pixels are arranged in the second column between the first column and the third column, in the fourth column between the third column and the fifth column, in the sixth column between the fifth column and the seventh column, and in the eighth column arranged outside the seventh column, In the third column and the seventh column, the red sub-pixels and the blue sub-pixels are alternately arranged in an order opposite to that in the first column and the fifth column.

11. The display device according to claim 1, wherein: The first switch to the fourth switch are constituted by transistors, the gate is a gate electrode, the first terminal is a drain electrode, and the second terminal is a source electrode.

12. A display device, wherein: include: Sub-pixels are arranged in a display area; A display driving circuit is arranged in a non-display area and is located at the lower side of the display area, wherein the non-display area is a peripheral area of ​​the display area; A crack sensing line, disposed in the non-display area; A fan-out line connecting the sub-pixel and the display driving circuit; as well as an inspection unit, which is arranged between the display area and the display driving circuit, is disposed adjacent to the display driving circuit, and is electrically connected to the fan-out line through the crack sensing line, The inspection section is configured to apply a test voltage to the fan-out line to inspect a short circuit and a disconnection of the fan-out line, and to apply a test voltage to the crack sensing line to inspect a damage of the crack sensing line.

13. The display device according to claim 12, wherein: The display device further includes: a wiring pad electrically connected to the fan-out line, The display driving circuit includes a bump and a driving integrated circuit, and the driving integrated circuit is connected to the wiring pad through the bump.

14. The display device according to claim 13, wherein: The display device further comprises: a display pad, which is arranged outside the display driving circuit and is attached with a circuit board.

15. The display device according to claim 14, wherein: The display device further includes: a lighting circuit unit, which is arranged between the display area and the inspection unit and is disposed adjacent to the display area.

16. The display device according to claim 15, wherein: The display device further includes: a first data line, a second data line, a third data line and a fourth data line connected to the sub-pixel, The fan-out lines include a first fan-out line, a second fan-out line, a third fan-out line and a fourth fan-out line, the first data line is connected to the first fan-out line, the second data line is connected to the second fan-out line, the third data line is connected to the third fan-out line, and the fourth data line is connected to the fourth fan-out line.

17. The display device according to claim 16, wherein: The sub-pixels are arranged along a plurality of columns in a stripe form, and sub-pixels of the same color are arranged in the same column.

18. A method for inspecting a display device, the display device comprising: Sub-pixels are arranged in a display area; A display driving circuit is arranged in a non-display area and is located at the lower side of the display area, wherein the non-display area is a peripheral area of ​​the display area; A crack sensing line, disposed in the non-display area; A fan-out line connecting the sub-pixel and the display driving circuit; and an inspection unit, which is arranged between the display area and the display driving circuit, is disposed adjacent to the display driving circuit, and is electrically connected to the fan-out line through the crack sensing line, wherein: The inspection unit comprises: The step of applying a test voltage to the fan-out line to check for short circuit and disconnection of the fan-out line; and The step of applying a test voltage to the crack sensing line to check for damage of the crack sensing line.

Images