Display panel and display device

Abstract

The present invention relates to a display panel and a display device. The display panel includes: a pixel region including a plurality of pixels; an open-short test region including a plurality of open-short test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to a plurality of pixels in response to the carry signal, wherein the plurality of stages are spaced apart from the pixel region by a first distance, and the dummy stage is spaced apart from the open-short test region by a second distance greater than the first distance.

Description

Technical Field

[0001] Aspects of some example embodiments generally relate to a display device. Background Art

[0002] When manufacturing a display panel such as an organic light emitting diode (OLED) display panel, an open-short test may be performed to detect whether a wiring such as a data line formed in the display panel is defective. An open-short test instrument may perform the open-short test by applying an open-short test signal to an open-short test pad of the display panel and by receiving the open-short test signal via a probe.

[0003] However, since the probes of the open-short test instrument may come into contact with the display panel, the display panel may be damaged by the probes of the open-short test instrument.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some example embodiments relate generally to a display device, and, for example, to a display panel including an open and short test area and a display device including the display panel.

[0006] Aspects of some example embodiments include a display panel capable of preventing or reducing damage during an open-short test.

[0007] Aspects of some example embodiments include a display device capable of preventing or reducing damage during an open-short test.

[0008] According to some example embodiments, a display panel includes: a pixel region in which a plurality of pixels are formed; an open-short test region in which a plurality of open-short test pads are formed; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal. The plurality of stages are spaced apart from the pixel region by a first distance, and the dummy stage is spaced apart from the open-short test region by a second distance greater than the first distance.

[0009] According to some example embodiments, the second distance between the open-short test region and the dummy stage may be greater than or equal to a reference distance to prevent damage caused by an open-short test instrument.

[0010] According to some example embodiments, a width of the dummy stage may be narrower than a width of each of the plurality of stages.

[0011] According to some example embodiments, each of the plurality of stages may include: a first circuit portion configured to operate in response to a previous carry signal; and a first buffer portion controlled by the first circuit portion to output a corresponding scan signal of the plurality of scan signals. The dummy stage may include: a second circuit portion configured to operate in response to a scan start signal; and a second buffer portion controlled by the second circuit portion. A width of the second buffer portion of the dummy stage may be narrower than a width of the first buffer portion of each of the plurality of stages.

[0012] According to some example embodiments, a size of at least one transistor included in the second buffer part may be smaller than a size of at least one transistor included in the first buffer part.

[0013] According to some example embodiments, each of the first circuit portion and the second circuit portion may include: a control node charging block configured to charge an internal control node in response to a scan start signal or a previous carry signal; an inverter block configured to control an internal inversion control node based on a voltage of the internal control node; a control node holding block configured to hold the voltage of the internal control node; a carry block configured to generate a current carry signal in response to the voltage of the internal control node; and a control node discharge block configured to discharge the internal control node in response to a next carry signal. Each of the first buffer portion and the second buffer portion may include: a scan signal output block configured to generate a corresponding scan signal in response to the voltage of the internal control node. The size of the scan signal output block of the second buffer portion may be smaller than the size of the scan signal output block of the first buffer portion.

[0014] According to some example embodiments, the scan signal output block of the first buffer part may be coupled to the corresponding scan line and output the corresponding scan signal to the corresponding scan line, and the scan signal output block of the second buffer part may not be coupled to the scan line.

[0015] According to some example embodiments, each of the first circuit portion and the second circuit portion may further include: a sensing block configured to control the internal control node based on the sensing start signal and the sensing clock signal. Each of the first buffer portion and the second buffer portion may further include: a sensing signal output block configured to generate a corresponding sensing signal of the plurality of sensing signals in response to a voltage of the internal control node. The size of the sensing signal output block of the second buffer portion may be smaller than the size of the sensing signal output block of the first buffer portion.

[0016] According to some example embodiments, the sensing signal output block of the first buffer part may be coupled to the corresponding sensing control line and output the corresponding sensing signal to the corresponding sensing control line, and the sensing signal output block of the second buffer part may not be coupled to the sensing control line.

[0017] According to some example embodiments, each of the plurality of stages may include: a first circuit portion configured to operate in response to a previous carry signal; and a first buffer portion controlled by the first circuit portion to output a corresponding scan signal of a plurality of scan signals and a corresponding sense signal of a plurality of sense signals. The dummy stage may include: a second circuit portion configured to operate in response to a scan start signal; and a second buffer portion controlled by the second circuit portion. The width of the second circuit portion of the dummy stage may be narrower than the width of the first circuit portion of each of the plurality of stages, and the width of the second buffer portion of the dummy stage may be narrower than the width of the first buffer portion of each of the plurality of stages.

[0018] According to some example embodiments, the first circuit portion may include a sense block configured to control the internal control node based on the sense-on signal and the sense clock signal, and the second circuit portion may not include the sense block.

[0019] According to some example embodiments, a size of at least one transistor included in the second buffer part may be smaller than a size of at least one transistor included in the first buffer part.

[0020] According to some example embodiments, the first buffer part may include a sensing signal output block configured to generate a corresponding sensing signal in response to a voltage of an internal control node of the first circuit part, and the second circuit part may not include the sensing signal output block.

[0021] According to some example embodiments, the display panel may further include: a wiring formed on the dummy stage and the plurality of stages. The wiring may be spaced apart from the pixel region by a third distance, and may be spaced apart from the open-short test region by a fourth distance greater than the third distance.

[0022] According to some example embodiments, the wiring may include a first portion passing through the dummy stage and extending in a vertical direction, a second portion extending in a horizontal direction between the dummy stage and the plurality of stages, and a third portion passing through the plurality of stages and extending in a vertical direction.

[0023] According to some example embodiments, there is provided a display panel, comprising: a pixel region in which a plurality of pixels are formed; an open-short test region in which a plurality of open-short test pads are formed; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal. The dummy stage is spaced apart from an open-short test line, and a probe of an open-short test instrument moves along the open-short test line.

[0024] According to some example embodiments, the open and short test lines may extend in a horizontal direction, and the dummy stages may be spaced apart a distance from the open and short test lines in a vertical direction.

[0025] According to some example embodiments, a dummy stage may be formed outside an outer edge of the open-short test region.

[0026] According to some example embodiments, a width of the dummy stage may be narrower than a width of each of the plurality of stages.

[0027] According to some example embodiments, there is provided a display device including a display panel, the display panel including: a pixel region in which a plurality of pixels are formed; an open-short test region in which a plurality of open-short test pads are formed; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal; a data driver configured to output a data signal to the display panel; and a controller configured to control the data driver, the dummy stage, and the plurality of stages. The plurality of stages are spaced apart from the pixel region by a first distance, and the dummy stage is spaced apart from the open-short test region by a second distance greater than the first distance.

[0028] As described above, in the display panel and the display device according to some example embodiments, the plurality of stages may be spaced apart from the pixel region by a first distance, and the dummy stage may be spaced apart from the open-short test region by a second distance greater than the first distance. Thus, damage to the display panel that may otherwise occur during the open-short test may be prevented or reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 is a diagram illustrating a display device according to some example embodiments.

[0031] Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0032] Figure 3 is a diagram illustrating a portion of a display panel according to some example embodiments.

[0033] Figure 4 It is shown Figure 3 A circuit diagram of an example of a dummy stage or a normal stage included in a display panel of FIG.

[0034] Figure 5 It is shown Figure 3 A circuit diagram of another example of a dummy stage or a normal stage included in a display panel of FIG.

[0035] Figure 6 is a diagram illustrating a portion of a display panel according to some example embodiments.

[0036] Figure 7 It is shown Figure 6 A circuit diagram of an example of a dummy stage included in a display panel.

[0037] Figure 8 is a diagram illustrating a portion of a display panel according to some example embodiments.

[0038] Fig. 9 is a block diagram illustrating an example of an electronic device including a display device according to some example embodiments. DETAILED DESCRIPTION

[0039] Hereinafter, example embodiments are described more fully with reference to the accompanying drawings.Throughout the text, the same or similar reference numerals refer to the same or similar elements.

[0040] Figure 1 is a diagram illustrating a display device according to some example embodiments, and Figure 2 It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0041] refer to Figure 1 , the display device 100 according to some example embodiments may include a display panel 110, a data driver 160 outputting a data signal to the display panel 110, and a controller 180 controlling an operation of the display device 100. According to some example embodiments, the display panel 110 may include a pixel region 120 in which a plurality of pixels PX are arranged, open-short test regions 130 and 135 in which a plurality of open-short (OS) test pads are formed, and a scan driver 140 providing a plurality of scan signals and / or a plurality of sensing signals to the plurality of pixels PX.

[0042] In the pixel region 120 of the display panel 110, a plurality of data lines DL, a plurality of scan lines SSL, and a plurality of pixels PX may be formed. The plurality of pixels PX may be coupled to the plurality of data lines DL and the plurality of scan lines SSL. According to some example embodiments, in the pixel region 120, a plurality of sensing control lines SCL and a plurality of sensing lines SL may be further formed, and the plurality of pixels PX may be further coupled to the plurality of sensing control lines SCL and the plurality of sensing lines SL.

[0043] According to some example embodiments, the display panel 110 may be an organic light emitting diode display panel in which each pixel PX includes an organic light emitting diode (OLED). According to some example embodiments, the display panel 110 may be, but is not limited to, a QD-OLED display panel in which a light emitting layer of each pixel PX includes a quantum dot (QD) material. According to some example embodiments, the display panel 110 may be a liquid crystal display (LCD) panel or any other suitable display panel.

[0044] According to some example embodiments, Figure 2 As shown, each pixel PX may have a 3T1C structure including three transistors TSWS1, TSWS2, and TDR and a capacitor CST. For example, each pixel PX may include a storage capacitor CST, a first switching transistor TSWS1 that couples the data line DL to one electrode of the storage capacitor CST in response to a scan signal SS (e.g., applied to the gate electrode of the first switching transistor TSWS1), a second switching transistor TSWS2 that couples the sensing line SL to the other electrode of the storage capacitor CST in response to a sensing signal SENS (e.g., applied to the gate electrode of the second switching transistor TSWS2), a driving transistor TDR that generates a driving current based on a voltage stored in the storage capacitor CST (e.g., a difference between voltages applied to the data line DL and the sensing line SL), and an organic light emitting diode EL that emits light based on the driving current.

[0045] although Figure 2 An example of a pixel PX having a 3T1C structure is shown, but the pixel PX of the display device 100 according to some example embodiments is not limited to the 3T1C structure. For example, the pixel PX may have a Figure 2 The 3T1C structure of the present invention may be another 3T1C structure having a different connection relationship, or may have any structure including two or more transistors and one or more capacitors. In addition, according to some example embodiments, without departing from the spirit and scope of the embodiments of the present disclosure, there may be additional transistors, capacitors, and other electronic components included in the circuit structure of the pixel circuit.

[0046] In the open-short test areas 130 and 135 of the display panel 110, a plurality of open-short test pads may be formed, and an open-short test instrument applies an open-short test signal to the plurality of open-short test pads. The open-short test instrument may receive an open-short test signal of a plurality of open-short test pads and lines (e.g., data lines DL and / or sensing lines SL) that have moved through the pixel area 120 of the display panel 110 by using a probe of the open-short test instrument, and may detect an open-short defect of the line of the pixel area 120 based on the received open-short test signal. In order to receive the open-short test signal, the probe of the open-short test instrument may move through the open-short test areas 130 and 135 so that the probe may contact the corresponding data line DL and / or the corresponding sensing line SL. Here, the imaginary line along which the probe of the open-short test instrument moves may be referred to as an open-short test line OSTL. In some example embodiments, as Figure 1 As shown, two open and short test regions 130 and 135 may be respectively formed or located on (e.g., opposite or opposing) two sides (e.g., upper and lower sides) of the pixel region 120. In other example embodiments, one open and short test region 130 or 135 may be formed on one side (e.g., upper or lower side) of the pixel region 120.

[0047] The scan driver 140 may be formed on the display panel 110, and may sequentially provide a plurality of scan signals SS to a plurality of pixels PX through a plurality of scan lines SSL in response to a scan control signal received from the controller 180. In some example embodiments, the scan control signal may include, but is not limited to, a scan start signal SSP and a scan clock signal CLK. The scan driver 140 may include at least one dummy stage 141 and 142 for generating a carry signal based on the scan start signal SSP and the scan clock signal CLK, and a plurality of stages 144, 146, ..., 148 for sequentially providing a plurality of scan signals SS to a plurality of pixels PX based on the carry signal and the scan clock signal CLK. In some example embodiments, the scan driver 140 may further receive a sense on signal SON and a sense clock signal SCLK as scan control signals, and may provide a plurality of sense signals SENS to a plurality of pixels PX through a plurality of sense control lines SCL in response to the sense on signal SON and the sense clock signal SCLK.

[0048] In the display device 100 according to some example embodiments, the plurality of stages 144, 146, ..., 148 may be spaced apart from the pixel region 120 by a first distance D1, and the dummy stages 141 and 142 may be spaced apart from the open and short test regions 130 and 135 by a second distance D2 greater than the first distance D1, respectively. In some example embodiments, the second distance D2 between the open and short test region 130 and the dummy stage 141 and between the open and short test region 135 and the dummy stage 142 may be greater than or equal to a reference distance to prevent or reduce damage caused by an open and short test instrument. For example, in a conventional display device, a wiring of the display panel 110 (e.g., a wiring WR passing through the dummy stages 141 and 142) may be damaged due to contact of a probe of the open and short test instrument with the display panel 110.

[0049] However, in the display device 100 according to some example embodiments, the dummy stages 141 and 142 may be spaced apart from the open and short test regions 130 and 135, respectively, by a second distance D2 greater than a reference distance, thereby preventing or reducing damage caused by a probe of an open and short test instrument. For example, the reference distance may be, but is not limited to, about 500 μm, and the second distance D2 may be greater than about 500 μm.

[0050] In some example embodiments, the plurality of stages 144, 146, ..., 148 may be spaced apart from the pixel region 120 by a first distance D1, and the dummy stages 141 and 142 may be spaced apart from the open and short test regions 130 and 135 by a second distance D2, respectively, and the widths (e.g., horizontal widths) of the dummy stages 141 and 142 are narrower than the width of each of the plurality of stages 144, 146, ..., 148. Figure 1 As shown, each of the plurality of stages 144, 146, ..., 148 may be coupled to a corresponding scan line SSL, and the dummy stages 141 and 142 may not be coupled to the scan line SSL. The dummy stages 141 and 142 may not output a scan signal to the scan line SSL, and thus the size of at least one transistor for generating a scan signal in the dummy stages 141 and 142 may be smaller than the size of at least one transistor for generating a scan signal SS in each of the plurality of stages 144, 146, ..., 148. Therefore, since at least one transistor of the dummy stages 141 and 142 has a small size, the dummy stages 141 and 142 may have a smaller width than the width of each of the plurality of stages 144, 146, ..., 148. In addition, in some example embodiments, the plurality of stages 144, 146, ..., 148 may be further coupled to a corresponding sense control line SCL, and the dummy stages 141 and 142 may not be coupled to the sense control line SCL.

[0051] In some example embodiments, the display device 100 may further include a wiring WR formed on the dummy stages 141 and 142 and the plurality of stages 144, 146, . . . , 148. The wiring WR may be any wiring for providing a voltage or a signal. For example, the wiring WR may be, but is not limited to, a wiring for a low power supply voltage ELVSS, a wiring for a high power supply voltage ELVDD, a wiring for a low gate voltage VGL (see Figure 4 ) wiring, for high gate voltage VGH (see Figure 4 ) wiring, etc.

[0052] In the display device 100 according to some example embodiments, as Figure 1 As shown, while the wiring WR passes through the plurality of stages 144, 146, ..., 148, the wiring WR may be spaced apart from the pixel region 120 by a third distance, and while the wiring WR passes through the dummy stages 141 and 142 (or the regions of the dummy stages 141 and 142), the wiring WR may be spaced apart from the open and short test regions 130 and 135 by a fourth distance greater than the third distance. For example, the wiring WR may include a first portion extending in a vertical direction (e.g., a direction of the data line DL) through the dummy stages 141 and 142, a second portion extending in a horizontal direction (e.g., a direction of the scan line SSL) between the dummy stages 141 and 142 and the plurality of stages 144, 146, ..., 148, and a third portion extending in a vertical direction through the plurality of stages 144, 146, ..., 148. In this case, the third portion of the wiring WR may be spaced apart from the pixel region 120 by a third distance, and the first portion of the wiring WR may be spaced apart from the open and short test regions 130 and 135 by a fourth distance greater than the third distance. Therefore, the wiring WR can be spaced apart a greater distance from the open short test line OSTL which is an imaginary line along which the probe of the open short test instrument moves, thereby preventing or reducing instances of damaging the wiring WR which may otherwise be caused during the open short test.

[0053] In some example embodiments, Figure 1 As shown, the scan driver 140 may include at least one first dummy stage 141 located before the first stage 144 among the plurality of stages 144, 146, ..., 148 and at least one second dummy stage 142 located after the last stage 148 among the plurality of stages 144, 146, ..., 148. In addition, each of the first dummy stage 141 and the second dummy stage 142 may be one or more dummy stages. In other example embodiments, the scan driver 140 may include the first dummy stage 141 and may not include the second dummy stage 142. In other example embodiments, the scan driver 140 may include the second dummy stage 142 and may not include the first dummy stage 141.

[0054] The data driver 160 may output a data signal to a plurality of data lines DL based on a data control signal DCTRL, and output image data ODAT received from the controller 180. In some example embodiments, the data control signal DCTRL may include, but is not limited to, a horizontal start signal and a load signal. In addition, in some example embodiments, the display device 100 may further include a sensing driver that senses driving characteristics of a plurality of pixels PX, such as a threshold voltage of a driving transistor TDR of a plurality of pixels PX, through a plurality of sensing lines SL. According to some example embodiments, the sensing driver may be included in the data driver 160, or may be formed outside the data driver 160.

[0055] The controller 180 (e.g., a timing controller (TCON)) may control the data driver 160 and the scan driver 140 (i.e., the dummy stages 141 and 142 and the plurality of stages 144, 146, ..., 148) based on the input image data IDAT and the control signal CTRL received from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In some example embodiments, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data.

[0056] Furthermore, in some example embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock signal, etc. The controller 180 may control the operation of the data driver 160 by providing the data control signal DCTRL and the image data ODAT to the data driver 160, and may control the operation of the scan driver 140 by providing a scan control signal (e.g., a scan start signal SSP, a scan clock signal CLK, a sense on signal SON, and a sense clock signal SCLK) to the scan driver 140.

[0057] As described above, in the display device 100 according to some example embodiments, the plurality of stages 144, 146, ..., 148 may be spaced apart from the pixel region 120 by a first distance D1, and the dummy stages 141 and 142 may be spaced apart from the open-short test regions 130 and 135 by a second distance D2 greater than the first distance D1, respectively. In addition, the second distance D2 between the open-short test region 130 and the dummy stage 141 and between the open-short test region 135 and the dummy stage 142 may be greater than or equal to the reference distance to prevent or reduce damage caused by an open-short test instrument. Therefore, in the display device 100 according to some example embodiments, damage to the display panel 110 that may otherwise be caused during an open-short test may be prevented or reduced.

[0058] Figure 3is a diagram illustrating a portion of a display panel according to some example embodiments, Figure 4 It is shown Figure 3 A circuit diagram of an example of a dummy stage or a normal stage included in a display panel of Figure 5 It is shown Figure 3 A circuit diagram of another example of a dummy stage or a normal stage included in a display panel of FIG.

[0059] refer to Figure 3 , the display panel 110a according to some example embodiments may include a pixel region 120 in which a plurality of pixels are formed, an open-short test region 130 in which a plurality of open-short test pads OSTP are formed, at least one dummy stage 141a that generates a carry signal CR in response to a scan start signal SSP, and a plurality of stages 144a and 146a (or normal stages 144a and 146a) that sequentially provide a plurality of scan signals SS to the plurality of pixels in response to the carry signal CR.

[0060] In the display panel 110a, the plurality of stages 144a and 146a may be spaced apart from the pixel region 120 by a first distance, and the dummy stage 141a may be spaced apart from the open-short test region 130 by a second distance greater than the first distance. In some example embodiments, the second distance between the open-short test region 130 and the dummy stage 141a may be greater than or equal to a reference distance to prevent or reduce damage caused by an open-short test instrument. Figure 3 As shown, the plurality of levels 144a and 146a may be spaced apart from the pixel region 120 by a first distance, and the dummy level 141a may be spaced apart from the open and short test region 130 by a second distance, and a width (e.g., a horizontal width) of the dummy level 141a may be narrower than a width of each of the plurality of levels 144a and 146a.

[0061] Each of the plurality of stages 144a and 146a may include a first circuit portion CIRP1 operated in response to a previous carry signal (e.g., a carry signal CR generated by the dummy stage 141a with respect to the first stage 144a, or a carry signal CR generated by the first stage 144a with respect to the second stage 146a) and a first buffer portion BUFP1 controlled by the first circuit portion CIRP1 to output a corresponding scan signal SS. The dummy stage 141a may include a second circuit portion CIRP2 operated in response to a scan start signal SSP and a second buffer portion BUFP2 controlled by the second circuit portion CIRP2. In the display panel 110a according to some example embodiments, so that the dummy stage 141a may have a narrower width than that of each of the plurality of stages 144a and 146a, a width W2 of the second buffer portion BUFP2 of the dummy stage 141a may be narrower than a width W1 of the first buffer portion BUFP1 of each of the plurality of stages 144a and 146a. For example, so that the second buffer portion BUFP2 may have a width W2 narrower than the width W1 of the first buffer portion BUFP1, the second buffer portion BUFP2 may be implemented to include at least one transistor having a size smaller than that of at least one transistor included in the first buffer portion BUFP1.

[0062] In some example embodiments, Figure 4 As shown, each of the first circuit part CIRP1a of each stage 144a and 146a and the second circuit part CIRP2a of the dummy stage 141a may include a control node charging block QCB that charges the internal control node NQ in response to the scan start signal SSP or the previous carry signal PCR, an inverter block IB that controls the internal inversion control node NQB based on the voltage of the internal control node NQ, a control node holding block QHB that holds the voltage of the internal control node NQ, a carry block CRB that generates a current carry signal CCR in response to the voltage of the internal control node NQ, and a control node discharge block QDB that discharges the internal control node NQ in response to the next carry signal NCR. In addition, each of the first buffer part BUFP1a of each stage 144a and 146a and the second buffer part BUFP2a of the dummy stage 141a may include a scan signal output block SSOB that generates a corresponding scan signal SS in response to the voltage of the internal control node NQ.

[0063] For example, the control node charging block QCB may include a first transistor T1 that transmits a high gate voltage VGH to the internal control node NQ in response to the scan start signal SSP or the previous carry signal PCR. The inverter block IB may include second transistors T2-1 and T2-2 that transmit the first scan clock signal CLK1 to the internal inversion control node NQB in response to the voltage of the internal control node NQ, a third transistor T3 that transmits the high gate voltage VGH to the internal inversion control node NQB in response to the first scan clock signal CLK1, and a fourth transistor T4 that transmits the high gate voltage VGH to the internal inversion control node NQB in response to the voltage of the internal inversion control node NQB.

[0064] According to some example embodiments, Figure 4 As shown, the second transistors T2-1 and T2-2 can be implemented using two transistors T2-1 and T2-2 connected in series. The control node holding block QHB may include a fifth transistor T5 and a sixth transistor T6 that couple the internal control node NQ to the carry output node in response to the second scan clock signal CLK2 and the voltage of the internal inverting control node NQB. The carry block CRB may include a seventh transistor T7 that outputs the third scan clock signal CLK3 as a current carry signal CCR in response to the voltage of the internal control node NQ, an eighth transistor T8 that transmits the low gate voltage VGL to the carry output node in response to the voltage of the internal inverting control node NQB, and a first capacitor C1 coupled between the internal inverting control node NQB and the line of the low gate voltage VGL.

[0065] The control node discharge block QDB may include a ninth transistor T9 coupling the internal control node NQ to the carry output node in response to the next carry signal NCR. In addition, the scan signal output block SSOB may include a tenth transistor T10 outputting the second scan clock signal CLK2 as the scan signal SS in response to the voltage of the internal control node NQ, an eleventh transistor T11 transmitting the low gate voltage VGL to the scan output node in response to the voltage of the internal inversion control node NQB, and a second capacitor C2 coupled between the internal control node NQ and the scan output node.

[0066] In the display panel 110a according to some example embodiments, the size of the scan signal output block SSOB of the second buffer section BUFP2a may be smaller than the size of the scan signal output block SSOB of the first buffer section BUFP1a. In order to achieve the smaller size of the scan signal output block SSOB of the second buffer section BUFP2a, the tenth transistor T10 and the eleventh transistor T11 of the scan signal output block SSOB of the second buffer section BUFP2a may have a smaller size (e.g., channel width) than the tenth transistor T10 and the eleventh transistor T11 of the scan signal output block SSOB of the first buffer section BUFP1a.

[0067] In addition, if Figure 3 and Figure 4 As shown, the scan signal output block SSOB of the first buffer parts BUFP1 and BUFP1a may be coupled to the corresponding scan line SSL and may output the corresponding scan signal SS to the corresponding scan line SSL. However, the scan signal output block SSOB of the second buffer parts BUFP2 and BUFP2a may not be coupled to the scan line SSL.

[0068] Therefore, although the scan signal output block SSOB of the second buffer parts BUFP2 and BUFP2a includes the tenth transistor T10 and the eleventh transistor T11 having a small size, the dummy stage 141a including the second buffer parts BUFP2 and BUFP2a can operate normally. As described above, the second buffer parts BUFP2 and BUFP2a can have a width W2 narrower than the width W1 of the first buffer parts BUFP1 and BUFP1a, and thus damage to the display panel 110a that may otherwise occur during the open short circuit test can be prevented or reduced.

[0069] According to some example embodiments, Figure 5 As shown, Figure 4 Compared to the first circuit portion CIRP1a or the second circuit portion CIRP2a shown, each of the first circuit portion CIRP1b of each stage 144a and 146a and the second circuit portion CIRP2b of the dummy stage 141a may further include a sense block SENB that controls the internal control node NQ based on the sense start signal SON and the sense clock signal SCLK. Figure 4 Compared to the first buffer part BUFP1a or the second buffer part BUFP2a shown, each of the first buffer part BUFP1b of each stage 144a and 146a and the second buffer part BUFP2b of the dummy stage 141a may further include a sensing signal output block SENSOB that generates a corresponding sensing signal SENS in response to the voltage of the internal control node NQ.

[0070] For example, the sensing block SENB may include twelfth transistors T12-1 and T12-2 that transmit the next carry signal NCR to the sensing node NSEN in response to the sensing start signal SON, thirteenth transistors T13-1 and T13-2 that transmit the sensing clock signal SCLK to the internal control node NQ in response to the voltage of the sensing node NSEN, and a third capacitor C3 coupled between the line of the low gate voltage VGL and the sensing node NSEN.

[0071] According to some example embodiments, Figure 5 As shown, the twelfth transistor T12-1 and T12-2 can be implemented using two transistors T12-1 and T12-2 connected in series, and the thirteenth transistor T13-1 and T13-2 can be implemented using two transistors T13-1 and T13-2 connected in series. The sensing signal output block SENSOB may include a fourteenth transistor T14 that outputs a fourth scan clock signal CLK4 as a sensing signal SENS in response to a voltage of an internal control node NQ, a fifteenth transistor T15 that transmits a low gate voltage VGL to a sensing output node in response to a voltage of an internal inverting control node NQB, and a fourth capacitor C4 coupled between the internal control node NQ and the sensing output node.

[0072] In this case, the size of the sensing signal output block SENSOB of the second buffer part BUFP2b can be smaller than the size of the sensing signal output block SENSOB of the first buffer part BUFP1b. In order to achieve the smaller size of the sensing signal output block SENSOB of the second buffer part BUFP2b, the fourteenth transistor T14 and the fifteenth transistor T15 of the sensing signal output block SENSOB of the second buffer part BUFP2b can have a smaller size (e.g., channel width) than the fourteenth transistor T14 and the fifteenth transistor T15 of the sensing signal output block SENSOB of the first buffer part BUFP1b.

[0073] In addition, if Figure 3 and Figure 5As shown, the sensing signal output block SENSOB of the first buffer parts BUFP1 and BUFP1b can be coupled to the corresponding sensing control line SCL, and the corresponding sensing signal SENS can be output to the corresponding sensing control line SCL. However, the sensing signal output block SENSOB of the second buffer parts BUFP2 and BUFP2b may not be connected to the sensing control line SCL. Therefore, although the sensing signal output block SENSOB of the second buffer parts BUFP2 and BUFP2b includes the fourteenth transistor T14 and the fifteenth transistor T15 having a small size, the dummy stage 141a including the second buffer parts BUFP2 and BUFP2b can operate normally. As described above, the second buffer parts BUFP2 and BUFP2b can have a narrower width W2 than the width W1 of the first buffer parts BUFP1 and BUFP1b, so that damage to the display panel 110a that may be caused during the open short circuit test can be prevented or reduced.

[0074] Figure 6 is a diagram illustrating a portion of a display panel according to some example embodiments, and Figure 7 It is shown in Figure 6 A circuit diagram of an example of a dummy stage included in a display panel.

[0075] refer to Figure 6 , the display panel 110b according to some example embodiments may include a pixel region 120 in which a plurality of pixels are formed, an open-short test region 130 in which a plurality of open-short test pads OSTP are formed, at least one dummy stage 141b that generates a carry signal CR in response to a scan start signal SSP, and a plurality of stages 144b and 146b (or normal stages 144b and 146b) that sequentially provide a plurality of scan signals SS to the plurality of pixels in response to the carry signal CR.

[0076] Each of the stages 144b and 146b may include a first circuit portion CIRP1 that operates in response to a previous carry signal and a first buffer portion BUFP1 that is controlled by the first circuit portion CIRP1 to output a corresponding scan signal SS and a corresponding sense signal SENS. The dummy stage 141b may include a second circuit portion CIRP2 that operates in response to a scan start signal SSP and a second buffer portion BUFP2 that is controlled by the second circuit portion CIRP2. Thus, the plurality of stages 144b and 146b may be spaced apart from the pixel region 120 by a first distance, and the dummy stage 141b may be spaced apart from the open-short test region 130 by a second distance greater than the first distance, as shown in FIG. Figure 6As shown, a width W4 of a second circuit portion CIRP2 of the dummy stage 141b may be narrower than a width W3 of a first circuit portion CIRP1 of each stage 144b and 146b, and a width W2 of a second buffer portion BUFP2 of the dummy stage 141b may be narrower than a width W1 of a first buffer portion BUFP1 of each stage 144b and 146b.

[0077] In some example embodiments, each of the stages 144b and 146b may be as follows Figure 5 , and the dummy stage 141b can be implemented as Figure 7 Therefore, the first circuit portion CIRP1b of each stage 144b and 146b may include a sensing block SENB that controls the internal control node NQ based on the sensing start signal SON and the sensing clock signal SCLK, such as Figure 5 As shown, the second circuit portion CIRP2c of the dummy stage 141b may not include a sensing block SENB, as shown in FIG. Figure 7 As shown. Therefore, the width W4 of the second circuit parts CIRP2 and CIRP2c of the dummy stage 141b may be narrower than the width W3 of the first circuit parts CIRP1 and CIRP1b of each stage 144b and 146b. In addition, the size (e.g., channel width) of at least one transistor T10, T11, T14, and T15 included in the second buffer part BUFP2c of the dummy stage 141b may be smaller than the size of at least one transistor T10, T11, T14, and T15 included in the first buffer part BUFP1b of each stage 144b and 146b. Therefore, the width W2 of the second buffer parts BUFP2 and BUFP2c of the dummy stage 141b may be narrower than the width W1 of the first buffer parts BUFP1 and BUFP1b of each stage 144b and 146b.

[0078] According to some example embodiments, each of the stages 144b and 146b may be as follows Figure 5 , and the dummy stage 141b can be implemented as Figure 4 Thus, the first circuit portion CIRP1b of each stage 144b and 146b may include a sensing block SENB, such as Figure 5 As shown, the second circuit portion CIRP2a of the dummy stage 141b may not include a sensing block SENB, as shown in FIG. Figure 4As shown. Therefore, the width W4 of the second circuit parts CIRP2 and CIRP2a of the dummy stage 141b may be narrower than the width W3 of the first circuit parts CIRP1 and CIRP1b of each stage 144b and 146b. In addition, the first buffer part BUFP1b of each stage 144b and 146b may include a sense signal output block SENSOB that generates a corresponding sense signal SENS in response to the voltage of the internal control node NQ of the first circuit part CIRP1b, as shown. Figure 5 As shown, the second buffer part BUFP2a of the dummy stage 141b may not include the sensing signal output block SENSOB, as shown in FIG. Figure 4 Therefore, the width W2 of the second buffering parts BUFP2 and BUFP2a of the dummy stage 141b may be narrower than the width W1 of the first buffering parts BUFP1 and BUFP1b of each of the stages 144b and 146b.

[0079] As described above, in the display panel 110b according to some example embodiments, the width W4 of the second circuit portion CIRP2 of the dummy stage 141b may be narrower than the width W3 of the first circuit portion CIRP1 of each stage 144b and 146b, and the width W2 of the second buffer portion BUFP2 of the dummy stage 141b may be narrower than the width W1 of the first buffer portion BUFP1 of each stage 144b and 146b. Therefore, damage to the display panel 110b that may otherwise be caused during the open short circuit test may be prevented or reduced.

[0080] Figure 8 is a diagram illustrating a portion of a display panel according to some example embodiments.

[0081] refer to Figure 8 , a display panel 110c according to some example embodiments may include a pixel region 120 in which a plurality of pixels are formed, an open-short test region 130 in which a plurality of open-short test pads OSTP are formed, at least one dummy stage 141c that generates a carry signal CR in response to a scan start signal SSP, and a plurality of stages 144c and 146c that sequentially provide a plurality of scan signals SS to the plurality of pixels in response to the carry signal CR.

[0082] In the display panel 110c, the dummy stage 141c may be spaced apart from the open-short test line OSTL along which a probe of an open-short test instrument moves. Figure 8 As shown, the open-short test line OSTL may extend in a horizontal direction (eg, a direction of the scan line SSL), and the dummy stage 141c may be spaced apart from the open-short test line OSTL by a predetermined distance PD in a vertical direction (eg, a direction of the data line DL). Figure 8As shown, the dummy stage 141c may be formed outside an outer edge 130c of the open and short test region 130, which is a distal edge of the open and short test region 130 from the pixel region 120. Furthermore, in some example embodiments, the width of the dummy stage 141c may be narrower than the width of each of the stages 144c and 146c.

[0083] As described above, in the display panel 110c according to some example embodiments, the dummy stage 141c may be spaced apart from the open-short test line OSTL along which the probe of the open-short test instrument moves, and thus, damage that may otherwise be caused by the probe of the open-short test instrument during the open-short test may be prevented or reduced.

[0084] Fig. 9 is a block diagram illustrating an example of an electronic device including a display device according to some example embodiments.

[0085] refer to Fig. 9 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with a graphics card, a sound card, a memory card, a universal serial bus (USB) device, other electrical devices, and the like.

[0086] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in some example embodiments, the processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0087] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0088] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100.

[0089] In the display device 1160, the plurality of stages may be spaced apart from the pixel region by a first distance, and the dummy stage may be spaced apart from the open-short test region by a second distance greater than the first distance. Furthermore, in some example embodiments, the second distance between the open-short test region and the dummy stage may be greater than or equal to the reference distance to prevent or reduce damage caused by the open-short test instrument. Therefore, in the display device 1160 according to some example embodiments, damage to the display panel during the open-short test may be prevented or reduced.

[0090] According to some example embodiments, the electronic device 1100 may be any electronic device including a display device 1160, such as a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a digital television, a 3D television, a personal computer (PC), a home appliance, a portable computer, etc.

[0091] The foregoing is an illustration of example embodiments and should not be construed as limiting the example embodiments. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the example embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A display panel, comprising: A pixel region, including a plurality of pixels; An open-short circuit test area, including a plurality of open-short circuit test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; as well as a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal, wherein the plurality of stages are spaced apart from the pixel region by a first distance, and the dummy stage is spaced apart from the open-short test region by a second distance greater than the first distance, The second distance between the open-short circuit test area and the dummy stage is greater than or equal to a reference distance to prevent damage caused by an open-short circuit test instrument.

2. The display panel according to claim 1, wherein: A width of the dummy stage is narrower than a width of each of the plurality of stages.

3. The display panel according to claim 1, wherein: Each of the plurality of stages comprises: a first circuit portion configured to operate in response to a previous carry signal; and a first buffering part, controlled by the first circuit part to output a corresponding scanning signal among the plurality of scanning signals, Wherein, the dummy stage comprises: a second circuit portion configured to operate in response to the scan start signal; and a second buffering section, controlled by the second circuit section, and wherein a width of the second buffer portion of the dummy stage is narrower than a width of the first buffer portion of each of the plurality of stages.

4. The display panel according to claim 3, wherein: A size of at least one transistor included in the second buffer portion is smaller than a size of at least one transistor included in the first buffer portion.

5. The display panel according to claim 3, wherein: Each of the first circuit portion and the second circuit portion comprises: a control node charging block configured to charge an internal control node in response to the scan start signal or the previous carry signal; an inverter block configured to control an internal inverting control node based on a voltage of the internal control node; a control node holding block configured to hold the voltage of the internal control node; a carry block configured to generate a current carry signal in response to the voltage of the internal control node; and a control node discharge block configured to discharge the internal control node in response to a next carry signal, Wherein, each of the first buffer portion and the second buffer portion comprises: a scan signal output block configured to generate the corresponding scan signal in response to the voltage of the internal control node, and The size of the scan signal output block of the second buffer part is smaller than the size of the scan signal output block of the first buffer part.

6. The display panel according to claim 5, wherein: The scan signal output block of the first buffer part is coupled to a corresponding scan line and outputs the corresponding scan signal to the corresponding scan line, and Wherein, the scan signal output block of the second buffer part is not coupled to the scan line.

7. The display panel according to claim 5, wherein: Each of the first circuit portion and the second circuit portion further comprises: a sensing block configured to control the internal control node based on a sensing start signal and a sensing clock signal, Wherein, each of the first buffer portion and the second buffer portion further comprises: A sensing signal output block is configured to generate a corresponding sensing signal among a plurality of sensing signals in response to the voltage of the internal control node, and wherein a size of the sensing signal output block of the second buffer part is smaller than a size of the sensing signal output block of the first buffer part.

8. A display panel, comprising: A pixel region, including a plurality of pixels; An open-short circuit test area, including a plurality of open-short circuit test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; as well as a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal, The dummy stage is separated from the open-short circuit test line, and the probe of the open-short circuit test instrument moves along the open-short circuit test line. Wherein, the distance between the open-short circuit test area and the dummy stage is greater than or equal to a reference distance to prevent damage caused by the open-short circuit test instrument.

9. A display device, comprising: A display panel, comprising: a pixel region including a plurality of pixels; an open-short test region including a plurality of open-short test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal; a data driver configured to output a data signal to the display panel; and a controller configured to control the data driver, the dummy stage, and the plurality of stages, wherein the plurality of stages are spaced apart from the pixel region by a first distance, and the dummy stage is spaced apart from the open-short test region by a second distance greater than the first distance, The second distance between the open-short circuit test area and the dummy stage is greater than or equal to a reference distance to prevent damage caused by an open-short circuit test instrument.

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