Display device

Abstract

A display device is provided. The display device includes a plurality of pixels. Each of the plurality of pixels includes a first transistor, a second transistor, a first sub-transistor, and a second sub-transistor, wherein the first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a second node, the first sub-transistor includes a gate electrode connected to a first scan line, a first electrode connected to a first node, and a second electrode connected to a fourth node, and the second sub-transistor includes a gate electrode connected to a first scan line, a first electrode connected to a fourth node, and a second electrode connected to a third node. The channel width of the second sub-transistor is wider than the channel width of the first sub-transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0069610 filed in the Korean Intellectual Property Office on June 12, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to display devices. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has increased. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly being used.

[0005] The display device can be driven according to various driving frequencies. For example, when the display device is driven at a driving frequency of 60 Hz, the display device can display 60 image frames per second. For example, when the display device is driven at a driving frequency of 15 Hz, the display device can display 15 image frames per second.

[0006] When the display device is driven at a low frequency (e.g., 15 Hz), each pixel should maintain a data voltage for a relatively long period of time in each image frame compared to when the display device is driven at a normal frequency (e.g., 60 Hz). When leakage current is generated in the direction of decreasing brightness, flicker may occur due to the difference between the initial brightness IL and the final brightness EL of the image frame (see Fig.17 ). Summary of the invention

[0007] Embodiments provide a display device capable of reducing leakage current in a direction in which brightness decreases and increasing leakage current in a direction in which brightness increases.

[0008] According to one aspect of the present disclosure, a display device is provided, the display device including a plurality of pixels, wherein each of the plurality of pixels includes a first transistor, a second transistor, a first sub-transistor, and a second sub-transistor, wherein the first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the second node, the first sub-transistor includes a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node, and the second sub-transistor includes a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node, wherein a channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.

[0009] A channel width of the first sub-transistor may be narrower than a first electrode region width or a second electrode region width of the first sub-transistor.

[0010] The channel of the first sub-transistor may include a recessed portion.

[0011] The channel width of the second sub-transistor may be wider than the first electrode region width or the second electrode region width of the second sub-transistor.

[0012] The channel of the second sub-transistor may include a convex portion.

[0013] The channel length of the second sub-transistor may be equal to or shorter than the channel length of the first sub-transistor.

[0014] Each of the plurality of pixels may further include a third sub-transistor and a fourth sub-transistor, wherein the third sub-transistor includes a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to the fifth node, and the fourth sub-transistor includes a gate electrode connected to the second scan line, a first electrode connected to the fifth node, and a second electrode connected to the initialization line. A channel width of the third sub-transistor may be wider than a channel width of the first sub-transistor.

[0015] A channel width of the third sub-transistor may be wider than a width of the first electrode region or a width of the second electrode region of the third sub-transistor.

[0016] The channel of the third sub-transistor may include a convex portion.

[0017] Each of the plurality of pixels may further include a third sub-transistor and a fourth sub-transistor, wherein the third sub-transistor includes a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to the fifth node, and the fourth sub-transistor includes a gate electrode connected to the second scan line, a first electrode connected to the fifth node, and a second electrode connected to the initialization line. A channel width of the fourth sub-transistor may be wider than a channel width of the first sub-transistor.

[0018] A channel width of the fourth sub-transistor may be wider than a width of the first electrode region or a width of the second electrode region of the fourth sub-transistor.

[0019] The channel of the fourth sub-transistor may include a convex portion.

[0020] Each of the plurality of pixels may further include a fourth transistor including a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to the initialization line. A channel width of the fourth transistor may be wider than a channel width of the first sub-transistor.

[0021] According to another aspect of the present disclosure, a display device is provided, the display device including a plurality of pixels, wherein each of the plurality of pixels includes a first transistor, a second transistor, a first sub-transistor, and a second sub-transistor, wherein the first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a second node, the first sub-transistor includes a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node, and the second sub-transistor includes a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node, wherein a channel width of the first sub-transistor is wider than a channel width of the second sub-transistor.

[0022] A channel width of the first sub-transistor may be wider than a first electrode region width or a second electrode region width of the first sub-transistor.

[0023] The channel of the first sub-transistor may include a convex portion.

[0024] According to another aspect of the present disclosure, a display device is provided, the display device including a plurality of pixels, wherein each of the plurality of pixels includes a first transistor, a second transistor, a third transistor, a first sub-transistor, and a second sub-transistor, wherein the first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a second node, the third transistor includes a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the third node, the first sub-transistor includes a gate electrode connected to a second scan line, a first electrode connected to the first node, and a second electrode connected to a fifth node, and the second sub-transistor includes a gate electrode connected to a second scan line, a first electrode connected to a fifth node, and a second electrode connected to an initialization line, wherein a channel width of the first sub-transistor is wider than a channel width of the second sub-transistor.

[0025] The channel of the first sub-transistor may include a convex portion.

[0026] According to yet another aspect of the present disclosure, a display device is provided, the display device including a plurality of pixels, wherein each of the plurality of pixels includes a first transistor, a second transistor, a third transistor, a first sub-transistor, and a second sub-transistor, wherein the first transistor includes a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a second node, the third transistor includes a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the third node, the first sub-transistor includes a gate electrode connected to a second scan line, a first electrode connected to the first node, and a second electrode connected to a fifth node, and the second sub-transistor includes a gate electrode connected to a second scan line, a first electrode connected to a fifth node, and a second electrode connected to an initialization line, wherein a channel width of the second sub-transistor is wider than a channel width of the first sub-transistor.

[0027] The channel of the second sub-transistor may include a convex portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, exemplary embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0029] In the accompanying drawings, for clear illustration, the dimensions may be exaggerated. It will be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the specification, similar reference numerals indicate similar elements.

[0030] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0032] Figure 3 is a diagram illustrating a method of driving a pixel according to an embodiment of the present disclosure.

[0033] Figure 4 is a view showing a stacked structure of a pixel according to an embodiment of the present disclosure.

[0034] Figure 5 is a plan view of a pixel according to an embodiment of the present disclosure.

[0035] Figure 6 It is shown Figure 3 Graph of the leakage current of the pixel shown in FIG.

[0036] Figure 7 is a diagram showing the channel width and channel length of a transistor.

[0037] Figure 8 is a view showing a case where a channel of the (3-1)th sub-transistor includes a recessed portion.

[0038] Fig. 9 is a view showing a case where a channel of the (3-2)th sub-transistor includes a convex portion.

[0039] Fig.10 is a view showing a case where a channel of the (4-1)th sub-transistor includes a convex portion.

[0040] Fig.11 is a view showing a case where a channel of the (4-2)th sub-transistor includes a convex portion.

[0041] Fig.12 It shows that there is a leakage current direction and Figure 6 Figure 2 shows pixels with different leakage current directions.

[0042] Fig.13 is a view showing a case where a channel of the (3-1)th sub-transistor includes a convex portion.

[0043] Figures 14 to 16 is a diagram showing that the embodiments of the present disclosure can be applied to other pixels.

[0044] Fig.17 This is a diagram comparing a case where the display device is driven at a low frequency and a case where the display device is driven at a normal frequency. DETAILED DESCRIPTION

[0045] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the exemplary embodiments described in this specification.

[0046] Parts not related to the description may be omitted to clearly describe the present disclosure, and throughout the specification, the same or similar constituent elements will be represented by the same reference numerals. Therefore, the same reference numerals may be used to identify the same or similar elements in different drawings.

[0047] In addition, for better understanding and convenience of description, the size and thickness of each component shown in the figures are arbitrarily shown, but the present disclosure is not limited thereto. For clear expression, the thickness of several parts and regions is exaggerated.

[0048] Figure 1 is a diagram showing a display device 10 according to an embodiment of the present disclosure.

[0049] Reference Figure 1 , a display device 10 according to an embodiment of the present disclosure may include a timing controller 11 , a data driver 12 , a scan driver 13 , an emission driver 14 , and a pixel unit 15 .

[0050] The timing controller 11 may receive grayscale values ​​and control signals with respect to respective image frames from an external processor. The timing controller 11 may render grayscale values ​​to correspond to the specifications of the display device 10. For example, the external processor may provide red grayscale values, green grayscale values, and blue grayscale values ​​with respect to respective unit points. However, for example, when the pixel unit 15 has structure( is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea), adjacent unit points share pixels, and therefore, multiple pixels may not correspond to their respective grayscale values ​​one by one. Accordingly, it may be necessary to render the grayscale values. When multiple pixels correspond to their respective grayscale values ​​one by one, it may not be necessary to render the grayscale values. The rendered or unrendered grayscale values ​​may be provided to the data driver 12. In addition, the timing controller 11 may provide control signals suitable for their specifications to the data driver 12, the scan driver 13, the emission driver 14, and any other appropriate components to achieve frame display.

[0051] The data driver 12 may generate data voltages to be supplied to the data lines D1, D2, D3, ... and Dn by using gray values ​​and control signals. For example, the data driver 12 may sample gray values ​​by using a clock signal and apply data voltages corresponding to the gray values ​​to the data lines D1, D2, D3, ... and Dn (where n is an integer greater than 0) in units of pixel rows.

[0052] The scan driver 13 may generate scan signals to be provided to the scan lines S1 , S2 , S3 , . . . , and Sm (where m is an integer greater than 0) by receiving a clock signal and a scan start signal, etc. from the timing controller 11 .

[0053] The scan driver 13 may supply (e.g., sequentially supply) a scan signal having a pulse of an on level to the scan lines S1, S2, S3, ... and Sm. The scan driver 13 may include a scan stage configured in the form of a shift register. Under the control of a clock signal, the scan driver 13 may generate a scan signal by sequentially transmitting a scan start signal in the form of a pulse of an on level to a next scan stage.

[0054] The emission driver 14 may generate an emission signal to be provided to the emission lines E1, E2, E3, ... and Eo by receiving a clock signal and an emission stop start signal from the timing controller 11. For example, the emission driver 14 may supply (e.g., sequentially supply) an emission signal having a pulse of an off level to the emission lines E1, E2, E3, ... and Eo (where o is an integer greater than 0). For example, each emission stage of the emission driver 14 may be configured in the form of a shift register. Under the control of the clock signal, the emission driver 14 may generate an emission signal in a manner of sequentially transmitting an emission stop start signal in the form of a pulse of an off level to the next scanning stage.

[0055] The pixel unit 15 includes a plurality of pixels PXij. Each pixel PXij (where i and j are natural numbers) may be connected to a corresponding data line, a corresponding scan line, and a corresponding emission line. The pixel PXij may mean a pixel whose scan transistor is connected to the i-th scan line and the j-th data line.

[0056] Figure 2 is a diagram showing a pixel PXij according to an embodiment of the present disclosure.

[0057] Reference Figure 2 , the pixel PXij may include a transistor T1 , a transistor T2 , a transistor T3 , a transistor T4 , a transistor T5 , a transistor T6 , and a transistor T7 , a storage capacitor Cst, and a light emitting diode LD.

[0058] Hereinafter, a circuit configured with a P-type transistor will be described as an example. However, those skilled in the art can design a circuit configured with an N-type transistor by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art can design a circuit configured with a combination of a P-type transistor and an N-type transistor. A P-type transistor refers to a transistor whose amount of current flowing increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor refers to a transistor whose amount of current flowing increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. The transistor can be configured in various forms, including a thin film transistor (TFT), a field effect transistor (FET), a bipolar junction transistor (BJT) and / or any other suitable form.

[0059] A gate electrode of the first transistor T1 may be connected to the first node N1, a first electrode of the first transistor T1 may be connected to the second node N2, and a second electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may be referred to as a driving transistor.

[0060] A gate electrode of the second transistor T2 may be connected to the i-th scan line Si, a first electrode of the second transistor T2 may be connected to the data line Dj, and a second electrode of the second transistor T2 may be connected to the second node N2. The second transistor T2 may be referred to as a scan transistor.

[0061] A gate electrode of the third transistor T3 may be connected to the i-th scan line Si, a first electrode of the third transistor T3 may be connected to the first node N1, and a second electrode of the third transistor T3 may be connected to the third node N3. The third transistor T3 may be referred to as a diode-connected transistor.

[0062] The third transistor T3 may include a (3-1)th sub-transistor T3a and a (3-2)th sub-transistor T3b. A gate electrode of the (3-1)th sub-transistor T3a may be connected to an i-th scan line Si, a first electrode of the (3-1)th sub-transistor T3a may be connected to a first node N1, and a second electrode of the (3-1)th sub-transistor T3a may be connected to a fourth node N4. A gate electrode of the (3-2)th sub-transistor T3b may be connected to an i-th scan line Si, a first electrode of the (3-2)th sub-transistor T3b may be connected to a fourth node N4, and a second electrode of the (3-2)th sub-transistor T3b may be connected to a third node N3.

[0063] The gate electrode of the fourth transistor T4 may be connected to the (i-1)th scan line S(i-1), the first electrode of the fourth transistor T4 may be connected to the first node N1, and the second electrode of the fourth transistor T4 may be connected to the initialization line INTL. In another embodiment, the gate electrode of the fourth transistor T4 may be connected to another scan line. The fourth transistor T4 may be referred to as a gate initialization transistor.

[0064] The fourth transistor T4 may include a (4-1)th sub-transistor T4a and a (4-2)th sub-transistor T4b. A gate electrode of the (4-1)th sub-transistor T4a may be connected to the (i-1)th scan line S(i-1), a first electrode of the (4-1)th sub-transistor T4a may be connected to the first node N1, and a second electrode of the (4-1)th sub-transistor T4a may be connected to the fifth node N5. A gate electrode of the (4-2)th sub-transistor T4b may be connected to the (i-1)th scan line S(i-1), a first electrode of the (4-2)th sub-transistor T4b may be connected to the fifth node N5, and a second electrode of the (4-2)th sub-transistor T4b may be connected to the initialization line INTL.

[0065] The gate electrode of the fifth transistor T5 may be connected to the i-th emission line Ei, the first electrode of the fifth transistor T5 may be connected to the first power line ELVDDL, and the second electrode of the fifth transistor T5 may be connected to the second node N2. The fifth transistor T5 may be referred to as an emission transistor. In another embodiment, the gate electrode of the fifth transistor T5 may be connected to another emission line.

[0066] The gate electrode of the sixth transistor T6 may be connected to the i-th emission line Ei, the first electrode of the sixth transistor T6 may be connected to the third node N3, and the second electrode of the sixth transistor T6 may be connected to the anode of the light emitting diode LD. The sixth transistor T6 may be referred to as an emission transistor. In another embodiment, the gate electrode of the sixth transistor T6 may be connected to another emission line.

[0067] The gate electrode of the seventh transistor T7 may be connected to the i-th scan line Si, the first electrode of the seventh transistor T7 may be connected to the initialization line INTL, and the second electrode of the seventh transistor T7 may be connected to the anode of the light emitting diode LD. The seventh transistor T7 may be referred to as an anode initialization transistor. In another embodiment, the gate electrode of the seventh transistor T7 may be connected to another scan line.

[0068] A first electrode of the storage capacitor Cst may be connected to the first power line ELVDDL, and a second electrode of the storage capacitor Cst may be connected to the first node N1.

[0069] An anode of the light emitting diode LD may be connected to the second electrode of the sixth transistor T6, and a cathode of the light emitting diode LD may be connected to the second power line ELVSSL. The light emitting diode LD may be implemented by an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0070] A first power supply voltage may be applied to the first power supply line ELVDDL, a second power supply voltage may be applied to the second power supply line ELVSSL, and an initialization voltage may be applied to the initialization line INTL. For example, the first power supply voltage may be greater than the second power supply voltage. For example, the initialization voltage may be equal to or greater than the second power supply voltage.

[0071] Figure 3 is a diagram illustrating a driving method of a pixel PXij according to an embodiment of the present disclosure.

[0072] First, the data voltage DATA(i-1)j of the (i-1)th pixel is applied to the data line Dj, and a scan signal having a turn-on level (eg, a low level) is applied to the (i-1)th scan line S(i-1).

[0073] Because a scan signal having an off level (eg, a high level) is applied to the i-th scan line Si, the second transistor T2 is in an off state and prevents the data voltage DATA(i-1)j of the (i-1)-th pixel from being input to the pixel PXij.

[0074] Because the fourth transistor T4 is in the on state, the first node N1 is connected (e.g., electrically connected) to the initialization line INTL, so the voltage of the first node N1 is initialized and the first transistor T1 is in the conduction state. Because the emission signal with the off level is applied to the i-th emission line Ei, the fifth transistor T5 and the sixth transistor T6 are in the off state, and unnecessary emission of the light emitting diode LD during the application of the initialization voltage is reduced or prevented.

[0075] Next, the data voltage DATAij of the i-th pixel is applied to the data line Dj, and a scan signal having an on-level is applied to the i-th scan line Si. Accordingly, the second transistor T2 and the third transistor T3 are in a conducting state (i.e., an on-state), and the data line Dj and the first node N1 are electrically connected to each other. Therefore, a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage DATAij is applied to the second electrode (i.e., the first node N1) of the storage capacitor Cst, and the storage capacitor Cst maintains a voltage corresponding to the difference between the first power supply voltage and the compensation voltage. The period during which the storage capacitor Cst maintains the voltage may be referred to as a threshold voltage compensation period.

[0076] Because the seventh transistor T7 is in the on state, the anode of the light emitting diode LD and the initialization line INTL are connected to each other, and the light emitting diode LD is initialized with charges having a size corresponding to the difference between the initialization voltage and the second power supply voltage.

[0077] Subsequently, when an emission signal having a conduction level is applied to the i-th emission line Ei, the fifth transistor T5 and the sixth transistor T6 may be in a conduction state (i.e., a conduction state). Therefore, a driving current path is formed as a path of the first power line ELVDDL, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the light emitting diode LD, and the second power line ELVSSL.

[0078] The amount of driving current flowing through the first electrode and the second electrode of the first transistor T1 is controlled according to the voltage maintained in the storage capacitor Cst. The light emitting diode LD emits light with a brightness corresponding to the amount of driving current. The light emitting diode LD emits light until an emission signal with an off level is applied to the i-th emission line Ei. The period of maintaining the driving current path may be referred to as an emission period.

[0079] exist Figure 3In the embodiment, a case where one pulse having a conduction level is generated in the (i-1)th scan line S(i-1) and the i-th scan line Si in one image frame period is described as an example. However, in another embodiment, in order to apply a conduction bias to the first transistor T1, two or more pulses having a conduction level may be generated in the (i-1)th scan line S(i-1) and the i-th scan line Si in one image frame period.

[0080] Figure 4 is a view showing a stack structure of a pixel PXij according to an embodiment of the present disclosure.

[0081] Reference Figure 4 In an embodiment of the present disclosure, each pixel PXij may have a structure in which a semiconductor layer L1, a gate insulating layer L2, a first gate electrode layer L3, a first insulating layer L4, a second gate electrode layer L5, a second insulating layer L6, and a source / drain electrode layer L7 are stacked on a substrate SUB. In some embodiments, the source / drain electrode layer L7 may include a first source / drain electrode layer and a second source / drain electrode layer, and an insulating layer is disposed between the first source / drain electrode layer and the second source / drain electrode layer.

[0082] In the above embodiments, the transistors T1 to T7 , the storage capacitor Cst, and the lines Dj, Si, S(i−1), Ei, ELVDDL, and INTL may be elements formed by patterning at least a portion of the stack structure.

[0083] The substrate SUB may be made of various materials such as glass, polymers, and metals. The substrate SUB may be selected as one of a rigid substrate and a flexible substrate depending on the product to which the substrate SUB is applied. When the substrate SUB includes at least one of polymer organic materials, the substrate SUB may be made of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or any other suitable substrate. In other embodiments, the substrate SUB may be made of fiber reinforced plastic (FRP).

[0084] The buffer layer or barrier layer may be located between the substrate SUB and the semiconductor layer L1. The buffer layer or barrier layer may be used to prevent impurities of the substrate SUB from diffusing into the semiconductor layer L1 or to prevent moisture from penetrating into the semiconductor layer L1. The buffer layer or barrier layer may be configured as an organic insulating layer, an inorganic insulating layer, or an organic / inorganic insulating layer, etc. The buffer layer or barrier layer may be configured as a single layer or as a multilayer. For example, the buffer layer or barrier layer may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO xN y ) and / or any other suitable material.

[0085] The semiconductor layer L1 may be made of polycrystalline silicon, amorphous silicon, an oxide semiconductor, an organic semiconductor, an inorganic semiconductor, and / or any other suitable material. A portion of the semiconductor layer L1 may constitute a channel of each transistor, and another portion of the semiconductor layer L1 may be doped with P-type impurities (i.e., acceptors). The portion doped with acceptors may constitute a first electrode and a second electrode of each transistor and a connecting line.

[0086] Each of the gate insulating layer L2, the first insulating layer L4, and the second insulating layer L6 prevents unnecessary electrical contact between the upper conductive layer and the lower conductive layer. Each of the gate insulating layer L2, the first insulating layer L4, and the second insulating layer L6 may be configured as an organic insulating layer, an inorganic insulating layer, an organic / inorganic insulating layer, and / or any other suitable insulating layer. Each of the gate insulating layer L2, the first insulating layer L4, and the second insulating layer L6 may be configured as a single layer or as a multilayer. For example, the gate insulating layer L2, the first insulating layer L4, and the second insulating layer L6 may be made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and / or any other suitable material.

[0087] Each of the first gate electrode layer L3, the second gate electrode layer L5, and the source / drain electrode layer L7 constitutes a conductive layer. Each conductive layer may be configured as a single layer or as a multilayer. Each conductive layer may be made of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), platinum (Pt), and / or any other suitable material.

[0088] The gate electrode of each transistor may be configured with the first gate electrode layer L3. The storage capacitor Cst may be configured by using the first gate electrode layer L3 as a lower electrode and using the second gate electrode layer L5 as an upper electrode.

[0089] Figure 5 is a plan view of a pixel PXij according to an embodiment of the present disclosure.

[0090] The i-th scan line Si, the (i-1)-th scan line S(i-1), the i-th emission line Ei, and the lower electrode LE of the storage capacitor Cst may be configured with (eg, at the same layer as) the first gate electrode layer L3.

[0091] The upper electrode UE of the storage capacitor Cst and the initialization line INTL may be configured with (eg, at the same layer as) the second gate electrode layer L5 .

[0092] The data line Dj, the first power line ELVDDL, and some bridge electrodes may be configured with the source / drain electrode layer L7 (eg, at the same layer as the source / drain electrode layer L7).

[0093] The channel of each of the transistors T1 to T7 may be configured with an undoped portion of the semiconductor layer L1 (e.g., at the undoped portion of the semiconductor layer L1), and the first electrode and the second electrode of each of the transistors T1 to T7 may be configured with a doped portion of the semiconductor layer L1 (e.g., at the doped portion of the semiconductor layer L1). The gate electrode of each of the transistors T1 to T7 may be configured with a first gate electrode layer L3 (e.g., at the same layer as the first gate electrode layer L3).

[0094] The connection electrode ANC may connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6 to the anode of the light emitting diode LD.

[0095] Figure 6 It is shown Figure 3 Graph of the leakage current of the pixel PXij shown in .

[0096] When the transistor is in the off state, it is ideal that the off current is 0. However, in reality, the off current is not actually 0. Therefore, the off current indicates the leakage current.

[0097] As described above, the compensation voltage may be stored at the first node N1 in the threshold voltage compensation period, and the light emission brightness may be maintained only when the compensation voltage of the first node N1 is maintained during the light emission period.

[0098] As the display device 10 is driven at a lower frequency, the leakage current may flow for a longer time. Therefore, the compensation voltage of the first node N1 cannot be maintained. Fig.17 It can be observed that when the display device is driven at a low frequency (eg, 15 Hz), the final brightness EL of an image frame is lower than the initial brightness IL of the image frame. Figure 6 The first transistor T1 shown in FIG. 1 is a P-type transistor, and thus the voltage of the first node N1 increases with the passage of time.

[0099] Therefore, in order to increase the final brightness EL, it may be necessary to adjust the drain current in a direction in which the voltage of the first node N1 decreases.

[0100] A parasitic capacitor Cp3 generated between the fourth node N4 and the first power line ELVDDL and a parasitic capacitor Cp4 generated between the fifth node N5 and the initialization line INTL may exist in the pixel PXij.

[0101] The leakage current direction of each node can be determined according to the capacitance of the parasitic capacitor Cp3 and the parasitic capacitor Cp4. Figure 6 Another parasitic capacitor not shown in FIG. 4 may become a factor (eg, a decisive factor) for determining the direction of the leakage current.

[0102] For example, a leakage current LC3a flowing in a direction from the fourth node N4 to the first node N1 may be generated in the (3-1)th sub-transistor T3a. A leakage current LC3b flowing in a direction from the fourth node N4 to the third node N3 may be generated in the (3-2)th sub-transistor T3b. A leakage current LC4a flowing in a direction from the first node N1 to the fifth node N5 may be generated in the (4-1)th sub-transistor T4a. A leakage current LC4b flowing in a direction from the fifth node N5 to the initialization line INTL may be generated in the (4-2)th sub-transistor T4b.

[0103] Therefore, in order to increase the final luminance EL, there are an embodiment in which the leakage current LC3a of the (3-1)th sub-transistor T3a is reduced, an embodiment in which the leakage current LC3b of the (3-2)th sub-transistor T3b is increased, an embodiment in which the leakage current LC4a of the (4-1)th sub-transistor T4a is increased, and an embodiment in which the leakage current LC4b of the (4-2)th sub-transistor T4b is increased. The embodiments may be combined with each other.

[0104] Figure 7 is a diagram showing the channel width and channel length of a transistor.

[0105] exist Figure 7 , for convenience, the channel of each of the transistors is shown at a portion where the gate electrode of the transistor and the semiconductor layer L1 overlap each other. However, as described above, the channel of the transistor may correspond to a doped portion between the first electrode and the second electrode of the transistor and may not completely overlap with the gate electrode of the transistor.

[0106] The (3-1)th sub-transistor T3a may include a channel having a channel width W3a and a channel length L3a. The (3-2)th sub-transistor T3b may include a channel having a channel width W3b and a channel length L3b. The (4-1)th sub-transistor T4a may include a channel having a channel width W4a and a channel length L4a. The (4-2)th sub-transistor T4b may include a channel having a channel width W4b and a channel length L4b.

[0107] When the embodiments of the present disclosure are not applied, the channel width W3a, channel width W3b, channel width W4a, and channel width W4b of the (3-1)th sub-transistor T3a, the (3-2)th sub-transistor T3b, the (4-1)th sub-transistor T4a, and the (4-2)th sub-transistor T4b may be substantially the same. In addition, when the embodiments of the present disclosure are not applied, the channel length L3a, channel length L3b, channel length L4a, and channel length L4b of the (3-1)th sub-transistor T3a, the (3-2)th sub-transistor T3b, the (4-1)th sub-transistor T4a, and the (4-2)th sub-transistor T4b may be substantially the same.

[0108] When the embodiments of the present disclosure are not applied, the channel width W3a and the channel width W3b of the (3-1)th sub-transistor T3a and the (3-2)th sub-transistor T3b may be wider than the channel width W4a and the channel width W4b of the (4-1)th sub-transistor T4a and the (4-2)th sub-transistor T4b. In addition, when the embodiments of the present disclosure are not applied, the channel length L3a, the channel length L3b, the channel length L4a and the channel length L4b of the (3-1)th sub-transistor T3a, the (3-2)th sub-transistor T3b, the (4-1)th sub-transistor T4a and the (4-2)th sub-transistor T4b may be substantially the same.

[0109] Figure 8 3 is a view showing a case where the channel of the (3-1)th sub-transistor T3a' includes a concave portion CC3a'.

[0110] For example, the channel width W3a' of the (3-1)th sub-transistor T3a' may be narrower than the channel width W3b of the (3-2)th sub-transistor T3b. In addition, the channel width W3a' of the (3-1)th sub-transistor T3a' may be narrower than the channel width W4a of the (4-1)th sub-transistor T4a. In addition, the channel width W3a' of the (3-1)th sub-transistor T3a' may be narrower than the channel width W4b of the (4-2)th sub-transistor T4b.

[0111] According to an embodiment, the channel width W3a' of the (3-1)th sub-transistor T3a' may be narrower than the first electrode region width W31a' and / or the second electrode region width W32a' of the (3-1)th sub-transistor T3a'. For example, the channel of the (3-1)th sub-transistor T3a' may have a concave portion CC3a'.

[0112] In another embodiment, the channel width W3a' of the (3-1)th sub-transistor T3a' may be equal to the first electrode region width W31a' or the second electrode region width W32a' of the (3-1)th sub-transistor T3a'. For example, the channel of the (3-1)th sub-transistor T3a' does not have a recess, and the channel width W3a' of the (3-1)th sub-transistor T3a' may be narrower than the channel width W3b and the channel width W4a. However, in this embodiment, the capacitance of the parasitic capacitor Cp3 may change due to the reduction of the line width of the fourth node N4, and therefore, the leakage current direction of the pixel PXij may need to be reconfirmed.

[0113] In an embodiment, the channel length L3a of the (3-1)th sub-transistor T3a' may be equal to or longer than the channel length L3b of the (3-2)th sub-transistor T3b. In addition, the channel length L3a of the (3-1)th sub-transistor T3a' may be equal to or longer than the channel length L4a and the channel length L4b of the (4-1)th sub-transistor T4a and the (4-2)th sub-transistor T4b.

[0114] according to Figure 8 The embodiment shown in can reduce the leakage current LC3a of the (3-1)th sub-transistor T3a'.

[0115] Fig. 9 3 is a view showing a case where the channel of the (3-2)th sub-transistor T3b' includes a convex portion CV3b'.

[0116] For example, the channel width W3b' of the (3-2)th sub-transistor T3b' may be wider than the channel width W3a of the (3-1)th sub-transistor T3a.

[0117] In an embodiment, the channel width W3b' of the (3-2)th sub-transistor T3b' may be wider than the first electrode region width W31b' and / or the second electrode region width W32b' of the (3-2)th sub-transistor T3b'. For example, the channel of the (3-2)th sub-transistor T3b' may have a convex portion CV3b'.

[0118] In another embodiment, the channel width W3b' of the (3-2)th sub-transistor T3b' may be equal to the first electrode region width W31b' or the second electrode region width W32b' of the (3-2)th sub-transistor T3b'. For example, the channel of the (3-2)th sub-transistor T3b' does not have a convex portion CV3b', and the channel width W3b' of the (3-2)th sub-transistor T3b' may be wider than the channel width W3a of the (3-1)th sub-transistor T3a. However, in this embodiment, the capacitance of the parasitic capacitor Cp3 may change due to an increase in the line width of the fourth node N4, and therefore, the leakage current direction of the pixel PXij may need to be reconfirmed.

[0119] In an embodiment, the channel length L3b of the (3-2)th sub-transistor T3b' may be equal to or shorter than the channel length L3a of the (3-1)th sub-transistor T3a.

[0120] according to Fig. 9 The embodiment shown in can increase the leakage current LC3b of the (3-2)th sub-transistor T3b'.

[0121] Fig.10 4 is a view showing a case where the channel of the (4-1)th sub-transistor T4a' includes a convex portion CV4a'.

[0122] For example, the channel width W4a' of the (4-1)th sub-transistor T4a' may be wider than the channel width W3a of the (3-1)th sub-transistor T3a.

[0123] In an embodiment, the channel width W4a' of the (4-1)th sub-transistor T4a' may be wider than the first electrode region width W41a' and / or the second electrode region width W42a' of the (4-1)th sub-transistor T4a'. For example, the channel of the (4-1)th sub-transistor T4a' may have a convex portion CV4a'.

[0124] In another embodiment, the channel width W4a' of the (4-1)th sub-transistor T4a' may be equal to the first electrode region width W41a' and / or the second electrode region width W42a' of the (4-1)th sub-transistor T4a'. For example, the channel of the (4-1)th sub-transistor T4a' does not have a convex portion CV4a', and the channel width W4a' of the (4-1)th sub-transistor T4a' may be wider than the channel width W3a of the (3-1)th sub-transistor T3a. However, in this embodiment, the capacitance of the parasitic capacitor Cp4 may change due to an increase in the line width of the fifth node N5, and therefore, the leakage current direction of the pixel PXij may need to be reconfirmed.

[0125] In an embodiment, the channel length L4a of the (4-1)th sub-transistor T4a' may be equal to or shorter than the channel length L3a of the (3-1)th sub-transistor T3a.

[0126] according to Fig.10 The embodiment shown in can increase the leakage current LC4a of the (4-1)th sub-transistor T4a'.

[0127] Fig.11 4 is a view showing a case where the channel of the (4-2)th sub-transistor T4b' includes a convex portion CV4b'.

[0128] For example, the channel width W4b' of the (4-2)th sub-transistor T4b' may be wider than the channel width W3a of the (3-1)th sub-transistor T3a.

[0129] In an embodiment, the channel width W4b' of the (4-2)th sub-transistor T4b' may be wider than the first electrode region width W41b' and / or the second electrode region width W42b' of the (4-2)th sub-transistor T4b'. For example, the channel of the (4-2)th sub-transistor T4b' may have a convex portion CV4b'.

[0130] In another embodiment, the channel width W4b' of the (4-2)th sub-transistor T4b' may be equal to the first electrode region width W41b' and / or the second electrode region width W42b' of the (4-2)th sub-transistor T4b'. For example, the channel of the (4-2)th sub-transistor T4b' does not have a convex portion CV4b', and the channel width W4b' of the (4-2)th sub-transistor T4b' may be wider than the channel width W3a of the (3-1)th sub-transistor T3a. However, in this embodiment, the capacitance of the parasitic capacitor Cp4 may change due to an increase in the line width of the fifth node N5, and therefore, the leakage current direction of the pixel PXij may need to be reconfirmed.

[0131] In an embodiment, the channel length L4b of the (4-2)th sub-transistor T4b' may be equal to or shorter than the channel length L3a of the (3-1)th sub-transistor T3a.

[0132] according to Fig.11 The embodiment shown in can increase the leakage current LC4b of the (4-2)th sub-transistor T4b'.

[0133] Figures 8 to 11 The above-described embodiments shown in can be selectively combined with each other.

[0134] Fig.12 It shows that there is a leakage current direction and Figure 6 Figure 2 shows pixels with different leakage current directions.

[0135] because Fig.12 The capacitance of the parasitic capacitor Cp3" of the pixel PXij shown in FIG. Figure 6 The difference between the capacitances of the parasitic capacitor Cp3 of the pixel PXij shown in FIG. 1 assumes the case where the leakage current LC3a" of the (3-1)th sub-transistor T3a flows in the direction from the first node N1 to the fourth node N4.

[0136] Therefore, in Fig.12 In the pixel PXij shown in , the leakage current LC3a" increases, so the final brightness EL can be increased.

[0137] Fig.13 3 is a view showing a case where the channel of the (3-1)th sub-transistor T3a" includes a convex portion CV3a".

[0138] For example, the channel width W3a" of the (3-1)th sub-transistor T3a" may be wider than the channel width W3b, the channel width W4a, and the channel width W4b.

[0139] In an embodiment, the channel width W3a" of the (3-1)th sub-transistor T3a" may be wider than the first electrode region width W31a" and / or the second electrode region width W32a" of the (3-1)th sub-transistor T3a". For example, the channel of the (3-1)th sub-transistor T3a" may have a convex portion CV3a".

[0140] In another embodiment, the channel width W3a" of the (3-1)th sub-transistor T3a" may be equal to the first electrode area width W31a" and / or the second electrode area width W32a" of the (3-1)th sub-transistor T3a". For example, the channel of the (3-1)th sub-transistor T3a" does not have a convex portion CV3a", and the channel width W3a" of the (3-1)th sub-transistor T3a" may be wider than the channel width W3b, the channel width W4a, and the channel width W4b. However, in this embodiment, the capacitance of the parasitic capacitor Cp3" may change due to the increase in the line width of the fourth node N4, and therefore, the leakage current direction of the pixel PXij may need to be reconfirmed.

[0141] according to Fig.13 The embodiment shown in can increase the leakage current LC3a" of the (3-1)th sub-transistor T3a".

[0142] Figures 14 to 16 is a diagram showing that the embodiments of the present disclosure can be applied to other pixels.

[0143] Fig.14 The pixel PXija shown in Figure 6 The third transistor T3 shown in FIG. 1 is configured as a single third transistor T3s and Figure 6 The fourth transistor T4 shown in FIG. 1 is configured as a single fourth transistor T4s.

[0144] The leakage current LC3s of the third transistor T3s may be generated in a direction from the first node N1 to the third node N3. In addition, the leakage current LC4s of the fourth transistor T4s may be generated in a direction from the first node N1 to the initialization line INTL.

[0145] Therefore, the leakage current LC3s and the leakage current LC4s may be increased (eg, preferably increased). To increase the leakage current LC3s and the leakage current LC4s, reference is made to the above embodiments including examples of changing the channel width / channel length of the third transistor T3s and the fourth transistor T4s.

[0146] Fig.15The pixel PXijb shown in Figure 6 The fourth transistor T4 shown in FIG. 1 is configured as a single fourth transistor T4s.

[0147] The drain current LC4s of the fourth transistor T4s may be generated in a direction from the first node N1 to the initialization line INTL.

[0148] Therefore, the drain current LC4s may be increased (eg, preferably increased). In order to increase the drain current LC4s, reference is made to the above-described embodiments including an example of changing the channel width / channel length of the fourth transistor T4s.

[0149] For example, the channel width of the fourth transistor T4s may be wider than the channel width of the (3-1)th sub-transistor T3a. In addition, the channel length of the fourth transistor T4s may be shorter than the channel length of the (3-1)th sub-transistor T3a.

[0150] Fig.16 The pixel PXijc shown in Figure 6 The third transistor T3 shown in FIG. 1 is configured as a single third transistor T3s.

[0151] The drain current LC3s of the third transistor T3s may be generated in a direction from the first node N1 to the third node N3.

[0152] Therefore, the drain current LC3s may be increased (eg, preferably increased). In order to increase the drain current LC3s, reference is made to the above-described embodiments including an example of changing the channel width / channel length of the third transistor T3s.

[0153] In an embodiment, the channel width of the (4-1)th sub-transistor T4a may be wider than the channel width of the (4-2)th sub-transistor T4b. For example, the channel of the (4-1)th sub-transistor T4a may include a convex portion. In addition, the channel length of the (4-1)th sub-transistor T4a may be shorter than the channel length of the (4-2)th sub-transistor T4b. Accordingly, the leakage current LC4a may be increased.

[0154] In an embodiment, the channel width of the (4-2)th sub-transistor T4b may be wider than the channel width of the (4-1)th sub-transistor T4a. For example, the channel of the (4-2)th sub-transistor T4b may include a convex portion. In addition, the channel length of the (4-2)th sub-transistor T4b may be shorter than the channel length of the (4-1)th sub-transistor T4a. Accordingly, the leakage current LC4b may be increased.

[0155] According to the present disclosure, the display device can reduce the leakage current in the direction in which the brightness decreases, and increase the leakage current in the direction in which the brightness increases.

[0156] Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art as this application is submitted that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node, and The channel width of the second sub-transistor is wider than the channel width of the first sub-transistor.

2. The display device according to claim 1, wherein: The channel width of the first sub-transistor is narrower than a first electrode region width or a second electrode region width of the first sub-transistor.

3. The display device according to claim 2, wherein: A channel of the first sub-transistor includes a recessed portion.

4. The display device according to claim 1, wherein: The channel width of the second sub-transistor is wider than the first electrode region width or the second electrode region width of the second sub-transistor, and Wherein, the channel of the second sub-transistor includes a convex portion.

5. The display device according to claim 1, wherein: A channel length of the second sub-transistor is equal to or shorter than a channel length of the first sub-transistor.

6. The display device according to claim 1, wherein: Each of the plurality of pixels further comprises: a third sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to a fifth node; and a fourth sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the fifth node, and a second electrode connected to an initialization line, Wherein, the channel width of the third sub-transistor is wider than the channel width of the first sub-transistor, The channel width of the third sub-transistor is wider than at least one of the first electrode region width and the second electrode region width of the third sub-transistor, and Wherein, the channel of the third sub-transistor includes a convex portion.

7. The display device according to claim 1, wherein: Each of the plurality of pixels further comprises: a third sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the first node, and a second electrode connected to a fifth node; and a fourth sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the fifth node, and a second electrode connected to an initialization line, Wherein, the channel width of the fourth sub-transistor is wider than the channel width of the first sub-transistor, The channel width of the fourth sub-transistor is wider than the first electrode region width or the second electrode region width of the fourth sub-transistor, and Wherein, the channel of the fourth sub-transistor includes a convex portion.

8. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a first sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to a fourth node; and a second sub-transistor including a gate electrode connected to the first scan line, a first electrode connected to the fourth node, and a second electrode connected to the third node, and The channel width of the first sub-transistor is wider than the channel width of the second sub-transistor.

9. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a third transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the third node; a first sub-transistor including a gate electrode connected to a second scan line, a first electrode connected to the first node, and a second electrode connected to a fifth node; and a second sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the fifth node, and a second electrode connected to an initialization line, and The channel width of the first sub-transistor is wider than the channel width of the second sub-transistor.

10. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: a first transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to a third node; a second transistor including a gate electrode connected to the first scan line, a first electrode connected to the data line, and a second electrode connected to the second node; a third transistor including a gate electrode connected to the first scan line, a first electrode connected to the first node, and a second electrode connected to the third node; a first sub-transistor including a gate electrode connected to a second scan line, a first electrode connected to the first node, and a second electrode connected to a fifth node; and a second sub-transistor including a gate electrode connected to the second scan line, a first electrode connected to the fifth node, and a second electrode connected to an initialization line, and The channel width of the second sub-transistor is wider than the channel width of the first sub-transistor.

Images