Memory device and method for reading page media stream
By introducing multi-level buffer latch and data path circuit into the NAND flash memory device, and combining with ECC circuit to optimize data transmission, the problem of long reading delay of NAND flash memory device is solved, and the effect of fast continuous reading and improving system throughput is achieved.
CN112634969BActive Publication Date: 2025-03-25MACRONIX INTERNATIONAL CO LTD
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Patent Information
- Application Number
- CN202010031351.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-09-24
- Filing Date
- 2020-01-13
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2040-01-13
AI Technical Summary
Technical Problem
NAND flash devices have long delays in read latency, resulting in the system significantly slower than other types of memory in some operations, affecting the system's throughput.
Method used
By introducing multi-level buffer latch and data path circuits into the memory device, pipeline operation is supported to reduce read delays and optimize data transmission through ECC circuits to improve read efficiency.
Benefits of technology
Support for fast continuous read operations in NAND flash devices is realized, reducing read latency, improving system throughput, and effectively managing chip area and manufacturing costs.
✦ Generated by Eureka AI based on patent content.
Abstract
The present invention discloses a memory device and a method for reading a page media stream thereof. The memory device is a memory device including a page buffer having a first-level buffer latch and a second-level buffer latch, such as a page-mode NAND flash memory. The memory device operates using: a first pipeline stage, transferring a page to the first-level buffer latch; a second pipeline stage, clearing the second-level buffer latch to a third buffer stage and transferring the page from the first-level buffer latch to the second-level buffer latch; and a third pipeline stage, moving the page to a third buffer stage and performing a first ECC function on data in a first portion of the page in an interleaved manner and outputting the first portion of the page when performing a second ECC function, and performing the first ECC function on data in a second portion of the page in the third buffer stage and outputting the second portion when performing the second ECC function.
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