Differential demodulation circuit and receiving circuit

Abstract

The present invention provides a differential demodulation circuit and a receiving end circuit, wherein the differential demodulation circuit comprises: a first filtering module, a second filtering module, a first signal conversion module, a second signal conversion module, a signal detection module and a signal output module; the third end of the first signal conversion module is connected to the first end of the signal detection module, the first end and the second end of the second signal conversion module are respectively connected to the first input signal and the second input signal, the third end of the second signal conversion module is connected to the second end of the signal detection module, and the output end of the signal detection module is connected to the signal output module; it can be judged whether the first input signal and the second input signal are differential signals, and the signal output module is controlled to output the corresponding level, thereby realizing demodulation of the differential signal. Different from the demodulation circuit solution in the prior art, the technical basis is provided for more application environments.

Description

Technical Field

[0001] The present invention relates to the technical field of communication systems, and in particular to a differential demodulation circuit and a receiving end circuit. Background Art

[0002] In a communication system, the signal received by the receiving end will be coupled with various interference signals in the transmission environment during the signal transmission process, making it impossible for the receiving end to obtain an accurate signal.

[0003] The receiving end circuit generally includes an amplifier circuit and a differential demodulation circuit. The amplifier amplifies the received signal; the differential demodulation circuit is a circuit that filters out the same interference signal from the received signal, amplifies the original signal, and then demodulates it. Summary of the invention

[0004] The present invention provides a differential demodulation circuit and a receiving end circuit, which break through the demodulation circuit solution in the prior art and provide a technical basis for more application environments.

[0005] According to a first aspect of the present invention, there is provided a differential demodulation circuit, comprising: a first filtering module, a second filtering module, a first signal conversion module, a second signal conversion module, a signal detection module and a signal output module;

[0006] The first filtering module is used to filter the first input signal and feed it back to the first end of the first signal conversion module; the second filtering module is used to filter the second input signal and feed it back to the second end of the first signal conversion module;

[0007] The third end of the first signal conversion module is connected to the first end of the signal detection module, and is used to convert the filtered first input signal and the filtered second input signal into a single-ended first target signal after amplification, and feed the first target signal back to the signal detection module;

[0008] The first end and the second end of the second signal conversion module are respectively connected to the first input signal and the second input signal, and the third end of the second signal conversion module is connected to the second end of the signal detection module, and is used to amplify the first input signal and the second input signal and convert them into a single-ended second target signal, and feed the second target signal back to the signal detection module;

[0009] The output end of the signal detection module is connected to the signal output module, and the signal output module is used to:

[0010] If it is detected that the first input signal and the second input signal are differential signals according to the first target signal and the second target signal, the signal output module is controlled to output a first level signal to a terminal at the receiving end;

[0011] If it is detected that the first input signal and the second input signal are non-differential signals according to the first target signal and the second target signal, the signal output module is controlled to output a second level signal to a terminal at the receiving end.

[0012] Optionally, the first signal conversion module includes a first transistor and a second transistor;

[0013] The control electrode of the first transistor is connected to the first end of the first filtering module, the first electrode of the first transistor is connected to the first electrode of the second transistor and the first end of the signal detection module, and the second electrode of the first transistor is connected to the second electrode of the second transistor;

[0014] The control electrode of the second transistor is connected to the first end of the second filtering module.

[0015] Optionally, the second signal conversion module includes a third transistor and a fourth transistor;

[0016] The control electrode of the third transistor is connected to the first input signal, the first electrode of the third transistor is connected to the first electrode of the fourth transistor and the first end of the signal detection module, and the second electrode of the third transistor is connected to the second electrode of the fourth transistor;

[0017] The control electrode of the fourth transistor is connected to the second input signal.

[0018] Optionally, the signal detection module includes a charging unit and a capacitor,

[0019] The first end of the charging unit is connected to the third end of the first signal conversion module, the second end of the charging unit is connected to the third end of the second signal conversion module, the output end of the charging unit is connected to the first end of the capacitor, and the charging unit charges the capacitor if it is detected that the first input signal and the second input signal are differential signals;

[0020] The first end of the capacitor is connected to the signal output module, and if the voltage of the capacitor is higher than a first threshold voltage, the signal output module outputs the first level signal;

[0021] If the voltage of the capacitor is lower than the first threshold voltage and higher than the second threshold voltage, the signal output module outputs the second level signal.

[0022] Optionally, the charging unit includes a first charging transistor, a second charging transistor, a third charging transistor and a fourth charging transistor;

[0023] The control electrode and the first electrode of the first charging transistor are connected to the third end of the first signal conversion module, and the control electrode of the first charging transistor is connected to the control electrode of the second charging transistor;

[0024] A first electrode of the second charging transistor is connected to a third terminal of the second signal conversion module, and a second electrode of the second charging transistor is connected to a second electrode of the first charging transistor;

[0025] The control electrode and the first electrode of the third charging transistor are connected to the third end of the second signal conversion module, the control electrode of the third charging transistor is connected to the control electrode of the fourth charging transistor, and the second electrode of the third charging transistor is connected to the second electrode of the second charging transistor;

[0026] The first electrode of the fourth charging transistor is connected to the first end of the signal output module, the second electrode of the fourth charging transistor is connected to the second electrode of the third charging transistor, and the fourth charging transistor is used to amplify the current received by the third charging transistor.

[0027] Optionally, the ratio of the current amplification factors of the first charging transistor and the second charging transistor is 1:1, and the ratio of the current amplification factors of the third charging transistor and the fourth charging transistor is 1:N, wherein N>0.

[0028] Optionally, the signal detection module further includes a bias unit, two ends of the bias unit are respectively connected to the first end and the second end of the capacitor, and the bias unit generates a bias current for the capacitor.

[0029] Optionally, the bias unit includes a second current source and a bias resistor;

[0030] Two ends of the second current source are respectively connected to the first end and the second end of the capacitor;

[0031] Two ends of the bias resistor are connected to the first end and the second end of the capacitor respectively.

[0032] Optionally, the signal output module includes a Schmitt trigger, the input end of the Schmitt trigger is connected to the third end of the signal detection module, and the output end of the Schmitt trigger is used to output the first level signal or the second level signal under the control of the signal detection module.

[0033] Optionally, the first filtering module includes a first filtering resistor and a first filtering capacitor;

[0034] A first end of the first filter resistor receives the first input signal, and a second end of the first filter resistor is connected to a first end of the first signal conversion module;

[0035] Two ends of the first filter capacitor are respectively connected to the first end of the first signal conversion module and the ground.

[0036] Optionally, the second filtering module includes a second filtering resistor and a second filtering capacitor;

[0037] A first end of the second filter resistor receives the second input signal, and a second end of the second filter resistor is connected to a second end of the second signal conversion module;

[0038] Two ends of the second filter capacitor are respectively connected to the second end of the second signal conversion module and the ground.

[0039] Optionally, the differential demodulation circuit further includes a first current source, one end of the first current source is respectively connected to the fourth end of the first signal conversion module and the fourth end of the second signal conversion module, and the other end of the first current source is connected to the ground.

[0040] According to a second aspect of the present invention, there is provided a receiving end circuit, comprising a first capacitor, a second capacitor, M amplifiers, and the differential demodulation circuit according to the first aspect of the present invention and its optional solutions, wherein M≥1;

[0041] The M amplifiers are connected in series, and the first input terminal and the second input terminal of the first amplifier along the signal transmission direction are connected to the first capacitor and the second capacitor respectively;

[0042] The first output terminal and the second output terminal of the Mth amplifier along the signal transmission direction respectively output the first input signal and the second input signal to the differential demodulation circuit.

[0043] Optionally, the first input terminal and the second input terminal of at least one of the amplifiers are connected to the first clamping module and the second clamping module respectively.

[0044] Optionally, the first clamping module includes a first clamping diode and a second clamping diode, and the second clamping module includes a third clamping diode and a fourth clamping diode;

[0045] The anode of the first clamping diode is connected to the ground, and the cathode of the first clamping diode is connected to the first input terminal of the corresponding amplifier;

[0046] The anode of the second clamping diode is connected to the first input terminal of the corresponding amplifier, and the cathode of the second clamping diode is connected to the ground;

[0047] The anode of the third clamping diode is connected to the ground, and the cathode of the third clamping diode is connected to the second input terminal of the corresponding amplifier;

[0048] The anode of the fourth clamping diode is connected to the second input terminal of the corresponding amplifier, and the cathode of the fourth clamping diode is connected to the ground.

[0049] Optionally, the first clamping module includes a first clamping transistor, and the second clamping module includes a second clamping transistor;

[0050] The control electrode and the first electrode of the first clamping transistor are connected to the first input terminal of the corresponding amplifier, and the second electrode of the first clamping transistor is grounded;

[0051] The control electrode and the first electrode of the second clamping transistor are connected to the second input terminal of the corresponding amplifier, and the second electrode of the second clamping transistor is grounded.

[0052] Optionally, the first clamping module further includes a third clamping transistor, and the second clamping module further includes a fourth clamping transistor;

[0053] The control electrode and the first electrode of the third clamping transistor are connected to the ground, and the second electrode of the third clamping transistor is connected to the first input terminal of the corresponding amplifier;

[0054] The control electrode and the first electrode of the fourth clamping transistor are connected to the ground, and the second electrode of the fourth clamping transistor is connected to the second input terminal of the corresponding amplifier.

[0055] Optionally, any one of the amplifiers includes a first amplifying transistor, a second amplifying transistor, an isolation capacitor, a third current source, a fourth current source and a load unit.

[0056] The control electrode of the first amplifying transistor is connected to the first output terminal or the first capacitor of the previous amplifier along the signal transmission direction, the first electrode of the first amplifying transistor is connected to the first input terminal or the first input node of the next amplifier along the signal transmission direction, and the second electrode of the first amplifying transistor is connected to the first end of the third current source;

[0057] The control electrode of the second amplifying transistor is connected to the second output terminal or the second capacitor of the previous amplifier along the signal transmission direction, the first electrode of the second amplifying transistor is connected to the second input terminal or the second input node of the next amplifier along the signal transmission direction, and the second electrode of the second amplifying transistor is connected to the first end of the fourth current source;

[0058] The second end of the third current source is connected to the second end of the fourth current source;

[0059] Two ends of the isolation capacitor are connected to the second electrode of the first amplifying transistor and the second electrode of the second amplifying transistor respectively;

[0060] Two ends of the load unit are respectively connected to the first electrode of the first amplifying transistor and the first electrode of the second amplifying transistor, and the load unit provides a load for the amplifier.

[0061] The present invention provides a differential demodulation circuit and a receiving end circuit, wherein in the differential demodulation circuit, a signal detection module can determine whether a first input signal and a second input signal are differential signals by obtaining a first target signal and a second target signal, and control a signal output module to output a corresponding level, thereby realizing demodulation of the differential signal. This is different from the demodulation circuit solution in the prior art, and provides a technical basis for more application environments.

[0062] In an optional solution of the present invention, clamping modules are respectively added to the input ends of the receiving end circuit, so that the voltage at the input end of the receiving end circuit is within the rated voltage of various devices, thereby protecting the devices in the circuit.

[0063] In an optional solution of the present invention, an isolation capacitor is used in the amplifier, and the isolation capacitor is coupled to the common-source amplifier to improve the common-mode suppression capability of the circuit. When the signal frequency does not reach the carrier frequency, the isolation capacitor is equivalent to an open circuit, and the amplifier has the ability to suppress changes in the common-mode level, thereby achieving response only to high-frequency signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0065] Figure 1 FIG. 1 is a schematic diagram of a differential demodulation circuit according to an embodiment of the present invention. Figure 1 ;

[0066] Figure 2 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 1 ;

[0067] Figure 3 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 2 ;

[0068] Figure 4 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 3 ;

[0069] Figure 5 is a signal waveform diagram of a differential demodulation circuit in one embodiment of the present invention;

[0070] Figure 6 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 4 ;

[0071] Figure 7 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 5 ;

[0072] Figure 8 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 6 ;

[0073] Fig. 9 FIG. 1 is a schematic diagram of a differential demodulation circuit according to an embodiment of the present invention. Figure 2 ;

[0074] Fig.10 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 7 ;

[0075] Fig.11 FIG. 1 is a circuit diagram of a differential demodulation circuit in an embodiment of the present invention. Figure 8 ;

[0076] Fig.12 FIG. 1 is a schematic diagram of the structure of a receiving end circuit in one embodiment of the present invention. Figure 1 ;

[0077] Fig.13 is a signal waveform diagram of a receiving end circuit in one embodiment of the present invention;

[0078] Fig.14 It is a partial structural diagram of a receiving end circuit in one embodiment of the present invention;

[0079] Fig.15 FIG. 1 is a schematic diagram of a portion of a receiving circuit in an embodiment of the present invention. Figure 1 ;

[0080] Fig.16 FIG. 1 is a schematic diagram of a portion of a receiving circuit in an embodiment of the present invention. Figure 2 ;

[0081] Fig.17 FIG. 1 is a schematic diagram of a portion of a receiving circuit in an embodiment of the present invention. Figure 3 ;

[0082] Fig.18 Schematic diagram of an amplifier circuit in one embodiment of the present invention. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0084] In the description of the specification of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0085] In the description of the present specification, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0086] In the description of the present invention, "plurality" means a plurality, such as two, three, four, etc., unless otherwise clearly and specifically defined.

[0087] In the description of the present invention, unless otherwise clearly specified and limited, the term "connection" and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0088] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0089] Please refer to Figure 1 , the differential demodulation circuit 11 comprises: a first filtering module 111, a second filtering module 112, a first signal conversion module 113, a second signal conversion module 114, a signal detection module 115 and a signal output module 116;

[0090] The first filtering module 111 is used to filter the first input signal VINP and feed it back to the first end of the first signal conversion module 113; the second filtering module 112 is used to filter the second input signal VINN and feed it back to the second end of the first signal conversion module 113;

[0091] The third end of the first signal conversion module 113 is connected to the first end of the signal detection module 115, and is used to convert the filtered first input signal and the filtered second input signal into a single-ended first target signal after amplification, and feed the first target signal back to the signal detection module 115;

[0092] The first end and the second end of the second signal conversion module 114 are respectively connected to the first input signal VINP and the second input signal VINN, and the third end of the second signal conversion module 114 is connected to the second end of the signal detection module 115, for amplifying the first input signal VINP and the second input signal VINN, converting them into a single-ended second target signal, and feeding back the second target signal to the signal detection module 115;

[0093] The output end of the signal detection module 115 is connected to the signal output module 116, and the signal output module is used to:

[0094] If it is detected that the first input signal VINP and the second input signal VINN are differential signals according to the first target signal and the second target signal, the signal output module 116 is controlled to output a first level signal to a terminal at the receiving end;

[0095] If the first input signal VINP and the second input signal VINN are non-differential signals according to the first target signal and the second target signal, the signal output module 116 is controlled to output a second level signal to the terminal at the receiving end.

[0096] The first filtering module 111 and the second filtering module 112 can filter out the differential signal in the first input signal and the second input signal, thereby making the signals output by the first signal conversion module 113 and the second signal conversion module 114 different.

[0097] In one example, when the first input signal VINP and the second input signal VINN are differential signals, since the first target signal and the second target signal received by the signal detection module 115 are different, the signal detection module 115 will output a current, so that the voltage at the input end of the signal output module 116 increases, and when the voltage reaches a certain value, the signal output module 116 outputs a first level signal;

[0098] When the first input signal VINP and the second input signal VINN are non-differential signals, since the first target signal and the second target signal received by the signal detection module 115 are the same, the signal detection module 115 will not output current, so that the voltage at the input end of the signal output module 116 is low, and the signal output module 116 outputs a second level signal.

[0099] In one example, the first level signal is a high level and the second level signal is a low level; in another example, the first level signal is a low level and the second level signal is a high level; it can be seen that the size relationship between the first level signal and the second level signal is related to the specific design of the signal output module 116, and the signal output module 116 can be designed according to actual conditions.

[0100] As described above, the signal detection module 115 can determine whether the first input signal VINP and the second input signal VINN are differential signals by obtaining the first target signal and the second target signal, and control the signal output module 116 to output the corresponding level, thereby realizing the demodulation of the differential signal. This is different from the existing demodulation circuit solutions and provides a technical basis for more application environments.

[0101] Please refer to Figure 2 , In one implementation, the first signal conversion module 113 includes a first transistor M1 and a second transistor M2;

[0102] The control electrode of the first transistor M1 is connected to the first end of the first filtering module 111, the first electrode of the first transistor M1 is connected to the first electrode of the second transistor M2 and the first end of the signal detection module 115, and the second electrode of the first transistor M1 is connected to the second electrode of the second transistor M2;

[0103] A control electrode of the second transistor M2 is connected to a first end of the second filtering module 112 .

[0104] Please refer to Figure 3 , In one implementation, the second signal conversion module 114 includes a third transistor M3 and a fourth transistor M4;

[0105] The control electrode of the third transistor M3 is connected to the first input signal VINP, the first electrode of the third transistor M3 is connected to the first electrode of the fourth transistor M4 and the first end of the signal detection module 115, and the second electrode of the third transistor M3 is connected to the second electrode of the fourth transistor M4;

[0106] The control electrode of the fourth transistor M3 is connected to the second input signal VINN.

[0107] Please refer to Figure 4In one embodiment, the signal detection module 115 includes a charging unit 1151 and a capacitor Cr.

[0108] The first end of the charging unit 1151 is connected to the third end of the first signal conversion module 113, the second end of the charging unit 1151 is connected to the third end of the second signal conversion module 114, the output end of the charging unit 1151 is connected to the first end of the capacitor Cr, and the charging unit 1151 charges the capacitor Cr if it is detected that the first input signal VINP and the second input signal VINN are differential signals;

[0109] The first end of the capacitor Cr is connected to the signal output module 116. If the voltage of the capacitor Cr is higher than the first threshold voltage, the signal output module 116 outputs a first level signal.

[0110] If the voltage of the capacitor Cr is lower than the first threshold voltage and higher than the second threshold voltage, the signal output module 116 outputs a second level signal. Furthermore, the output signal VOUT of the signal output module 116 includes the second level signal and the first level signal.

[0111] Combine the following Figure 4 and Figure 5 , describing the working principle of the charging unit 1151 and the capacitor Cr in one embodiment:

[0112] The signal waveform corresponding to VINP is the signal waveform corresponding to the first input signal, the signal waveform corresponding to VINN is the signal waveform corresponding to the second input signal, the signal waveform corresponding to VDEM is the signal waveform corresponding to the output end of the charging unit 1151, and the signal waveform corresponding to VOUT is the signal waveform corresponding to the output signal of the signal output module 116; the value of the dotted line corresponding to Vth1 is the first threshold voltage, and the value of the dotted line corresponding to Vth2 is the second threshold voltage;

[0113] When the first input signal VINP and the second input signal VINN are differential signals, excess current flows out of the charging unit 1151 to charge the capacitor Cr. At time t1, the voltage across the capacitor Cr reaches the first threshold voltage Vth1. At this time, the output signal VOUT of the signal output module 116 begins to flip and becomes a first level signal.

[0114] Please refer to Figure 6 , the charging unit 1151 includes a first charging transistor M5, a second charging transistor M6, a third charging transistor M7 and a fourth charging transistor M8;

[0115] The control electrode and the first electrode of the first charging transistor M5 are connected to the third end of the first signal conversion module 113, and the control electrode of the first charging transistor M5 is connected to the control electrode of the second charging transistor M6;

[0116] A first electrode of the second charging transistor M6 is connected to a third terminal of the second signal conversion module 114, and a second electrode of the second charging transistor M6 is connected to a second electrode of the first charging transistor M5;

[0117] The control electrode and the first electrode of the third charging transistor M7 are connected to the third end of the second signal conversion module 114, the control electrode of the third charging transistor M7 is connected to the control electrode of the fourth charging transistor M8, and the second electrode of the third charging transistor M7 is connected to the second electrode of the second charging transistor M6;

[0118] A first electrode of the fourth charging transistor M8 is connected to the first end of the capacitor Cs, a second electrode of the fourth charging transistor is connected to the second electrode of the third charging transistor M7, and the fourth charging transistor M8 is used to amplify the current received from the third charging transistor M7.

[0119] In one implementation, the ratio of the current amplification factors of the first charging transistor M5 to the second charging transistor M6 is 1:1, and the ratio of the current amplification factors of the third charging transistor M7 to the fourth charging transistor M8 is 1:N, where N>0.

[0120] Where N>0 can be understood as:

[0121] When 0<N<1, the current amplification factor of the third charging transistor M7 is greater than the current amplification factor of the fourth charging transistor M8;

[0122] When N=1, the current amplification factor of the third charging transistor M7 is the same as the current amplification factor of the fourth charging transistor M8;

[0123] When N>1, the current amplification factor of the third charging transistor M7 is smaller than the current amplification factor of the fourth charging transistor M8.

[0124] In one example, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 have the same size (which can be understood as the same current amplification factor). When the first input signal VINP and the second input signal VINN are differential signals, the first filter module 111 and the second filter module 112 will filter out the differential signal, and then the differential signal is amplified only in the third transistor M3 and the fourth transistor M4. Due to the current mirror relationship between the first charging transistor M5 and the second charging transistor M6, there will be excess current flowing into the third charging transistor M7, and the corresponding fourth charging transistor M8 will also have current, and the capacitor Cr starts to charge;

[0125] When the first input signal VINP and the second input signal VINN are non-differential signals, the currents flowing to the first charging transistor M5 and the second charging transistor M6 are the same, and no additional current flows into the third charging transistor M7, and the capacitor Cr starts to discharge.

[0126] The transistors therein may be NFETs, i.e., pairs of complementary N-channel MOSFETs, or may be PFETs, i.e., pairs of complementary P-channel MOSFETs. Regardless of NFET or PFET, the control electrode of the transistor may be understood as the gate of the field effect transistor, and the first electrode and the second electrode of the transistor may be understood as the source and the drain of the field effect transistor.

[0127] Please refer to Figure 7 , In one implementation, the first filtering module 111 includes a first filtering resistor R1 and a first filtering capacitor C1;

[0128] A first end of the first filter resistor R1 receives the first input signal VINP, and a second end of the first filter resistor R1 is connected to a first end of the first signal conversion module 113;

[0129] Two ends of the first filter capacitor C1 are respectively connected to a first end of the first signal conversion module 113 and the ground.

[0130] In one implementation, the second filtering module 112 includes a second filtering resistor R2 and a second filtering capacitor C2;

[0131] A first end of the second filter resistor R2 receives the second input signal VINN, and a second end of the second filter resistor R2 is connected to a second end of the second signal conversion module 114;

[0132] Two ends of the second filter capacitor C2 are connected to the second end of the second signal conversion module 114 and the ground respectively.

[0133] The above filter resistor and filter capacitor can filter out the differential signal at the input end of the differential demodulation circuit, thereby achieving the purpose of differential demodulation.

[0134] Please refer to Figure 8 In one embodiment, the signal output module 116 includes a Schmitt trigger U1, the input end of the Schmitt trigger U1 is connected to the third end of the signal detection module 115, and the output end of the Schmitt trigger U1 is used to output the output signal VOUT under the control of the signal detection module.

[0135] In one example, the Schmitt trigger U1 can be replaced with other devices with level conversion and output functions to convert the slowly rising or falling voltage signal during the charging and discharging process of the capacitor Cr into a square wave signal.

[0136] Please refer to Fig. 9 The differential demodulation circuit 11 further includes a first current source I1, one end of the first current source I1 is respectively connected to the fourth end of the first signal conversion module 113 and the fourth end of the second signal conversion module 114, and the other end of the first current source I1 is connected to the ground.

[0137] The first current source provides bias current for the first signal conversion module 113 and the second signal conversion module 114 .

[0138] Please refer to Fig.10 The signal detection module 115 further includes a bias unit 1152, two ends of the bias unit 1152 are respectively connected to the first end and the second end of the capacitor Cr, and the bias unit 1152 generates a bias current for the capacitor Cr.

[0139] Please refer to Figure 5 and Fig.10 The bias unit 1152 can also realize the discharge function of the capacitor Cr. When the first input signal VINP and the second input signal VINN are non-differential signals, the bias unit 112 and the capacitor Cr form a discharge loop, and the capacitor Cr starts to discharge. At time t2, after the voltage across the capacitor Cr drops to the second threshold voltage Vth2, the output signal VOUT of the signal output module 116 flips again and becomes a second level signal.

[0140] Please refer to Fig.11 , the bias unit 1152 includes a second current source I2 and a bias resistor R3;

[0141] Two ends of the second current source I2 are respectively connected to the first end and the second end of the capacitor Cr;

[0142] Two ends of the bias resistor R3 are connected to the first end and the second end of the capacitor Cr respectively.

[0143] In one example, the second current source I2 may be designed to be process and temperature dependent, thereby reducing the impact of process and temperature variations on transmission delay in the circuit.

[0144] Please refer to Fig.12 , a receiving end circuit, comprising a first capacitor, a second capacitor, M amplifiers and the differential demodulation circuit described above, wherein M≥1;

[0145] The M amplifiers are connected in series, and the first amplifier along the signal transmission direction (such as Fig.12 A first input terminal and a second input terminal of the leftmost amplifier) ​​are connected to the first capacitor C3 and the second capacitor C4 respectively;

[0146] The Mth amplifier along the signal transmission direction (such as Fig.12 The first output terminal and the second output terminal of the rightmost amplifier in the differential demodulation circuit respectively output the first input signal and the second input signal to the differential demodulation circuit.

[0147] The M amplifiers perform M-stage amplification on the received signal.

[0148] Please refer to Fig.13 The waveform corresponding to DATA is the waveform of the information in the process of signal sending and receiving, the waveform corresponding to DRVP is the signal waveform connected to the first input end of the receiving end circuit, and the waveform corresponding to DRVN is the signal waveform connected to the second input end of the receiving end circuit.

[0149] Please refer to Fig.14 The first input terminal and the second input terminal of at least one of the amplifiers are connected to the first clamping module 13 and the second clamping module 14 respectively.

[0150] In the above implementations, clamping modules are respectively added to the input ends of the receiving end circuit, so that the voltage at the input end of the receiving end circuit is within the rated voltage of various components, thereby protecting the components in the circuit and improving the stability of the circuit.

[0151] Please refer to Fig.15 In one embodiment, the first clamping module 13 includes a first clamping diode D1 and a second clamping diode D2, and the second clamping module 14 includes a third clamping diode D3 and a fourth clamping diode D4;

[0152] The anode of the first clamping diode D1 is connected to the ground, and the cathode of the first clamping diode D1 is connected to the first input terminal of the corresponding amplifier;

[0153] The anode of the second clamping diode D2 is connected to the first input terminal of the corresponding amplifier, and the cathode of the second clamping diode D2 is connected to the ground;

[0154] The anode of the third clamping diode D3 is connected to the ground, and the cathode of the third clamping diode D3 is connected to the second input terminal of the corresponding amplifier;

[0155] The anode of the fourth clamping diode D4 is connected to the second input terminal of the corresponding amplifier, and the cathode of the fourth clamping diode D4 is connected to the ground. Fig.16 In one implementation, the first clamping module 13 includes a first clamping transistor N1, and the second clamping module 14 includes a second clamping transistor N2;

[0156] The control electrode and the first electrode of the first clamping transistor N1 are connected to the first input terminal of the corresponding amplifier 12, and the second electrode of the first clamping transistor N1 is grounded;

[0157] The control electrode and the first electrode of the second clamping transistor N2 are connected to the second input terminal of the corresponding amplifier 12, and the second electrode of the second clamping transistor N2 is grounded.

[0158] In the above implementation, when the signal transmitting end has a large common-mode level change to the receiving end circuit, if the signal transmitting end injects current to the receiving end circuit through the first capacitor C3 and the second capacitor C4, the first clamping transistor N1 and the first clamping transistor N2 connected to the gate and drain can clamp the voltage; if the signal transmitting end draws current to the receiving end circuit through the first capacitor C3 and the second capacitor C4, the body diodes of the first clamping transistor N1 and the first clamping transistor N2 can clamp the voltage. This ensures that the voltage seen by the receiving end does not exceed the rated voltage that the device can withstand.

[0159] The current injection can be understood as the current from the signal sending end to the receiving end circuit, and the current extraction can be understood as the current from the receiving end circuit to the signal sending end.

[0160] Please refer to Fig.17 , the first clamping module 13 further includes a third clamping transistor N3, and the second clamping module 14 further includes a fourth clamping transistor N4;

[0161] The control electrode and the first electrode of the third clamping transistor N3 are connected to the ground, and the second electrode of the third clamping transistor N3 is connected to the first input terminal of the corresponding amplifier 12;

[0162] The control electrode and the first electrode of the fourth clamp transistor N4 are connected to the ground, and the second electrode of the fourth clamp transistor N4 is connected to the second input terminal of the corresponding amplifier 12 .

[0163] In the above implementation, when the signal transmission end has a large common mode level change to the receiving end circuit:

[0164] If the signal transmitting end injects current into the receiving end circuit through the first capacitor C3 and the second capacitor C4, the body diodes of the first clamping transistor N1 and the first clamping transistor N2 connected to the gate and drain, and the third clamping transistor N3 and the fourth clamping transistor N4 can also clamp the voltage;

[0165] If the signal transmitting end draws current from the receiving end circuit through the first capacitor C3 and the second capacitor C4, the body diodes of the first clamping transistor N1 and the first clamping transistor N2, as well as the third clamping transistor N3 and the fourth clamping transistor N4 connected to the gate and drain can clamp the voltage, thereby ensuring that the voltage seen by the receiving end does not exceed the rated voltage that the device can withstand.

[0166] Different from the examples in the above implementation modes, the gate and drain of the first clamp transistor N1 and the first clamp transistor N2 are connected and then grounded, and the gate and drain of the third clamp transistor N3 and the fourth clamp transistor N4 are connected and then respectively connected to the first input terminal and the second input terminal of the receiving end circuit. It can be seen that the first clamp transistor N1 and the third clamp transistor N3 can be interchanged, and the second clamp transistor N2 and the fourth clamp transistor N4 can be interchanged.

[0167] Please refer to Fig.18 Any one of the amplifiers includes a first amplifying transistor M9, a second amplifying transistor M10, an isolation capacitor C, a third current source I3, a fourth current source I4 and a load unit 121,

[0168] The control electrode of the first amplifying transistor M9 is connected to the first output terminal of the previous amplifier along the signal transmission direction or the first capacitor C3, the first electrode of the first amplifying transistor M9 is connected to the first input terminal or the first input node of the next amplifier along the signal transmission direction, and the second electrode of the first amplifying transistor M9 is connected to the first end of the third current source I3;

[0169] The control electrode of the second amplifying transistor M10 is connected to the second output terminal or the second capacitor of the previous amplifier along the signal transmission direction, the first electrode of the second amplifying transistor M10 is connected to the second input terminal or the second input node of the next amplifier along the signal transmission direction, and the second electrode of the second amplifying transistor M10 is connected to the first end of the fourth current source I4;

[0170] The second end of the third current source I3 is connected to the second end of the fourth current source I4;

[0171] Two ends of the isolation capacitor C are respectively connected to the second electrode of the first amplifying transistor M9 and the second electrode of the second amplifying transistor M10;

[0172] Two ends of the load unit 121 are respectively connected to the first electrode of the first amplifying transistor M9 and the first electrode of the second amplifying transistor M10 , and the load unit 121 provides a load for the amplifier 12 .

[0173] The third current source I3 and the fourth current source I4 provide bias currents for the first amplifying transistor M9 and the second amplifying transistor M10 .

[0174] In the above implementation, an isolation capacitor C is used in the amplifier, and the isolation capacitor C is coupled to the common-source amplifier to improve the common-mode suppression capability of the circuit. When the signal frequency does not reach the carrier frequency, the isolation capacitor C is equivalent to an open circuit, and the amplifier 12 has the ability to suppress changes in the common-mode level, thereby achieving only response to high-frequency signals.

[0175] In the description of this specification, the description with reference to the terms "one implementation", "one example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A differential demodulation circuit, characterized in that: include: A first filtering module, a second filtering module, a first signal conversion module, a second signal conversion module, a signal detection module and a signal output module; The first filtering module is used to filter the first input signal and feed it back to the first end of the first signal conversion module; the second filtering module is used to filter the second input signal and feed it back to the second end of the first signal conversion module; wherein the first filtering module and the second filtering module filter out the differential signal between the first input signal and the second input signal; The third end of the first signal conversion module is connected to the first end of the signal detection module, and is used to convert the filtered first input signal and the filtered second input signal into a single-ended first target signal after amplification, and feed the first target signal back to the signal detection module; The first end and the second end of the second signal conversion module are respectively connected to the first input signal and the second input signal, and the third end of the second signal conversion module is connected to the second end of the signal detection module, and is used to amplify the first input signal and the second input signal and convert them into a single-ended second target signal, and feed the second target signal back to the signal detection module; The output end of the signal detection module is connected to the signal output module, and the signal output module is used to: If it is detected that the first input signal and the second input signal are differential signals according to the first target signal and the second target signal, the signal output module is controlled to output a first level signal to a terminal at the receiving end; If it is detected that the first input signal and the second input signal are non-differential signals according to the first target signal and the second target signal, the signal output module is controlled to output a second level signal to a terminal at the receiving end.

2. The differential demodulation circuit according to claim 1, characterized in that: The first signal conversion module includes a first transistor and a second transistor; The control electrode of the first transistor is connected to the first end of the first filtering module, the first electrode of the first transistor is connected to the first electrode of the second transistor and the first end of the signal detection module, and the second electrode of the first transistor is connected to the second electrode of the second transistor; The control electrode of the second transistor is connected to the first end of the second filtering module.

3. The differential demodulation circuit according to claim 1, characterized in that: The second signal conversion module includes a third transistor and a fourth transistor; The control electrode of the third transistor is connected to the first input signal, the first electrode of the third transistor is connected to the first electrode of the fourth transistor and the first end of the signal detection module, and the second electrode of the third transistor is connected to the second electrode of the fourth transistor; The control electrode of the fourth transistor is connected to the second input signal.

4. The differential demodulation circuit according to claim 1, characterized in that: The signal detection module includes a charging unit and a capacitor. The first end of the charging unit is connected to the third end of the first signal conversion module, the second end of the charging unit is connected to the third end of the second signal conversion module, the output end of the charging unit is connected to the first end of the capacitor, and the charging unit charges the capacitor if it is detected that the first input signal and the second input signal are differential signals; The first end of the capacitor is connected to the signal output module, and if the voltage of the capacitor is higher than a first threshold voltage, the signal output module outputs the first level signal; If the voltage of the capacitor is lower than the first threshold voltage and higher than the second threshold voltage, the signal output module outputs the second level signal.

5. The differential demodulation circuit according to claim 4, characterized in that: The charging unit includes a first charging transistor, a second charging transistor, a third charging transistor and a fourth charging transistor; The control electrode and the first electrode of the first charging transistor are connected to the third end of the first signal conversion module, and the control electrode of the first charging transistor is connected to the control electrode of the second charging transistor; A first electrode of the second charging transistor is connected to a third terminal of the second signal conversion module, and a second electrode of the second charging transistor is connected to a second electrode of the first charging transistor; The control electrode and the first electrode of the third charging transistor are connected to the third end of the second signal conversion module, the control electrode of the third charging transistor is connected to the control electrode of the fourth charging transistor, and the second electrode of the third charging transistor is connected to the second electrode of the second charging transistor; The first electrode of the fourth charging transistor is connected to the first end of the signal output module, the second electrode of the fourth charging transistor is connected to the second electrode of the third charging transistor, and the fourth charging transistor is used to amplify the current received by the third charging transistor.

6. The differential demodulation circuit according to claim 5, characterized in that: The ratio of the current amplification factors of the first charging transistor to the second charging transistor is 1:1, and the ratio of the current amplification factors of the third charging transistor to the fourth charging transistor is 1:N, wherein N>0.

7. The differential demodulation circuit according to claim 4, characterized in that: The signal detection module further includes a bias unit, Two ends of the bias unit are connected to a first end and a second end of the capacitor respectively, and the bias unit generates a bias current for the capacitor.

8. The differential demodulation circuit according to claim 7, characterized in that: The bias unit includes a second current source and a bias resistor; Two ends of the second current source are respectively connected to the first end and the second end of the capacitor; Two ends of the bias resistor are connected to the first end and the second end of the capacitor respectively.

9. The differential demodulation circuit according to claim 1, characterized in that: The signal output module includes a Schmitt trigger, the input end of the Schmitt trigger is connected to the third end of the signal detection module, and the output end of the Schmitt trigger is used to output the first level signal or the second level signal under the control of the signal detection module.

10. The differential demodulation circuit according to claim 1, characterized in that: The first filtering module includes a first filtering resistor and a first filtering capacitor; A first end of the first filter resistor receives the first input signal, and a second end of the first filter resistor is connected to a first end of the first signal conversion module; Two ends of the first filter capacitor are respectively connected to the first end of the first signal conversion module and the ground.

11. The differential demodulation circuit according to claim 1, characterized in that: The second filtering module includes a second filtering resistor and a second filtering capacitor; A first end of the second filter resistor receives the second input signal, and a second end of the second filter resistor is connected to a second end of the second signal conversion module; Two ends of the second filter capacitor are respectively connected to the second end of the second signal conversion module and the ground.

12. The differential demodulation circuit according to claim 1, characterized in that: It also includes a first current source, one end of which is respectively connected to the fourth end of the first signal conversion module and the fourth end of the second signal conversion module, and the other end of the first current source is connected to the ground.

13. A receiving end circuit, characterized in that: The differential demodulation circuit comprises a first capacitor, a second capacitor, M amplifiers, and any one of claims 1 to 12, wherein M≥1; The M amplifiers are connected in series, and the first input terminal and the second input terminal of the first amplifier along the signal transmission direction are connected to the first capacitor and the second capacitor respectively; The first output terminal and the second output terminal of the Mth amplifier along the signal transmission direction respectively output the first input signal and the second input signal to the differential demodulation circuit.

14. The receiving end circuit according to claim 13, characterized in that: The first input terminal and the second input terminal of at least one of the amplifiers are connected to the first clamping module and the second clamping module respectively.

15. The receiving end circuit according to claim 14, characterized in that: The first clamping module includes a first clamping diode and a second clamping diode, and the second clamping module includes a third clamping diode and a fourth clamping diode; The anode of the first clamping diode is connected to the ground, and the cathode of the first clamping diode is connected to the first input terminal of the corresponding amplifier; The anode of the second clamping diode is connected to the first input terminal of the corresponding amplifier, and the cathode of the second clamping diode is connected to the ground; The anode of the third clamping diode is connected to the ground, and the cathode of the third clamping diode is connected to the second input terminal of the corresponding amplifier; The anode of the fourth clamping diode is connected to the second input terminal of the corresponding amplifier, and the cathode of the fourth clamping diode is connected to the ground.

16. The receiving end circuit according to claim 14, characterized in that: The first clamping module includes a first clamping transistor, and the second clamping module includes a second clamping transistor; The control electrode and the first electrode of the first clamping transistor are connected to the first input terminal of the corresponding amplifier, and the second electrode of the first clamping transistor is grounded; The control electrode and the first electrode of the second clamping transistor are connected to the second input terminal of the corresponding amplifier, and the second electrode of the second clamping transistor is grounded.

17. The receiving end circuit according to claim 16, characterized in that: The first clamping module further includes a third clamping transistor, and the second clamping module further includes a fourth clamping transistor; The control electrode and the first electrode of the third clamping transistor are connected to the ground, and the second electrode of the third clamping transistor is connected to the first input terminal of the corresponding amplifier; The control electrode and the first electrode of the fourth clamping transistor are connected to the ground, and the second electrode of the fourth clamping transistor is connected to the second input terminal of the corresponding amplifier.

18. The receiving end circuit according to claim 13, characterized in that: Any one of the amplifiers includes a first amplifying transistor, a second amplifying transistor, an isolation capacitor, a third current source, a fourth current source and a load unit. The control electrode of the first amplifying transistor is connected to the first output terminal or the first capacitor of the previous amplifier along the signal transmission direction, the first electrode of the first amplifying transistor is connected to the first input terminal or the first input node of the next amplifier along the signal transmission direction, and the second electrode of the first amplifying transistor is connected to the first end of the third current source; The control electrode of the second amplifying transistor is connected to the second output terminal or the second capacitor of the previous amplifier along the signal transmission direction, the first electrode of the second amplifying transistor is connected to the second input terminal or the second input node of the next amplifier along the signal transmission direction, and the second electrode of the second amplifying transistor is connected to the first end of the fourth current source; The second end of the third current source is connected to the second end of the fourth current source; Two ends of the isolation capacitor are connected to the second electrode of the first amplifying transistor and the second electrode of the second amplifying transistor respectively; Two ends of the load unit are respectively connected to the first electrode of the first amplifying transistor and the first electrode of the second amplifying transistor, and the load unit provides a load for the amplifier.

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