A SoC dual-core system clock synchronization method and device

Abstract

The present application discloses a SoC dual-core system clock synchronization method and device, the method comprising: when the real-time core starts the interrupt, the first system clock and verification information are sent to the shared memory through the real-time core, and the first clock synchronization flag is set at the same time; when the management core detects the existence of the first clock synchronization flag in the shared memory, the first system clock and verification information in the shared memory are obtained through the management core; after the first system clock is reversely verified according to the verification information, the clock data of the management core is updated with the first system clock to achieve clock synchronization. The present application can solve the technical problem in the prior art that the management core cannot save the system clock after the clock is restarted, resulting in the product's punctuality accuracy being affected.

Description

Technical Field

[0001] The present application relates to the technical field of clock synchronization, and in particular to a method and device for clock synchronization of a SoC dual-core system. Background Art

[0002] With the rapid development of distribution networks, there are more stringent requirements for the real-time detection capabilities of operating equipment and the reliability of protecting the operation of automation equipment. The System on Chip dual-core system integrates two ARM processors and FPGA. Data exchange is completed inside the chip, and they work together efficiently, which can effectively improve the reliability of data exchange, reduce the complexity of the single board, and reduce power consumption.

[0003] At present, most distribution automation terminals use clock chips for clock timekeeping. The first core of the dual-core is the management core, which runs on the operating system and is responsible for data interaction with the master station and advanced applications; the second core is the real-time core, which is responsible for processing high real-time tasks. When performing standardized timekeeping accuracy testing in the system, it is necessary to obtain the management core clock, but the RTC clock chip runs on the real-time core, and the management core only has a soft clock. After power outage and restart, the system clock of the management core cannot be saved after power outage, so it cannot meet the timekeeping accuracy requirements of distribution terminal products. Summary of the invention

[0004] The present application provides a SoC dual-core system clock synchronization method and device, which are used to solve the technical problem in the prior art that the management core cannot save the system clock after the clock is restarted, resulting in the product's timekeeping accuracy being affected.

[0005] In view of this, the first aspect of the present application provides a SoC dual-core system clock synchronization method, comprising:

[0006] When the real-time core starts interruption, the first system clock and verification information are sent to the shared memory through the real-time core, and the first clock synchronization flag is set at the same time;

[0007] When the management core periodically detects that the first clock synchronization flag exists in the shared memory, acquiring the first system clock and the verification information in the shared memory through the management core;

[0008] After the first system clock passes the reverse verification according to the verification information, the first system clock is used to update the clock data of the management core to achieve clock synchronization.

[0009] Optionally, when the real-time core enables interruption, the first system clock and verification information are sent to the shared memory through the real-time core, and a first clock synchronization flag is set, which also includes:

[0010] After completing format verification of the format of the master station clock received from the master station by the management check, the master station clock is stored in the shared memory and a second clock synchronization flag is set;

[0011] When the real-time core detects the presence of a second clock synchronization flag in the shared memory, acquiring the master station clock in the shared memory through the real-time core;

[0012] The master station clock is used to update the clock data of the real-time core to achieve clock synchronization.

[0013] Optionally, when the real-time core enables interruption, the first system clock and verification information are sent to the shared memory through the real-time core, and a first clock synchronization flag is set, which also includes:

[0014] After the SoC dual-core system is powered on, initial system clock settings are performed on the management core and the real-time core respectively.

[0015] Optionally, after the SoC dual-core system is powered on, respectively performing initial system clock settings on the management core and the real-time core includes:

[0016] The real-time core sends the RTC clock obtained on the RTC chip to the shared memory, so that the management core sets the initial system clock according to the RTC clock obtained in the shared memory to obtain the first initial system clock, and the real-time core uses the RTC clock as the second initial system clock.

[0017] Optionally, the sending, by the real-time core, the RTC clock acquired on the RTC chip to the shared memory further includes:

[0018] If the real-time core fails to obtain the RTC clock on the RTC chip, the management core uses the Linux system clock in the shared memory maintained by the real-time core as the first initial system clock, and the real-time core uses the Linux system clock in the shared memory as the second initial system clock.

[0019] A second aspect of the present application provides a SoC dual-core system clock synchronization device, comprising:

[0020] A shared storage module, used for sending the first system clock and verification information to the shared memory through the real-time core when the real-time core starts interruption, and setting the first clock synchronization flag at the same time;

[0021] A first clock acquisition module, configured to acquire the first system clock and the verification information in the shared memory through the management core when the management core detects that the first clock synchronization flag exists in the shared memory;

[0022] The verification update module is used to update the clock data of the management core with the first system clock after the first system clock is reversely verified according to the verification information to achieve clock synchronization.

[0023] Optionally, also include:

[0024] A master station time synchronization module, configured to store the master station clock in the shared memory and set a second clock synchronization flag after completing format verification of the master station clock received from the master station through the management check;

[0025] A second clock acquisition module, when the real-time core detects the presence of a second clock synchronization flag in the shared memory, acquires the master station clock in the shared memory through the real-time core;

[0026] The clock update module is used to update the clock data of the real-time core using the master station clock to achieve clock synchronization.

[0027] Optionally, also include:

[0028] The initialization module is used to respectively perform initial system clock settings on the management core and the real-time core after the SoC dual-core system is powered on.

[0029] Optionally, the initialization module is specifically used for:

[0030] The real-time core sends the RTC clock obtained on the RTC chip to the shared memory, so that the management core sets the initial system clock according to the RTC clock obtained in the shared memory to obtain the first initial system clock, and the real-time core uses the RTC clock as the second initial system clock.

[0031] Optionally, also include:

[0032] The acquisition failure module is used for, if the real-time core fails to acquire the RTC clock on the RTC chip, the management core uses the Linux system clock in the shared memory maintained by the real-time core as the first initial system clock, and the real-time core uses the Linux system clock in the shared memory as the second initial system clock.

[0033] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0034] In the present application, a SoC dual-core system clock synchronization method is provided, including: when the real-time core starts the interrupt, the first system clock and verification information are sent to the shared memory through the real-time core, and the first clock synchronization flag is set at the same time; when the management core detects the presence of the first clock synchronization flag in the shared memory, the first system clock and verification information in the shared memory are obtained through the management core; after the first system clock is reversely verified according to the verification information, the clock data of the management core is updated with the first system clock to achieve clock synchronization.

[0035] The SoC dual-core system clock synchronization method provided by the present application configures a shared memory between the management core and the real-time core, stores the system clock in the real-time core through the shared memory, and the management core obtains the system clock and completes its own clock data update, thereby avoiding the clock asynchronization caused by the restart of the management core due to power failure. The clock synchronization between the real-time core and the management core ensures that the clock of the SoC dual-core system comes from the real-time core, and the timekeeping accuracy of the SoC dual-core system is ensured by verification. Therefore, the present application can solve the technical problem in the prior art that the management core cannot save the system clock after the clock restarts, resulting in the product's timekeeping accuracy being affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic flow chart of a SoC dual-core system clock synchronization method provided in an embodiment of the present application;

[0037] Figure 2 Another flowchart of a SoC dual-core system clock synchronization method provided by an embodiment of the present application;

[0038] Figure 3 A schematic diagram of the structure of a SoC dual-core system clock synchronization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] For easier understanding, see Figure 1 , Embodiment 1 of a SoC dual-core system clock synchronization method provided by the present application includes:

[0041] Step 101: When the real-time core enables interruption, the first system clock and verification information are sent to the shared memory through the real-time core, and a first clock synchronization flag is set at the same time.

[0042] Shared memory is a memory that can be accessed by both the real-time core and the management core. It can be set in advance as needed and is mainly used to store information such as clocks and related flags during the clock synchronization process. The verification information includes not only the information obtained by the real-time verification of the first system clock, but also the verification method information, which is convenient for the management core to reverse the verification and verification. The clock synchronization flag provides different states depending on whether the synchronization is completed, thereby confirming whether the clock has been acquired by the management core and the clock synchronization operation has been completed.

[0043] When the real-time core enables interruption, the soft clock in the management core cannot be saved. The real-time core sends the first system clock at this time to the shared memory and sets the first clock synchronization flag to prompt the management core to perform clock synchronization operation.

[0044] Step 102: When the management core periodically detects that there is a first clock synchronization mark in the shared memory, the management core obtains the first system clock and verification information in the shared memory.

[0045] When the management verifies that the first clock synchronization flag in the shared memory is in an unsynchronized state, the first system clock and verification information in the shared memory are obtained to obtain necessary information for the clock synchronization process of the management core.

[0046] Step 103: After the first system clock is reversely verified according to the verification information, the clock data of the management core is updated using the first system clock to achieve clock synchronization.

[0047] When the first system clock is reversed and verified according to the verification information, if the reverse verification is successful, the synchronization operation of the management core clock can be performed, and the clock data of the management core is updated with the first system clock, thereby completing the synchronization task.

[0048] The meaning of clock synchronization is timekeeping test. When the master station needs to perform timekeeping test on the dual-core system, the real-time core stores the clock of the timing device in an independent storage point. The management core updates the clock data through the acquired clock to achieve clock synchronization. The master station can perform more accurate timekeeping test on the dual-core system. Reverse verification can also further ensure the accuracy of the clock.

[0049] The SoC dual-core system clock synchronization method provided in the embodiment of the present application configures a shared memory between the management core and the real-time core, stores the system clock in the real-time core through the shared memory, and the management core obtains the system clock and completes its own clock data update, thereby avoiding the clock asynchronization caused by the restart of the management core due to power failure. The clock synchronization of the real-time core and the management core ensures that the clock of the SoC dual-core system comes from the real-time core, and the timekeeping accuracy of the SoC dual-core system is ensured by verification. Therefore, the embodiment of the present application can solve the technical problem in the prior art that the management core cannot save the system clock after the clock restarts, resulting in the product's timekeeping accuracy being affected.

[0050] The above is an embodiment of a SoC dual-core system clock synchronization method provided by the present application, and the following is another embodiment of a SoC dual-core system clock synchronization method provided by the present application.

[0051] For easier understanding, see Figure 2 The present application provides a second embodiment of a SoC dual-core system clock synchronization method, comprising:

[0052] Step 201: After the SoC dual-core system is powered on, initial system clock settings are performed on the management core and the real-time core respectively.

[0053] The clock of the management core is mainly provided by the real-time core, and the initial system clock setting process is no exception. The clock of the real-time core is provided by the RTC chip. The real-time core can obtain clock data from the RCT chip, but if the acquisition fails, the system clock in the management core Linux kernel is used to update the clocks of the real-time core and the RTC chip at the same time.

[0054] Further, step 201 includes:

[0055] The real-time core sends the RTC clock obtained on the RTC chip to the shared memory, so that the management core sets the initial system clock according to the RTC clock obtained in the shared memory to obtain the first initial system clock, and the real-time core uses the RTC clock as the second initial system clock.

[0056] RTC clock T rtc The real-time core obtains the RTC clock for the management core to complete the initial system clock setting process. The initial clock at this time is set to the first initial system clock T sys1 , and the real-time core obtains the RCT clock and completes the setting of its own clock data to the second initial system clock T sys2 .

[0057] Furthermore, it also includes:

[0058] If the real-time core fails to obtain the RTC clock on the RTC chip, the management core uses the Linux system clock in the shared memory maintained by the real-time core as the first initial system clock, and the real-time core uses the Linux system clock in the shared memory as the second initial system clock.

[0059] If the real-time core fails to obtain the RCT clock, the management core will use the system clock T in the management core Linux kernel. sys The real-time core acquires and updates the system clock of the real-time core, obtains the second initial system clock, and performs punctual management on the acquired Linux system clock, i.e., clock maintenance operation. The maintained Linux system clock is then sent to the shared memory for the management core to acquire and update the system clock in the management core, thereby ensuring that the clock of the management core is always synchronized with the real-time core, i.e., the first initial system clock is always the synchronized clock maintained by the real-time core.

[0060] Step 202: After completing format verification of the master station clock received from the master station through the management check, the master station clock is stored in the shared memory and a second clock synchronization flag is set.

[0061] When receiving the master station clock synchronization signal, you first need to process and parse the synchronization message frame to obtain the master station clock T sent by the master station. mst , perform clock format verification on the parsed clock data. After the verification is completed, the master station clock can be sent to the shared memory for storage through the management core, and the corresponding second clock synchronization flag can be set at the same time.

[0062] Step 203: When the real-time core detects that there is a second clock synchronization flag in the shared memory, the master station clock in the shared memory is obtained through the real-time core.

[0063] The real-time core will also periodically detect the shared memory to determine whether the second clock synchronization flag is in an unsynchronized state. If so, the master station clock in the shared memory is obtained.

[0064] Step 204: Use the master station clock to update the clock data of the real-time core to achieve clock synchronization.

[0065] The real-time core uses the master station clock to update its own clock data, and also needs to update the master station clock value in the RTC chip.

[0066] It can be understood that the above is the time synchronization process from the master station to the management core and the real-time core. Before the clock synchronization from the real-time core to the management core is performed, the clocks of the management core and the real-time core are first sent down by the master station, and then the real-time core maintains the clock to achieve the purpose of timekeeping. However, in the actual process, the time synchronization of the master station does not only occur before the timekeeping process, but can also occur during the timekeeping process, that is, during the process of the real-time core maintaining the management core clock, the master station can send the system clock to the management core and the real-time core from time to time, and update the clocks in the management core, the real-time core and the RTC chip. The specific process is similar to the above operation and will not be repeated here.

[0067] Step 205: When the real-time core enables interruption, the first system clock and verification information are sent to the shared memory through the real-time core, and the first clock synchronization flag is set at the same time.

[0068] Step 206: When the management core periodically detects that there is a first clock synchronization mark in the shared memory, the management core obtains the first system clock and verification information in the shared memory.

[0069] Step 207: After the first system clock is reversely verified according to the verification information, the clock data of the management core is updated using the first system clock to achieve clock synchronization.

[0070] For the detailed process of step 205-step 207, please refer to step 101-step 103. It should be noted that the real-time core is interrupted regularly. When the interrupt is turned on, the real-time core needs the current system clock, that is, the running time of the first system clock, so the real-time core writes the first system clock into the shared memory and sets the corresponding synchronization flag. The management core will first detect the synchronization flag and determine whether a synchronization operation is required. If so, it will read the first system clock and the verification information. After the verification, the local clock synchronization operation will be performed, that is, the management core clock data will be updated.

[0071] The clock synchronization operation is to perform a timekeeping test. Taking the timing device as the benchmark, the timing device and the device under test trigger an external hard contact at the same time, obtain the clocks of the two devices, and compare the clocks to get the clock error. The specific operation process can be achieved through existing technology and will not be repeated here.

[0072] The above is an embodiment of a SoC dual-core system clock synchronization method provided by the present application, and the following is an embodiment of a SoC dual-core system clock synchronization device provided by the present application.

[0073] For easier understanding, see Figure 3 The present application provides an embodiment of a SoC dual-core system clock synchronization device, including:

[0074] The shared storage module 301 is used to send the first system clock and verification information to the shared memory through the real-time core when the real-time core starts interruption, and set the first clock synchronization flag at the same time;

[0075] A first clock acquisition module 302 is used to acquire the first system clock and verification information in the shared memory through the management core when the management core detects that there is a first clock synchronization mark in the shared memory;

[0076] The verification and updating module 303 is used to update the clock data of the management core with the first system clock after the first system clock passes the reverse verification according to the verification information, so as to achieve clock synchronization.

[0077] Furthermore, it also includes:

[0078] The master station time synchronization module 304 is used to store the master station clock in the shared memory and set the second clock synchronization flag after completing the format verification of the master station clock received from the master station through the management check;

[0079] The second clock acquisition module 305 acquires the master station clock in the shared memory through the real-time core when the real-time core detects the presence of the second clock synchronization flag in the shared memory;

[0080] The clock update module 306 is used to update the clock data of the real-time core using the master station clock to achieve clock synchronization.

[0081] Furthermore, it also includes:

[0082] The initialization module 307 is used to perform initial system clock settings for the management core and the real-time core respectively after the SoC dual-core system is powered on.

[0083] Furthermore, the initialization module 307 is specifically used for:

[0084] The real-time core sends the RTC clock obtained on the RTC chip to the shared memory, so that the management core sets the initial system clock according to the RTC clock obtained in the shared memory to obtain the first initial system clock, and the real-time core uses the RTC clock as the second initial system clock.

[0085] Furthermore, it also includes:

[0086] The acquisition failure module 308 is used for, if the real-time core fails to obtain the RTC clock on the RTC chip, the management core uses the Linux system clock in the shared memory maintained by the real-time core as the first initial system clock, and the real-time core uses the Linux system clock in the shared memory as the second initial system clock.

[0087] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0088] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0089] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0090] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for executing all or part of the steps of the method described in each embodiment of the present application through a computer device (which can be a personal computer, a server, or a network device, etc.). The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (full name in English: Read-Only Memory, English abbreviation: ROM), random access memory (full name in English: Random Access Memory, English abbreviation: RAM), disk or optical disk and other media that can store program codes.

[0091] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A SoC dual-core system clock synchronization method, characterized in that: include: After completing format verification of the master station clock received from the master station by the management check, the master station clock is stored in the shared memory and a second clock synchronization flag is set; When the real-time core detects the presence of the second clock synchronization flag in the shared memory, acquiring the master station clock in the shared memory through the real-time core; The master station clock is used to update the clock data of the real-time core to achieve clock synchronization; When the real-time core starts interruption, the first system clock and verification information are sent to the shared memory through the real-time core, and the first clock synchronization flag is set at the same time; When the management core periodically detects that the first clock synchronization flag exists in the shared memory, acquiring the first system clock and the verification information in the shared memory through the management core; After the first system clock passes the reverse verification according to the verification information, the first system clock is used to update the clock data of the management core to achieve clock synchronization.

2. The SoC dual-core system clock synchronization method according to claim 1, characterized in that: When the real-time core starts interrupting, the first system clock and the verification information are sent to the shared memory through the real-time core, and the first clock synchronization flag is set at the same time, which also includes: After the SoC dual-core system is powered on, initial system clock settings are performed on the management core and the real-time core respectively.

3. The SoC dual-core system clock synchronization method according to claim 2, characterized in that: After the SoC dual-core system is powered on, initial system clock settings are performed on the management core and the real-time core respectively, including: The real-time core sends the RTC clock obtained on the RTC chip to the shared memory, so that the management core sets the initial system clock according to the RTC clock obtained in the shared memory to obtain the first initial system clock, and the real-time core uses the RTC clock as the second initial system clock.

4. The SoC dual-core system clock synchronization method according to claim 3, characterized in that: The method of sending the RTC clock acquired on the RTC chip to the shared memory through the real-time core further includes: If the real-time core fails to obtain the RTC clock on the RTC chip, the management core uses the Linux system clock in the shared memory maintained by the real-time core as the first initial system clock, and the real-time core uses the Linux system clock in the shared memory as the second initial system clock.

5. A SoC dual-core system clock synchronization device, characterized in that: include: A master station time synchronization module, for performing format verification on the master station clock received from the master station through management verification, storing the master station clock in a shared memory, and setting a second clock synchronization flag; A second clock acquisition module, when the real-time core detects the presence of the second clock synchronization flag in the shared memory, acquires the master station clock in the shared memory through the real-time core; An updating clock module, used to update the clock data of the real-time core using the master station clock to achieve clock synchronization; A shared storage module, used for sending the first system clock and verification information to the shared memory through the real-time core when the real-time core starts interruption, and setting the first clock synchronization flag at the same time; A first clock acquisition module, configured to acquire the first system clock and the verification information in the shared memory through the management core when the management core detects that the first clock synchronization flag exists in the shared memory; The verification update module is used to update the clock data of the management core with the first system clock after the first system clock is reversely verified according to the verification information to achieve clock synchronization.

6. The SoC dual-core system clock synchronization device according to claim 5, characterized in that: Also includes: The initialization module is used to respectively perform initial system clock settings on the management core and the real-time core after the SoC dual-core system is powered on.

7. The SoC dual-core system clock synchronization device according to claim 6, characterized in that: The initialization module is specifically used for: The real-time core sends the RTC clock obtained on the RTC chip to the shared memory, so that the management core sets the initial system clock according to the RTC clock obtained in the shared memory to obtain the first initial system clock, and the real-time core uses the RTC clock as the second initial system clock.

8. The SoC dual-core system clock synchronization device according to claim 7, characterized in that: Also includes: The acquisition failure module is used for, if the real-time core fails to acquire the RTC clock on the RTC chip, the management core uses the Linux system clock in the shared memory maintained by the real-time core as the first initial system clock, and the real-time core uses the Linux system clock in the shared memory as the second initial system clock.

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