Storage device, storage system, and operating method thereof

Abstract

A storage device, a storage system, and a method of operating the same are provided. The storage device separates a plurality of keys and a plurality of values ​​corresponding to the plurality of keys, and manages the plurality of keys and the plurality of values ​​corresponding to the plurality of keys. It includes: a first controller for processing a first key and a first value corresponding to the first key; a second controller for processing a second key and a second value corresponding to the second key; and a non-volatile memory for storing the first key, the second key, the first value, and the second value, wherein the first key includes information about the second controller relating to a processing core for processing the second value after the first value.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0158449, filed on December 2, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a storage device and a method of operating the same, and more specifically, to a storage device based on key-value storage of data. Background Technology

[0003] Electronic devices can store data and operate based on the stored data. Therefore, electronic devices may include storage devices or storage systems for storing data, or may communicate with external storage devices or storage systems to store or retrieve data.

[0004] Storage devices can be classified in various ways. For example, storage devices can be classified as memory based on non-volatile memory and memory based on volatile memory. Even when power is not supplied to memory based on non-volatile memory, data will not be lost. If the power supply is interrupted, data stored in memory based on volatile memory may be lost, but memory based on volatile memory can operate much faster than memory based on non-volatile memory.

[0005] For example, storage devices can be categorized into block storage, file storage, and object storage. Block storage manages data based on physical location, file storage manages data based on logical sequence, and object storage manages data based on unique identifiers. Block storage and file storage are useful when there are large amounts of text data, while object storage can be an efficient alternative when there are large amounts of unstructured data (such as audio data, video data, etc.). Object storage stores data and metadata separately, where metadata can be stored in encapsulated form, database form, or key-value form. Examples of object storage include key-value stores that store data values ​​based on associated keys. Summary of the Invention

[0006] The inventive concept provides a storage device and a storage system that efficiently includes processor information for processing the next key within a key.

[0007] According to one aspect of the inventive concept, a storage device is provided that separates a plurality of keys and a plurality of datasets or values ​​corresponding to the plurality of keys, and manages the plurality of keys and the plurality of datasets or values ​​corresponding to the plurality of keys, the storage device comprising: a first controller configured to process a first key and a first value corresponding to the first key; a second controller configured to process a second key and a second value corresponding to the second key; and a non-volatile memory configured to store the first key, the second key, the first value, and the second value, wherein the first key includes information about the second controller relating to a processing core for processing the second value after the first value.

[0008] According to another aspect of the inventive concept, a storage device includes: a first controller configured to process a first key-value pair including a first key and a first value corresponding to the first key; a second controller configured to process a second key-value pair including a second key and a second value corresponding to the second key; and a non-volatile memory configured to store the first value and the second value in at least one first region of the non-volatile memory, and to store the first key and the second key in at least one second region of the non-volatile memory, wherein at least one of the first key-value pair and the second key-value pair respectively includes: information about which of the second controller and the first controller is configured to process the next key-value pair of the first key-value pair and the at least one of the second key-value pair.

[0009] According to one aspect of the inventive concept, a method of operating a storage system is provided, the method comprising: receiving data; receiving a first key and a first value corresponding to the first key from the received data; extracting a second key and a second value corresponding to the second key from the received data; including first processing core information about a processing core for processing the second value after the first value in the first key; and storing the first key including the first processing core information in a non-volatile memory.

[0010] According to another aspect of the inventive concept, a method of operating a storage system includes: receiving data; extracting a first key-value pair from the received data, including a first key and a first value corresponding to the first key; extracting a second key-value pair from the received data, including a second key and a second value corresponding to the second key; including first processing core information regarding a processing core for processing a key-value pair after the at least one first key-value pair or the second key-value pair in at least one of the first key-value pair and the second key-value pair; and storing the at least one of the first key-value pair and the second key-value pair including the first processing core information in a non-volatile memory.

[0011] According to one aspect of the inventive concept, a storage system is provided, the storage system comprising: a host configured to transmit data including a plurality of keys and a plurality of values ​​corresponding to the plurality of keys; a first storage device configured to process a first key among the plurality of keys and a first value corresponding to the first key; and a second storage device configured to process a second key among the plurality of keys and a second value corresponding to the second key, wherein the first key includes information about the second storage device relating to a processing core for processing the second value after the first value.

[0012] According to another aspect of the inventive concept, a storage system includes: a host configured to transmit data comprising a plurality of key-value pairs, the plurality of key-value pairs comprising a plurality of keys and a plurality of values ​​respectively corresponding to the plurality of keys; a first storage device configured to process a first key-value pair comprising a first key among the plurality of keys and a first value corresponding to the first key; and a second storage device configured to process a second key-value pair comprising a second key among the plurality of keys and a second value corresponding to the second key, wherein at least one of the first key-value pair and the second key-value pair includes: information relating to at least one storage device in the second storage device and the first storage device to a processing core for processing a next key-value pair after the at least one of the first key-value pair and the second key-value pair. Attached Figure Description

[0013] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a schematic block diagram illustrating a storage system according to an exemplary embodiment;

[0015] Figure 2 This is a schematic block diagram illustrating a storage device according to an exemplary embodiment;

[0016] Figure 3 This is a flowchart illustrating an operation method of a storage device according to an exemplary embodiment;

[0017] Figure 4 This is a circuit diagram illustrating a memory block included in a memory cell array according to an exemplary embodiment;

[0018] Figure 5 It is shown Figure 4 A 3D view of the memory block;

[0019] Figure 6 This is a schematic block diagram illustrating a storage device according to an exemplary embodiment;

[0020] Figure 7 This is a conceptual diagram illustrating the operation of a storage device according to an exemplary embodiment;

[0021] Figures 8A to 8D This is a tabular diagram illustrating key-value pairs according to an exemplary embodiment;

[0022] Figure 9 This is a conceptual diagram illustrating the operation of a storage device according to an exemplary embodiment;

[0023] Figure 10 This is a schematic block diagram illustrating a storage device according to an exemplary embodiment;

[0024] Figure 11 This is a schematic block diagram illustrating a storage system according to an exemplary embodiment;

[0025] Figure 12 This is a schematic block diagram illustrating a storage device according to an exemplary embodiment;

[0026] Figure 13 This is a block diagram illustrating a storage device according to an exemplary embodiment;

[0027] Figure 14 This is a block diagram illustrating a storage device according to an exemplary embodiment; and

[0028] Figure 15 This is a schematic block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0029] Figure 1 A storage system according to an exemplary embodiment is shown.

[0030] Reference Figure 1 The storage system 10 may include a storage device 100 and a host 200. The storage device 100 may include a first controller 110, a second controller 130, and non-volatile memory (NVM) 150. The storage device 100 may be a multi-core system with multiple controllers (such as the first controller 110 and the second controller 130), without limitation. In one example, the storage device 100 may be configured as a dual-core system with two processors, a quad-core system with four processors, a hexa-core system with six processors, an octa-core system with eight processors, etc., but is not limited thereto. Furthermore, the first controller 110 and the second controller 130 may be driven by different processors, or may represent different processors.

[0031] The host 200 can communicate with the storage device 100 through various types of interfaces. For example, the host 200 can be implemented as an application processor (AP) or a system-on-a-chip (SoC).

[0032] In one embodiment, storage device 100 may be a key-value storage device or a key-value memory (such as a key-value solid-state drive (SSD)). A key-value storage device is a device that uses key-value pairs to process data quickly and efficiently. Here, a "key-value pair" is a pair of unique keys and values ​​that are data corresponding to the key, and may represent a "tuple" or a "key-value tuple". In a key-value pair, the key can be represented by any string (such as a filename, a Uniform Resource Identifier (URI), a hash, etc.), and the value can be any type of data (such as an image, a binary large object (blob), or a user-favorited file or document). Here, the size of the key and value can vary; for example, the size of the value may change depending on the data included in the value.

[0033] In the following description, an embodiment of storage device 100 as a key-value store will be given, where storage device 100 may be substantially referred to as the same as a key-value store or key-value memory. However, storage device 100 is not limited to a key-value store and can be applied to any object caching system or object storage system (such as encapsulated memory or database) that manages data in units of objects. Therefore, storage device 100 can manage data in units of key-value pairs as a key-value embodiment or in any manner other than key-value pairs (such as, but not limited to, tuples).

[0034] Host 200 may send a command CMD (e.g., a write request or put command) to storage device 100 for writing data including at least one key-value pair. Storage device 100 may write at least one value VALUE to non-volatile memory 150 in response to the command CMD. In one embodiment, host 200 may send a command CMD (e.g., a read request or get command) including at least one key KEY to storage device 100, and storage device 100 may read at least one value VALUE corresponding to at least one key KEY from non-volatile memory 150 in response to the command CMD.

[0035] The first controller 110 can control the non-volatile memory 150 to write the value VALUE to the non-volatile memory 150 in response to a write request from the host 200, or to read the value VALUE stored in the non-volatile memory 150 in response to a read request from the host 200. The first controller 110 may include a first key-value manager 120.

[0036] The first key-value manager 120 can receive key-value pairs included in a command CMD and separate the key and value included in the key-value pair. For example, the first key-value manager 120 can extract a set or multiple keys included in the key-value pair and store the set or multiple keys in a data buffer. The first key-value manager 120 can extract multiple values ​​included in the key-value pair and store the multiple values ​​in the data buffer.

[0037] When multiple keys of a preset number or preset quantity of data are stored in the data buffer, the first key-value manager 120 can store the stored multiple keys as a key stream in the non-volatile memory 150. When multiple values ​​of a preset number or preset quantity of data are stored in the data buffer, the first key-value manager 120 can store the stored multiple values ​​as a value stream in the non-volatile memory 150. In one embodiment, the value stream and the key stream can be stored in different areas of the non-volatile memory 150.

[0038] In one embodiment, the value VALUE may have a larger data volume than the key KEY. The first key-value manager 120 may separate the key-value pairs and manage the key KEY and value VALUE independently to reduce the amount of input / output data used for the non-volatile memory 150, thereby increasing the data processing capability for key-value pairs.

[0039] As in the first controller 110, the second controller 130 can control the non-volatile memory 150 to write the value VALUE to the non-volatile memory 150 in response to a write request from the host 200, or to read the value VALUE stored in the non-volatile memory 150 in response to a read request from the host 200. In one embodiment, the second controller 130 can process a second key in a key that is different from the first key in the key processed by the first controller 110. In one example, the multiple key keys may include a first key set and a second key set, the first key set and its corresponding value may be processed by the first controller 110, and the second key set and its corresponding value may be processed by the second controller 130.

[0040] The second controller 130 may include a second key-value manager 140. Similar to the first key-value manager 120, the second key-value manager 140 may perform the above operations on a second set of keys assigned to the second controller 130. The details of the second key-value manager 140 are the same as those disclosed in the above description of the first key-value manager 120, and therefore their repetition here may be omitted.

[0041] The non-volatile memory 150 may include a memory cell array MCA, which may include memory blocks BLK1 to BLKz, and memory block BLK1 may include multiple pages PG1 to PGk. Here, z and k may be positive integers and may be varied depending on the embodiment. For example, a memory block may be an erasure unit, and a page may be a write and read unit. In some embodiments, the memory cell array MCA may include multiple faces, multiple dies, or multiple chips. In one embodiment, the non-volatile memory 150 may include a flash memory device (such as a NAND flash memory device). However, the inventive concept is not limited thereto, and the non-volatile memory 150 may include a resistive memory device (such as resistive RAM (ReRAM), phase-change RAM (PRAM), and / or magnetic RAM (MRAM), etc.).

[0042] The storage system 10 can be implemented as, for example, a personal computer (PC), a data server, a networked storage device, an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices can be laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-book readers, wearable devices, etc.

[0043] In some embodiments, storage device 100 may be internal memory embedded in an electronic device. For example, storage device 100 may be a solid-state drive (SSD), an embedded universal flash memory (UFS) device, an embedded multimedia card (eMMC), etc. In some embodiments, storage device 100 may be external memory removable from the electronic device. For example, storage device 100 may be a UFS memory card, a compact flash memory (CF) card, a secure digital card (SD) card, a micro-secure digital card (Micro-SD) card, a mini-secure digital card (Mini-SD) card, an extreme digital card (xD) card, or a memory stick.

[0044] exist Figure 1 In an exemplary embodiment, two controllers 110 and 130 are included in the storage device 100, but the inventive concept is not limited thereto. For example, alternative embodiments may have two or more controllers included in the storage device 100. Furthermore, the two or more controllers do not need to share a single non-volatile memory 150, but can control multiple non-volatile memories.

[0045] Figure 2 A storage device according to an exemplary embodiment is shown. The above-mentioned provisions may be omitted here. Figure 1 Given Figure 2Repeated descriptions in the text.

[0046] Reference Figure 2 The storage device 100 may include a first key value manager 120, a second key value manager 140, and a non-volatile memory (NVM) 150.

[0047] The first key-value manager 120 may include a first key-value extractor 121, a first key generator 122, and a first compression module 123. The first key-value extractor 121 can extract and assign keys (KEY) and values ​​(VALUE) to a first controller from a command CMD. Figure 1 The first key and first value of (110). In one example, the first key-value extractor 121 may store the extracted first key in the key buffer of the data buffer and the extracted first value in the value buffer of the data buffer.

[0048] The first key generator 122 may add information about the controller that processes the next key or next value (or next key-value pair) after the first key extracted by the first key-value extractor 121 to the first key-value pair. In one example, the command CMD may include a second key and a corresponding second value after the first key and its corresponding first value in the data sequence, and the second key and second value may be generated by the second controller ( Figure 1 (130) Processing. The first key generator 122 can add information about the second controller that processes the second value to the first key.

[0049] The storage device 100 according to the inventive concept can add processing core information about the controller that processes each subsequent key or value existing in the key KEY. When processing a key from the key KEY and then processing the next key from the key KEY, the storage device 100 can identify the processing target of the next key from the key KEY based on the processing core information included in the key from the previous processed key. Therefore, in a multi-core system where multiple controllers process data, the processing of multiple keys with continuity can be performed efficiently. As used herein, the term "next key" may refer to the key corresponding to the next value in a data sequence with continuity.

[0050] The first key-value extractor 121 can generate a first key stream ST_KEY1 by merging multiple keys with added processing kernel information, and generate a first value stream ST_VAL1 by merging multiple corresponding values. The first key-value extractor 121 can store the first value stream ST_VAL1 in a first region AR1 of the NVM 150, and store the first key stream ST_KEY1 in a second region AR2 of the NVM 150. In one example, the first controller can store the first key stream in a first block, and the second controller can store the second key stream in a second block different from the first block.

[0051] The first compression module 123 can perform a compression operation on at least one key stream ST_KEY1 or ST_KEY2 stored in the second region AR2. As used herein, the compression operation can represent an operation to generate a new key stream by deleting the key KEY corresponding to an invalid value VALUE stored in the non-volatile memory 150. In one example, the compression operation can represent an operation to compress data in a log structure merge (LSM) tree-based data structure.

[0052] The first compression module 123 can read at least one key stream ST_KEY1 or ST_KEY2 stored in the second region AR2 and distinguish invalid keys. In one example, an invalid key could be a key from key KEY that corresponds to the value of a delete command received from the host from value VALUE (e.g., the value of a delete command received from the host). The first compression module 123 can generate a new key stream using only valid keys from key KEY included in at least one key stream ST_KEY1 or ST_KEY2. The first compression module 123 can write the generated new key stream into the second region AR2 of the non-volatile memory 150.

[0053] According to an embodiment, the first compression module 123 can identify the processing target of the next key based on the processing core information of the key included in the first key stream ST_KEY1. In one example, the second key stream ST_KEY2 may be located after the first key stream ST_KEY1 in the data sequence. The first compression module 123 can identify, based on the processing core information included in the first key stream ST_KEY1, that the processing target of the subsequent second key stream ST_KEY2 is the second controller and the second key value manager 140 included in the second controller, and send the processed first key stream ST_KEY1 to the second key value manager 140 so that the second key value manager 140 can perform a compression operation.

[0054] The second key value manager 140 may include a second key value extractor 141, a second key generator 142, and a second compression module 143. The second key value manager 140 differs from the first key value manager 120 in that it includes a controller with the same or corresponding processor, but performs similar operations; therefore, its repeated description here may be omitted.

[0055] According to an embodiment, when a multi-core system performs a compression operation, the storage device 100 can identify the processing object of the next key based on the processing core information included in the previous key, and the compression operation can be efficiently performed by multiple controllers.

[0056] exist Figure 2The illustration shows an embodiment in which two key-value managers 120 and 140 are included in the storage device 100; however, this is merely an embodiment, and therefore the spirit of the inventive concept can be applied even if more than two key-value managers are included in the storage device 100. Furthermore, in Figure 2 An embodiment is shown in which multiple key value managers 120 and 140 share a single non-volatile memory 150; however, this is merely an embodiment, and it will be understood that the spirit of the inventive concept can be applied even when multiple key value managers are connected to multiple non-volatile memories.

[0057] Figure 3 This illustrates a method of operating a storage device according to an exemplary embodiment. (The above-mentioned aspects may be omitted here.) Figure 1 and Figure 2 Given Figure 3 The description in the text.

[0058] Reference Figure 2 and Figure 3 In operation S110, storage device 100 may receive data including multiple keys and multiple values. In operation S120, storage device 100 may add processing core information about the processing of the next key to the first key. In one example, the processing core information may instruct one of multiple controllers to process the next key.

[0059] In operation S130, storage device 100 can generate a key stream using a first key with added processing kernel information. In one example, storage device 100 can generate a key stream by merging other keys with the first key having added processing kernel information.

[0060] In operation S140, storage device 100 may store the generated key stream in non-volatile memory 150. In one embodiment, storage device 100 may store the key stream and multiple values ​​in different regions of non-volatile memory 150 (e.g., different blocks, but not limited thereto).

[0061] Figure 4 A memory block included in a memory cell array is shown according to an exemplary embodiment.

[0062] Reference Figure 4 Memory cell arrays (such as, Figure 1The memory cell array (MCA), but not limited to it, can be a vertical NAND flash memory array and may include multiple memory blocks. Each memory block (e.g., BLK0) may include multiple NAND cell strings NS11 to NS13, NS21 to NS23 and NS31 to NS33, multiple word lines WL1 to WL8, multiple bit lines BL1 to BL3, multiple ground select lines GSL1 to GSL3, multiple cell string select lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND cell strings, word lines, bit lines, ground select lines, and cell string select lines may be varied according to the embodiment.

[0063] NAND cell strings NS11, NS21, and NS31 are disposed between the first bit line BL1 and the common source line CSL; NAND cell strings NS12, NS22, and NS32 are disposed between the second bit line BL2 and the common source line CSL; and NAND cell strings NS13, NS23, and NS33 are disposed between the third bit line BL3 and the common source line CSL. Each NAND cell string (e.g., NAND cell string NS11) may include a cell string select transistor SST, a ground select transistor GST, and a plurality of memory cells MC1 to MC8 connected in series therewith. The cell string select transistor SST has a gate connected to the corresponding cell string select line, and the ground select transistor GST has a gate connected to the corresponding ground select line.

[0064] Strings of NAND cells connected to a single bit line form a column. For example, NAND cell strings NS11, NS21, and NS31 connected to the first bit line BL1 can correspond to the first column, NAND cell strings NS12, NS22, and NS32 connected to the second bit line BL2 can correspond to the second column, and NAND cell strings NS13, NS23, and NS33 connected to the third bit line BL3 can correspond to the third column.

[0065] NAND cell strings connected to a cell string select line constitute a row. For example, NAND cell strings NS11, NS12, and NS13 connected to the first cell string select line SSL1 can correspond to the first row, NAND cell strings NS21, NS22, and NS23 connected to the second cell string select line SSL2 can correspond to the second row, and NAND cell strings NS31, NS32, and NS33 connected to the third cell string select line SSL3 can correspond to the third row.

[0066] The cell string select transistor SST is connected to the corresponding cell string select lines SSL1 to SSL3, and each defines a cell string for a vertically arranged memory cell. Multiple memory cells MC1 to MC8 are connected to their corresponding word lines WL1 to WL8. The ground select transistor GST is connected to the corresponding ground select lines GSL1 to GSL3. The cell string select transistor SST is connected to the corresponding bit lines BL1 to BL3, and the ground select transistor GST is connected to the common source line CSL.

[0067] Word lines of the same height (such as the first word line WL1) are connected together, while cell string select lines SSL1 to SSL3 are separate from each other, and ground select lines GSL1 to GSL3 are also separate from each other. For example, when programming a memory cell connected to the first word line WL1 and belonging to NAND cell strings NS11, NS12, and NS13, the first word line WL1 and the first cell string select line SSL1 are selected. Ground select lines GSL1 to GSL3 may also be connected together, but are not limited to this.

[0068] The storage device according to an embodiment can store keys and values ​​in different areas of a memory cell array. In one example, the key may be stored in a first horizontally arranged page of a memory cell connected to the first word line WL1 of memory block BLK0, and the value may be stored in a second horizontally arranged page of a memory cell connected to the fourth word line WL4 of memory block BLK0.

[0069] Figure 5 Show Figure 4 An exemplary structure of a memory block.

[0070] Reference Figure 5 Including memory cell arrays (such as, Figure 1 Each memory block BLK0 in the memory cell array (MCA) is oriented in a direction substantially perpendicular to the substrate SUB (e.g., Figure 5 The Z-direction is formed. Figure 5 In the diagram, memory block BLK0 is shown as including two select lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, but may actually include more or fewer lines than these.

[0071] The substrate SUB has a first conductivity type (e.g., p-type) and a common source electrode CSL, the common source electrode CSL being in a first direction (e.g., ... Figure 5 They are spaced apart in the X direction and in the second direction (such as, Figure 5 Extending in the Y direction, and doped with impurities of a second conductivity type (such as n-type). In the region between two adjacent common source lines CSL of the substrate SUB, multiple insulating layers IL extending in the second direction extend in the third direction (such as n-type). Figure 5 The insulating layers are arranged sequentially in the Z direction and spaced apart from each other by a specific distance in the third direction. For example, multiple insulating layers IL may include an insulating material (such as silicon oxide).

[0072] In the region between two adjacent common source lines CSL of the substrate SUB, a plurality of pillars P are arranged sequentially in a second direction and penetrate multiple insulating layers IL in a third direction. For example, the plurality of pillars P can contact the substrate SUB through the multiple insulating layers IL. Specifically, the surface layer S of each pillar P may include a silicon material of a first type and serve as a channel region. The inner layer I of each pillar P may include an insulating material (such as silicon oxide) or an air gap.

[0073] In the region between two adjacent common-source lines CSL, a charge storage layer CS is disposed along the exposed surfaces of the insulating layer IL, pillar P, and substrate SUB. The charge storage layer CS may include a gate insulating layer or "tunnel insulating layer," a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Furthermore, in the region between the two adjacent common-source lines CSL, gate electrodes GE (such as select lines GSL and SSL, and word lines WL1 to WL8) are disposed on the exposed surfaces of the charge storage layer CS.

[0074] The drain or drain contact DR is disposed on a plurality of pillars P. For example, the drain or drain contact DR may comprise silicon material doped with impurities having a second conductivity type. In the first direction (e.g., Figure 5 Bit lines BL1 to BL3, which extend in the X direction, are spaced apart at a specific distance in the second direction and are disposed on the drain DR.

[0075] Figure 6 A storage device according to an exemplary embodiment is shown. The above-mentioned provisions will be omitted here. Figure 1 and Figure 2 Given Figure 6 The description in the text.

[0076] Reference Figure 6 The storage device 100 may include a first controller 110, a second controller 130, a third controller 160, and a data buffer 170. The storage device 100 may also include non-volatile memory (such as...) connected to the data buffer 170. Figure 2 NVM 150).

[0077] The first controller 110 can receive key-value pairs included in the command CMD, and can extract multiple first keys KEY1 and multiple first values ​​VAL1 assigned to the first controller 110 from the key-value pairs. The first controller 110 can store the extracted multiple first keys KEY1 and the extracted multiple first values ​​VAL1 in a data buffer 170.

[0078] When multiple first keys KEY1 of a preset quantity or preset amount of data are stored in the data buffer 170, the first controller 110 can use the stored multiple first keys KEY1 as a first key stream (such as, Figure 2 The ST_KEY1 is stored in non-volatile memory 150. When a preset number or preset amount of data with multiple first values ​​VAL1 are stored in data buffer 170, the first controller 110 can use the stored multiple first values ​​VAL1 as a first value stream (such as, Figure 2 The ST_VAL1 is stored in non-volatile memory 150. In one embodiment, the value stream and the key stream may be stored in different areas of the non-volatile memory 150. In one embodiment, the first controller 110 may add processing core information about the controller (such as the second controller 130 or the third controller 160) that processes the next key to a plurality of first keys KEY1, and generate a first key stream by merging the plurality of first keys KEY1 with the added processing core information.

[0079] In one embodiment, the first controller 110 may use a key table KT to manage the physical address of the first key KEY1 stored in the data buffer 170. In one embodiment, the key table KT may be generated as a hash table, which is stored together with the hash key corresponding to the first key KEY1 as a mapping index of the first key KEY1. Furthermore, in one embodiment, the first controller 110 may use a value table VT to manage the physical address of the first value VAL1 stored in the data buffer 170.

[0080] Similar to the first controller 110, the second controller 130 can use a plurality of second keys KEY2 assigned to the second controller 130 to generate a second key stream, and use a plurality of second values ​​VAL2 to generate a second value stream. Similarly, similar to the first controller 110, the third controller 160 can use a plurality of third keys KEY3 assigned to the third controller 160 to generate a third key stream, and use a plurality of third values ​​VAL3 to generate a third value stream.

[0081] The data buffer 170 may include at least one storage device for storing a first key KEY1, a second key KEY2, and a third key KEY3, as well as a first value VAL1, a second value VAL2, and a third value VAL3. In one embodiment, the data buffer 170 may include a volatile memory device (such as dynamic random access memory (DRAM) or static random access memory (SRAM)).

[0082] In addition to storing the first key KEY1, the second key KEY2, and the third key KEY3, and the first value VAL1, the second value VAL2, and the third value VAL3, the data buffer 170 may also store a key table KT and a value table VT. The key table KT may store the physical address of the key stream in the non-volatile memory 150. In one embodiment, the key table KT may further include a valid bit indicating whether the key stream is valid. The value table VT may store the value stream in the non-volatile memory 150. In one embodiment, the value table VT may further include a valid bit indicating whether the value stream is valid.

[0083] According to an embodiment, multiple controllers (such as a first controller 110, a second controller 130, and a third controller 160) can perform corresponding operations in response to a command CMD. Here, the multiple controllers (such as the first controller 110, the second controller 130, and the third controller 160) can respectively add information about the controller processing the next key to the first key KEY1, the second key KEY2, and the third key KEY3, so that key-value-based data processing can be efficiently performed by multiple controllers.

[0084] exist Figure 6 The illustration shows an example in which three controllers (i.e., first controller 110, second controller 130 and third controller 160) are included in the storage device 100, but this is only an embodiment, and the spirit of the inventive concept can also be applied to embodiments in which more or fewer controllers are included in the storage device 100.

[0085] Figure 7 The operation of a storage device according to an exemplary embodiment is shown.

[0086] Reference Figure 2 and Figure 7 Since the second controller 130 performs substantially the same or similar operations as the first controller 110, therefore in Figure 7To avoid redundancy, only the operation of the first controller 110 may be described. The first controller 110 can receive key-value pairs KVP and can separate the keys and values ​​from those included in the key-value pairs KVP. The first controller 110 can combine the processing kernel information Info_PC for the next key with each key. Furthermore, the first controller 110 can generate a key stream ST_KEY by merging multiple keys that combine the processing kernel information Info_PC, and store the generated key stream ST_KEY in the first region AR1 of the non-volatile memory 150.

[0087] exist Figure 7 In the diagram, a key stream ST_KEY is shown as corresponding to a processing kernel information Info_PC (but this is for ease of description). Thus, for example, the key stream ST_KEY according to an embodiment may include multiple processing kernel information-key pairs in which the processing kernel information Info_PC is combined with each key.

[0088] The first controller 110 can also combine the indexes and keys corresponding to the values ​​respectively, and generate a key stream ST_KEY by merging multiple keys combined with the indexes and the processing core information Info_PC, and store the generated key stream ST_KEY in the first region AR1 of the non-volatile memory 150.

[0089] The first controller 110 can store the values ​​separated from the key-value pair KVP in a data buffer (such as, Figure 6 In the data buffer 170, a value stream ST_VAL is generated by merging multiple values ​​stored in the data buffer, and the generated value stream ST_VAL is stored in the second region AR2 of the non-volatile memory 150.

[0090] The first controller 110 can generate a key table KT using the physical page number (PPN) of the key stream ST_KEY stored in the non-volatile memory 150. In other words, the key table KT can store the PPN and the physical address of the non-volatile memory 150 where the key stream ST_KEY is stored. In one embodiment, the key table KT may also include a valid bit indicating whether the key stream ST_KEY is valid.

[0091] The first controller 110 can generate a value table VT using the value stream ST_VAL stored in the non-volatile memory 150 via a PPN. In other words, the value table VT can store the PPN and the physical address of the non-volatile memory 150 where the value stream ST_VAL is stored. In one embodiment, the value table VT may also include a validity bit indicating whether the value stream ST_VAL is valid.

[0092] Figures 8A to 8D A key-value pair is shown according to an exemplary embodiment.

[0093] Reference Figure 2 and Figure 8A The first key KEY0 through the ninth key KEY8 may have a sequential metadata sequence. The first controller 110 may receive the first key KEY0, the fourth key KEY3, and the seventh key KEY6, and include second processing core information C1 from the second controller 130 regarding the processing of the next key in each of the received first key KEY0, the received fourth key KEY3, and the received seventh key KEY6. Furthermore, the second controller 130 may receive the second key KEY1, the fifth key KEY4, and the eighth key KEY7, and include third processing core information C2 from the third controller 160 regarding the processing of the next key in each of the received second key KEY1, the received fifth key KEY4, and the received eighth key KEY7. The third controller 160 may receive the third key KEY2, the sixth key KEY5, and the ninth key KEY8, and include first processing core information C0 from the first controller 110 regarding the processing of the next key in each of the received third key KEY2, the received sixth key KEY5, and the received ninth key KEY8.

[0094] Reference Figure 2 and Figure 8B The first controller 110 can receive the first key KEY0, the fourth key KEY3 and the seventh key KEY6, and include the second processing core information C1 of the second controller 130 regarding the processing of the second key KEY1 as the next key in the received first key KEY0, include the third processing core information C2 of the third controller 160 regarding the processing of the fifth key KEY4 as the next key in the received fourth key KEY3, and include the second processing core information C1 of the second controller 130 regarding the processing of the eighth key KEY7 as the next key in the received seventh key KEY6.

[0095] The second controller 130 can receive the second key KEY1, the sixth key KEY5, and the eighth key KEY7, and include the third processing core information C2 of the third controller 160 regarding the processing of the third key KEY2 as the next key in the received second key KEY1, include the first processing core information C0 of the first controller 110 regarding the processing of the seventh key KEY6 as the next key in the received sixth key KEY5, and include the third processing core information C2 of the third controller 160 regarding the processing of the ninth key KEY8 as the next key in the received eighth key KEY7.

[0096] The third controller 160 can receive the third key KEY2, the fifth key KEY4, and the ninth key KEY8. It includes the first processing core information C0 of the first controller 110 regarding the processing of the fourth key KEY3 as the next key in the received third key KEY2, and includes the second processing core information C1 of the second controller 130 regarding the processing of the sixth key KEY5 as the next key in the received fifth key KEY4. Here, if there is no next key, the third controller does not need to include the first processing core information C0 of the first controller 110 regarding the processing of the next key in the received ninth key KEY8.

[0097] Reference Figure 2 and Figure 8C , Figure 8C This illustration shows an embodiment where processing core information is not included when the next key is processed in the same controller. The first controller 110 can receive a first key KEY0, a second key KEY1, and a third key KEY2. Since the next key after the received first key KEY0 and the received second key KEY1 is also processed in the first controller 110, the first controller 110 can include only the second processing core information C1 regarding the second controller 130 in the third key KEY2, wherein the next key after the third key KEY2 is processed in the second controller 130, not the first controller 110.

[0098] The second controller 130 can receive the fourth key KEY3, the fifth key KEY4, and the sixth key KEY5. Since the next key after the received fourth key KEY3 and the received fifth key KEY4 is also processed in the second controller 130, the second controller 130 can include only the third processing core information C2 about the third controller 160 in the sixth key KEY5, wherein the next key after the sixth key KEY5 is processed in the third controller 160 instead of the second controller 130.

[0099] The third controller 160 can receive the seventh key KEY6, the eighth key KEY7, and the ninth key KEY8. Since the next key after the received seventh key KEY6 and the received eighth key KEY7 is also processed in the third controller 160, the third controller 160 can include only the first processing core information C0 regarding the first controller 110 in the ninth key KEY8, wherein the next key after the ninth key KEY8 is processed in the first controller 110, not in the third controller 160. Here, the next key after the ninth key KEY8 (not shown) can be processed in the first controller 110.

[0100] Reference Figure 2 and Figure 8D , Figure 8DAn embodiment is illustrated where processing kernel information is included in values ​​rather than keys. A first controller 110 may receive a first value VAL0, a fourth value VAL3, and a seventh value VAL6, and includes second processing kernel information C1 from a second controller 130 regarding processing the next value in each of the received first value VAL0, the received fourth value VAL3, and the received seventh value VAL6. Furthermore, the second controller 130 may receive a second value VAL1, a fifth value VAL4, and an eighth value VAL7, and includes third processing kernel information C2 from a third controller 160 regarding processing the next value in each of the received second value VAL1, the received fifth value VAL4, and the received eighth value VAL7. The third controller 160 may receive a third value VAL2, a sixth value VAL5, and a ninth value VAL8, and includes first processing kernel information C0 from the first controller 110 regarding processing the next value in each of the received third value VAL2, the received sixth value VAL5, and the received ninth value VAL8.

[0101] In an alternative embodiment, processing kernel information may be included in both the key and the value. For example, such an embodiment can normally use the processing kernel information included in the key, but if the key is invalid, the processing kernel information from the value can be used.

[0102] Figure 9 The operation of a storage device according to an exemplary embodiment is illustrated. In detail, Figure 9 This is a diagram illustrating a method for performing compression operations on a storage device.

[0103] Reference Figure 2 and Figure 9 The first controller 110 can read the invalid key stream ST_IK from the first region AR1 of the non-volatile memory 150. In one embodiment, the first controller 110 can respond to the host ( Figure 1 Various types of commands (of type 200) update the hash table HT with information about whether the keys included in the key stream are valid, and identify invalid key streams ST_IK based on the hash table HT. In one example, when from host ( Figure 1 When the first controller 110 receives an erase command for the first value, it can identify the first key in the hash table HT corresponding to the first value and update the hash table HT to indicate that the first key is invalid.

[0104] The first controller 110 can use the second processing core information C1 included in the identified invalid key stream ST_IK to identify the next key to be processed in the second controller 130. The first controller 110 can output the associated information to the second controller 130 so that the second controller 130 can read the next invalid key stream ST_IK. In one example, the first controller 110 can delete invalid keys included in the invalid key stream ST_IK allocated to the first controller 110 and send a key stream containing only valid keys to the second controller 130.

[0105] The second controller 130 may receive at least one key from the first controller 110 and merge the at least one key with an invalid key stream ST_IK assigned to the second controller 130 to generate at least one merged key stream ST_MK. In one example, either the first controller 110 or the second controller 130 may delete invalid keys based on the hash table HT described above and extract valid keys to generate the merged key stream ST_MK. Therefore, the merged key stream ST_MK may be a key stream that includes valid keys.

[0106] The first controller 110 or the second controller 130 may write the generated merged key stream ST_MK into a first region AR1 of the non-volatile memory 150. Furthermore, the first key-value manager 120 may delete invalid key streams ST_IK. In one embodiment, the first controller 110 or the second controller 130 may perform garbage collection for invalid values ​​based on the valid bits of the value table VT. When garbage collection is performed based on the value table VT, invalid values ​​may be deleted from the second region AR2.

[0107] The storage device 100 according to the embodiment can use processing kernel information to identify information about the next key during compression operations, and perform compression operations through data transfer between multiple controllers using the same valid tables and / or NVM storage areas, so that compression operations can be performed efficiently even in multiple controllers.

[0108] Figure 10 A storage device according to an exemplary embodiment is shown. In detail, Figure 10 This illustrates an example of processing core information via a standby controller and incorporating it into the key. The above information can be omitted here. Figures 1 to 9 The basic information given Figure 10 The description in the text.

[0109] Reference Figure 10 The storage device 100a may include a first controller 110, a second controller 130, a non-volatile memory 150, and a backup controller 180. The first controller 110, the second controller 130, and the non-volatile memory 150 may be referenced above. Figure 2The descriptions are essentially the same, so their descriptions can be omitted here.

[0110] The backup controller 180 may include a key generator 181. The key generator 181 may receive a command CMD including multiple keys and multiple values, and may incorporate processing kernel information for the next key into the multiple keys. In one example, the multiple keys may include a first key KEY1 corresponding to a first value VAL1 and a second key KEY2 corresponding to a second value VAL2. Here, the next key after the first key KEY1 may be processed in the second controller 130, and the next key after the second key KEY2 may be processed in the first controller 110.

[0111] Therefore, key generator 181 can include the second processing core information C1 corresponding to the second controller 130 in the first key KEY1, and output the first key KEY1 and the first value VAL1 to the first controller 110. Key generator 181 can include the first processing core information C0 corresponding to the first controller 110 in the second key KEY2, and output the second key KEY2 and the second value VAL2 to the second controller 130.

[0112] According to an embodiment, an additional controller may include processing core information in at least some of the multiple keys, so that key-value pair processing by multiple controllers (such as the first controller 110 and the second controller 130) can be performed efficiently.

[0113] Figure 11 A storage system according to an exemplary embodiment is shown. In detail, Figure 11 This illustrates an example where kernel information is included in a key via the host. (The above references can be omitted here.) Figures 1 to 10 The basic information given Figure 11 The description in the text.

[0114] Reference Figure 11 The storage system 10b may include a host 200b, a first storage device 100b, and a second storage device 300b. The first storage device 100b may include a first controller 110b and a first non-volatile memory 150b, and the second storage device 300b may include a second controller 310b and a second non-volatile memory 350b. In one example, the first storage device 100b and the second storage device 300b may each include a first region and a second region of the same non-volatile memory device.

[0115] Each of the first controller 110b and the second controller 310b is executable and refers to the above. Figures 1 to 10 The operations described are the same as or similar to those performed by the controller, and each of the first non-volatile memory 150b and the second non-volatile memory 350b is executable as described above. Figures 1 to 10 The operations described are the same as or similar to those performed by non-volatile memory.

[0116] Host 200b may include key generator 210b. Key generator 210b may include processing core information for the next key among a plurality of keys. In one example, the plurality of keys may include a first key KEY1 corresponding to a first value VAL1 and a second key KEY2 corresponding to a second value VAL2, the next key of the first key KEY1 may be processed in the second storage device 300b, and the next key of the second key KEY2 may be processed in the first storage device 100b.

[0117] Key generator 210b can include the second processing core information SD1 corresponding to the second storage device 300b in the first key KEY1, and output the first key KEY1 and the first value VAL1 to the first storage device 100b. Key generator 210b can include the first processing core information SD0 corresponding to the first storage device 100b in the second key KEY2, and output the second key KEY2 and the second value VAL2 to the second storage device 300b.

[0118] According to an embodiment, host 200b may include processing core information in at least some of the multiple keys KEY1, KEY2, so that key-value pair processing via multiple storage devices 100b and 300b can be performed efficiently.

[0119] Figure 12 A storage device according to an exemplary embodiment is shown.

[0120] Reference Figure 12 The storage device 100c may include control circuitry 110c, volatile memory (VM) 190, and non-volatile memory 150. Furthermore, the control circuitry 110c may include a first processor 111, a second processor 112, a memory 113, a host interface (IF) 114, a volatile memory interface 115, a non-volatile memory interface 116, an error correction code (ECC) engine 117, and an Advanced Encryption Standard (AES) engine 118, all of which can communicate with each other via a bus 119.

[0121] Each of the first processor 111 and the second processor 112 may include a central processing unit (CPU), a microprocessor, etc., and can control the overall operation of the control circuit 110c. The memory 113 can operate under the control of the first processor 111 or the second processor 112, and can be used as operational memory, buffer memory, cache memory, etc. For example, the memory 113 can also be implemented as volatile memory (such as DRAM or SRAM) or non-volatile memory (such as PRAM or flash memory including a flash translation layer (FTL)). Referring to the above... Figures 1 to 11Each of the first processor 111 and the second processor 112 can be operated using the memory 113 and can be operated as a first controller or a second controller.

[0122] The key-value manager 120c can be implemented in firmware or software and can be loaded into memory 113. In one embodiment, the key-value manager 120c can be implemented in FTL and can be loaded into memory 113. However, the inventive concept is not limited thereto, and the key-value manager 120c can be implemented in hardware. References above Figures 1 to 11 The described operations can be performed using the key value manager 120c via the first processor 111 or the second processor 112.

[0123] Host interface 114 provides an interface between the host computer and control circuitry 110c. For example, host interface 114 may provide interfaces according to the following: Universal Serial Bus (USB), Multimedia Card (MMC), PCI Express (PCI-E), AT Accessory (ATA), Serial AT Accessory (SATA), Parallel AT Accessory (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0124] The non-volatile memory interface 116 provides an interface between the control circuitry 110c and the non-volatile memory 150. For example, key streams or value streams can be sent and / or received between the control circuitry 110c and the non-volatile memory 150 via the non-volatile memory interface 116. The non-volatile memory interface 116 can be implemented to conform to standard conventions (such as Toggle or ONFI).

[0125] The volatile memory interface 116 can provide an interface between the control circuitry 110c and the volatile memory 190. For example, keys, values, and mapping tables MT can be sent and / or received between the control circuitry 110c and the volatile memory 190.

[0126] ECC engine 117 can perform error detection and correction functions on read data read from non-volatile memory 150. Specifically, ECC engine 117 can generate parity bits for write data to be written to non-volatile memory 150, and the parity bits generated as described above are stored together with the write data. When reading data from non-volatile memory 150, ECC engine 117 can use the parity bits read from non-volatile memory 150 together with the read data to correct errors in the read data and output the error-corrected read data. In one embodiment, ECC engine 117 may include an ECC encoder (not shown) that generates parity bits for write data and / or an ECC decoder (not shown) that corrects errors in the read data.

[0127] The AES engine 118 can perform at least one of encryption and decryption operations on data input to the control circuit 110c. In one embodiment, the AES engine 118 can use a symmetric key algorithm to perform at least one of encryption and decryption operations. In one embodiment, the AES engine 118 may include an encryption module (not shown) that performs encryption operations and / or a decryption module (not shown) that performs decryption operations.

[0128] Each of the ECC engine 117 and the AES engine 118 may be implemented as firmware or software and may be loaded into memory 113. However, this disclosure is not limited thereto, and each of the ECC engine 117 and the AES engine 118 may be implemented as hardware or as a combination of software and hardware.

[0129] Volatile memory 190 can store a mapping table MT. In one example, such as in Figure 6 Similar to the data buffer 170, the volatile memory 190 can also store keys and values. For this purpose, the volatile memory 190 can be implemented as DRAM. The mapping table MT can include, as referenced above... Figures 1 to 11 Any one of the hash table, key table, and value table mentioned above.

[0130] According to the embodiment, the storage device 100c can include processing core information for the next key within the key when key-value data is processed by multiple processors (such as a first processor 111 and a second processor 112), so that key-value data processing can be performed efficiently.

[0131] Figure 13 This is a block diagram illustrating a storage device according to an embodiment.

[0132] Reference Figure 12 and Figure 13The storage device 400 may include a controller 410 and a non-volatile memory 420. The storage device 400 may support multiple channels CH1 to CHm, and the controller 410 and the non-volatile memory 420 may be connected via multiple channels CH1 to CHm. The controller 410 may correspond to the above... Figures 1 to 12 The controllers 110, 130, 160, 110b and 310b and the control circuit 110c described herein, and the non-volatile memory 420 may correspond to the above. Figures 1 to 12 The non-volatile memories 150, 150b, and 350b are described in the document.

[0133] The non-volatile memory 420 may include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, non-volatile memory devices NVM11 to NVM1n are connected to the first channel CH1 via paths W11 to W1n, and non-volatile memory devices NVM21 to NVM2n are connected to the second channel CH2 via paths W21 to W2n. For example, each of n and m may be an integer greater than 2.

[0134] The controller 410 can send signals to and receive signals from the non-volatile memory 420 via multiple channels CH1 to CHm. For example, the controller 410 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the non-volatile memory 420 via channels CH1 to CHm. Optionally, data DATAa to DATAm can be received from the non-volatile memory 420.

[0135] Controller 410 can select one of the non-volatile memory devices connected to the corresponding channel for each channel, and use the selected non-volatile memory device to send and receive signals. For example, controller 410 can select non-volatile memory device NVM11 from non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. Controller 410 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 via path W11, or receive data DATAa from the selected non-volatile memory device NVM11 via path W11.

[0136] Figure 14 This is a block diagram illustrating a storage device according to an embodiment.

[0137] Reference Figure 13 and Figure 14The storage device 500 may include a controller 510 and a non-volatile memory 520. The non-volatile memory 520 may correspond to... Figure 13 A non-volatile memory device NVM11 to NVMmn communicates with controller 410 based on one of multiple channels CH1 to CHm. Controller 510 may correspond to... Figure 13 The controller 410.

[0138] The controller 510 may include first pins P21 to eighth pins P28 and controller interface circuitry 511. The non-volatile memory 520 may include first pins P11 to eighth pins P18, memory interface circuitry 521, control logic circuitry 523, and memory cell array 525. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18.

[0139] The controller interface circuit 511 can send the chip enable signal nCE to the non-volatile memory 520 via the first pin P21. The controller interface circuit 511 can send signals to the non-volatile memory 520 selected by the chip enable signal nCE and receive signals from the non-volatile memory 520 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0140] The controller interface circuit 511 sends the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory 520 via pins P22 to P24. The controller interface circuit 511 sends the read enable signal nRE to the non-volatile memory 520 via pin P25. The controller interface circuit 511 receives the data strobe signal DQS from the non-volatile memory 520 via pin P26, or sends the data strobe signal DQS to the non-volatile memory 520 via pin P26.

[0141] The controller interface circuit 511 can send or receive the data signal DQ from the non-volatile memory 520 via pin 7 P27. Command CMD, address ADDR, and data DATA can be sent via the data signal DQ. For example, the data signal DQ can be sent via multiple data signal lines. In this case, pin 7 P17 may include multiple pins corresponding to multiple data signals. The memory interface circuit 521 can send the ready / busy output signal nR / B to the controller 510 via pin 8 P28.

[0142] Control logic circuit 523 typically controls various operations of non-volatile memory 520. Control logic circuit 523 can receive commands / addresses CMD / ADDR obtained from memory interface circuit 521. Control logic circuit 521 can generate various control signals based on the received commands / addresses CMD / ADDR for programming data DATA into or reading data DATA from memory cell array 525.

[0143] Figure 15 An electronic device according to an exemplary embodiment is shown.

[0144] Reference Figure 15 The electronic device 3000 may include a processor 3100, a memory device 3200, a storage device 3300, a modem 3400, an input / output (I / O) device 3500, and a power supply 3600. In one embodiment, the storage device 3300 may use the above-mentioned reference. Figures 1 to 14 The described embodiments are implemented.

[0145] In one embodiment, the storage device 3300 may receive key-value pairs from a host, including multiple keys and multiple values ​​corresponding to the multiple keys respectively, and separate the multiple keys and multiple values ​​from the key-value pairs.

[0146] In one embodiment, storage device 3300 can combine processing core information for the next key with each of a plurality of keys, and merge the plurality of keys combining the processing core information to generate a key stream. Furthermore, storage device 3300 can merge multiple values ​​to generate a value stream. Additionally, storage device 3300 can store the generated key stream and the generated value stream in an internal non-volatile memory device or an external non-volatile memory device.

[0147] In one embodiment, the storage device 3300 can use processing core information to remove invalid keys from multiple controllers during compression processing and generate a key stream including valid keys. Therefore, in the compression processing of the storage device 3300 with a multi-core processing system, key-value data processing can be performed efficiently.

[0148] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein by those skilled in the art without departing from the scope and spirit of the inventive concept as defined by the claims.

Claims

1. A storage device, comprising: The first controller is assigned to process a first key-value pair, which includes a first key and a first value corresponding to the first key. The second controller is assigned to process second key-value pairs, including a second key and a second value corresponding to the second key; and The non-volatile memory is configured to store a first key, a second key, a first value, and a second value. The information indicates whether the controller assigned to process the next key-value pair after processing at least one of the first and second key-value pairs is the second controller or the first controller. The information is included in at least one of the first key-value pair and the second key-value pair.

2. The storage device according to claim 1, wherein: The storage device is configured to separate a plurality of keys and a plurality of values ​​corresponding to the plurality of keys, and to manage the plurality of keys and the plurality of values ​​corresponding to the plurality of keys. The first controller includes the first index corresponding to the first value and the first processing core information corresponding to the second controller in the first key, and merges the first key with at least one third key processed by the first controller to generate a first key stream. The second controller includes the second index corresponding to the second value in the second key, and merges the second key with at least one fourth key processed by the second controller to generate a second key stream.

3. The storage device according to claim 2, wherein: The non-volatile memory consists of a first block and a second block. The first controller stores the first key stream in the first block, and The second controller stores the second key stream in the second block.

4. The storage device according to claim 3, wherein: The first controller reads the first key stream from the first block and outputs the first key stream to the second controller based on the first processing core information included in the first key stream. The second controller performs a compression operation that reads the second key stream from the second block and merges the second key stream with the first key stream received from the first controller to generate a third key stream.

5. The storage device according to claim 4, wherein: The second controller generates a third key stream by merging valid keys from multiple keys included in the first key stream and the second key stream. The valid key corresponds to the value among the plurality of values ​​for which an erase command was not received from the host.

6. The storage device according to claim 2, wherein: The first controller merges the first value corresponding to the first key and the at least one third value corresponding to the at least one third key to generate a first value stream, and stores the generated first value stream in non-volatile memory. The second controller merges the second value corresponding to the second key and the at least one fourth value corresponding to the at least one fourth key to generate a second value stream, and stores the generated second value stream in non-volatile memory. The first value stream is stored in non-volatile memory independently of the first key stream, and the second value stream is stored in non-volatile memory independently of the second key stream.

7. The storage device according to claim 6, further comprising: The volatile memory is configured to store a key table and a value table. The key table includes physical addresses of a first key stream and a second key stream stored in non-volatile memory. The value table includes physical addresses of a first value stream and a second value stream stored in non-volatile memory.

8. The storage device according to claim 2, wherein: At least one fourth value, processed after at least one third value corresponding to the at least one third key, is processed by the second controller, and The first controller includes the first processing core information in both the first key and the at least one third key.

9. The storage device according to any one of claims 1 to 8, further comprising: The third controller is configured to process the fifth key and the fifth value corresponding to the fifth key. The second controller includes information about the third controller regarding the processing of the fifth value after the second value in the second key as the second processing core information.

10. The storage device of claim 1, further comprising: The backup controller is configured to include information about the first processing core corresponding to the second controller that processes the second value after the first value in the first key.

11. The storage device according to claim 1, wherein, The non-volatile memory is configured to store a first value and a second value in at least one first region of the non-volatile memory, and to store a first key and a second key in at least one second region of the non-volatile memory. The first controller receives a first key containing information about the first processing core corresponding to the second controller that processes the second value after the first value.

12. A method of operating a storage system, comprising: Receive data; Extract the first key-value pair from the received data, including the first key and the first value corresponding to the first key; Extract the second key-value pair from the received data, including the second key and the second value corresponding to the second key; Generate first processing core information indicating a processing core for processing key-value pairs after processing at least one of the first key-value pairs and the second key-value pairs, wherein the first processing core information is included in at least one of the first key-value pairs and the second key-value pairs; and The first key-value pair and the second key-value pair containing the first processing kernel information are stored in non-volatile memory.

13. The operating method according to claim 12, wherein: The storage system includes a storage device, and the storage device includes a first controller and a second controller. The step of extracting the first key-value pair is executed by the first controller, and The step of extracting the second key-value pair is performed by the second controller.

14. The method of operation of claim 13, wherein, The first processing core information includes information about the second controller.

15. The operating method according to claim 13, wherein: The storage device includes a backup controller, and The step of including the first processing core information in at least one of the first key-value pair and the second key-value pair is performed by the standby controller.

16. The operating method according to claim 12, wherein: The storage system includes a first storage device and a second storage device. The step of extracting the first key-value pair is performed by the first storage device, and the step of extracting the second key-value pair is performed by the second storage device. The first processing core information includes information about the second storage device.

17. The operating method according to claim 12, wherein: The storage system includes a host and at least one storage device, and The step of including the first processing kernel information in at least one of the first key-value pair and the second key-value pair is performed by the host.

18. A storage system, comprising: The host is configured to send data comprising multiple key-value pairs, the multiple key-value pairs comprising multiple keys and multiple values ​​respectively corresponding to the multiple keys; A first storage device is configured to process a first key-value pair comprising a first key among the plurality of keys and a first value corresponding to the first key; and The second storage device is configured to process second key-value pairs, including a second key from the plurality of keys and a second value corresponding to the second key. Wherein, at least one of the first key-value pair and the second key-value pair includes: information indicating whether the storage device assigned to process the next key-value pair after processing the first key-value pair and the second key-value pair is the second storage device or the first storage device.

19. The storage system according to claim 18, wherein The information is related to the processing core. The host includes first processing core information about the second storage device for processing a second value after the first value in the first key, and sends the first key including the first processing core information to the first storage device.

20. The storage system according to claim 18 or claim 19, wherein: The first storage device and the second storage device respectively include a first region and a second region of the same non-volatile memory device. The first region includes the first value and the second value. The second area includes the first key and the second key.

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