Display panel and electronic device

Abstract

The present application discloses a display panel and an electronic device, in which the test circuit of the display panel has a signal transmission line, the signal transmission line is electrically connected to the touch signal line, and the signal transmission line is also electrically connected to the data line through a connecting line. In this way, in the test phase, the test signal can be input to the data line through the signal transmission line, and the panel test is implemented through the signal transmission line. In the non-test phase, the connecting line is disconnected from the test circuit, and the signal transmission line outputs the touch signal detected by the touch electrode, and the touch detection is implemented through the signal transmission line. It can be seen that the signal transmission line in the test circuit can be used for both panel testing and touch detection, reducing the number of wiring. The electronic device adopts the above-mentioned display panel, which can reduce the number of wiring and facilitate the realization of narrow frame design and full-screen design.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and more specifically, to a display panel and an electronic equipment. Background Art

[0002] With the continuous advancement of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The main component of an electronic device to realize the display function is the display panel. As the functions of electronic devices become increasingly powerful, the display panel is required to have not only image display function, but also integrate other functions, such as integrated touch electrodes with touch detection function, etc., which results in the display panel needing to have more wiring, which is not convenient for narrow bezel design and full-screen design. Summary of the invention

[0004] In view of this, the present application provides a display panel and an electronic device, and the scheme is as follows:

[0005] A display panel, the display panel having a display area and a frame area, the display panel comprising:

[0006] A plurality of sub-pixels are arranged in the display area, and the sub-pixels are electrically connected to the data lines;

[0007] A touch electrode located in the display area;

[0008] A touch signal line electrically connected to the touch electrode;

[0009] A test circuit is arranged in the border area; the test circuit includes a signal transmission line, and the signal transmission line is electrically connected to the touch signal line;

[0010] Connecting lines, which correspond one to one with data lines. In the test phase, the signal transmission line and the data line are connected through the connecting lines, and the signal transmission line inputs a test signal to the data line. In the non-test phase, the connecting lines are disconnected from the test circuit, and the signal transmission line outputs a touch signal detected by the touch electrode.

[0011] In the display panel provided by the technical solution of the present application, the test circuit has a signal transmission line, the signal transmission line is electrically connected to the touch signal line, and the signal transmission line is also electrically connected to the data line through the connecting line. In this way, in the test phase, the test signal can be input to the data line through the signal transmission line, and the panel test is realized through the signal transmission line. In the non-test phase, the connecting line is disconnected from the test circuit, and the signal transmission line outputs the touch signal detected by the touch electrode, and the touch detection is realized through the signal transmission line. It can be seen that the signal transmission line in the test circuit can be used for both panel testing and touch detection, reducing the number of lines.

[0012] The present application also provides an electronic device, which includes the above-mentioned display panel.

[0013] The electronic device provided by the technical solution of the present application adopts the above-mentioned display panel, which can reduce the number of wiring and facilitate the realization of narrow bezel design and full-screen design. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0015] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0016] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0017] Figure 2 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0018] Figure 3 A schematic diagram of a test circuit provided in an embodiment of the present application;

[0019] Figure 4 for Figure 3 A schematic diagram of the structure of a gating circuit unit in the test circuit shown;

[0020] Figure 5 A schematic diagram of a display array in a display panel provided in an embodiment of the present application;

[0021] Figure 6 A schematic diagram of the structure of another test circuit provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of the arrangement of signal transmission lines in a display panel provided in an embodiment of the present application;

[0023] Figure 8 A schematic diagram of the arrangement of switch signal lines in a display panel provided in an embodiment of the present application;

[0024] Fig. 9 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0025] Fig.10 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0026] Fig.11 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0027] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0029] In existing display panels, the test circuit is only used for panel testing before shipment to test whether there is a data line break or a sub-pixel that cannot display normally. The test circuit needs to be equipped with a separate routing and a gating circuit to be electrically connected to the data line. The touch signal line of the touch electrode also needs to be equipped with a separate routing and a gating circuit, resulting in a large number of signal lines and gating circuits in the panel, which requires a large step area.

[0030] In order to solve the above problems, in the display panel and electronic device provided in the embodiments of the present application, signal transmission lines of the touch line multiplexing test circuit are designed, so that there is no need to set up separate lines and enabling circuits for the touch lines, thereby reducing the number of lines and enabling circuits, and facilitating the narrow bezel and full-screen design of electronic devices.

[0031] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0032] like Figure 1 As shown, Figure 1 The structure diagram of a display panel provided in an embodiment of the present application is shown in FIG. 1 , wherein the display panel 100 has a display area AA and a frame area BB. The display panel includes:

[0033] A plurality of sub-pixels P are arranged in the display area AA, and the sub-pixels P are electrically connected to the data lines DATA;

[0034] A touch electrode 200 located in the display area AA;

[0035] A touch signal line TP electrically connected to the touch electrode 200;

[0036] A test circuit 11 is arranged in the border area BB; the test circuit 11 comprises a signal transmission line TPX, and the signal transmission line TPX is electrically connected to the touch signal line TP;

[0037] Connecting line 13, connecting line 13 corresponds to data line DATA one by one. In the test phase, signal transmission line TPX is connected to data line DATA through connecting line 13, and signal transmission line TPX inputs test signal to data line DATA. In the non-test phase, connecting line 13 and test circuit 11 are disconnected, and signal transmission line TPX outputs touch signal detected by touch electrode.

[0038] It should be noted that Figure 1 Only one touch electrode 200 is shown in the figure. The display panel has multiple touch electrodes 200, and the multiple touch electrodes 200 are arranged in an array. The present application does not limit the specific number and arrangement of the touch electrodes 200. The touch electrode 200 and the touch signal line TP are on different layers, and the two can be connected through vias. In order to reduce the connection impedance, the touch electrode 200 and the electrically connected touch signal line TP can be connected through multiple vias. Figure 1 Vias are not shown.

[0039] A metal layer can be added to the display panel separately to make the touch electrode 200, or an existing metal layer in the display panel can be reused as the touch electrode 200. For example, when the display panel is an LCD panel, the common electrode can be reused as the touch electrode 200. When the display panel is an OLED panel, the OLED sub-pixel needs to be encapsulated and protected by an encapsulation layer, and a metal layer is added to the side of the encapsulation layer away from the OLED sub-pixel to form the touch electrode 200. In the embodiment of the present application, the implementation method of the touch electrode 200 is not specifically limited.

[0040] The data line DATA may be electrically connected to the display control chip 14 located in the border area BB. In the non-testing stage, the display control chip 14 provides a data signal to the sub-pixel P through the data line DATA to realize the light-emitting display of the sub-pixel P.

[0041] In the display panel provided by the technical solution of the present application, in the test phase, the signal transmission line TPX of the test circuit 11 can not only provide a test signal to the data line DATA through the connecting line 13 to realize panel testing (such as VT testing), but also can test whether there is a disconnection of the data line DATA or a bad sub-pixel P based on the display image of the display panel when the test signal is input. In the non-test phase, the signal transmission line TPX can also obtain and output the touch signal detected by the touch electrode 200 to the touch chip through the touch signal line TP, and the touch chip realizes touch detection based on the touch signal. It can be seen that the signal transmission line TPX in the test circuit 11 can be used for both panel testing and touch detection, reducing the number of lines.

[0042] In the technical solution of the present application, after the test phase is completed, the connection line 13 between the test circuit 11 and the data line DATA can be directly cut off, so as to realize the disconnection between the connection line 13 and the test circuit 11 in the non-test phase. Figure 1 As shown by the dotted line L, the connection line 13 between the test circuit 11 and the data line DATA can be cut by laser. Alternatively, a switch element is set in the connection line 13 between the test circuit 11 and the data line DATA, and the connection line 13 between the test circuit 11 and the data line DATA is disconnected by the switch element.

[0043] During the test phase, the test circuit 11 inputs a test signal to the data line DATA through the signal transmission line TPX. At this time, the touch signal line TP is electrically connected to the signal transmission line TPX, and the signal transmission line TPX serves as an input signal line. Although the touch line TP inputs a test signal, it does not affect the test effect.

[0044] In the prior art, the test circuit is only used for VT testing. When the VT test is completed, the test circuit will be abandoned. In the technical solution of the present application, the test circuit 11 can perform panel testing in the test phase, and in the non-test phase, it can be used as a selection circuit for touch detection, outputting the touch signal detected by the touch electrode 200 for touch detection.

[0045] like Figure 2 As shown, Figure 2 A schematic diagram of another display panel structure provided in an embodiment of the present application, based on Figure 1 As shown, Figure 2 In the display panel shown, the test circuit 11 has a plurality of first selection transistors T1; the test circuit 11 also has a switch signal line sw.

[0046] The first selection transistor T1 has a gate, a first electrode, and a second electrode. The gate of the first selection transistor T1 is electrically connected to the switch signal line sw, the first electrode of the first selection transistor T1 is electrically connected to the touch signal line TP, and is electrically connected to the corresponding data line DATA through the connecting line 13, and the second electrode of the first selection transistor T1 is electrically connected to the signal transmission line TPX. The conduction state of the first selection transistor T1 is controlled by the switch signal line sw. In the embodiment of the present application, one of the first electrode and the second electrode of the selection transistor is a drain, and the other is a source.

[0047] The first selection transistors T1 are electrically connected to the data lines DATA in a one-to-one correspondence, and different first selection transistors T1 are electrically connected to different data lines DATA. The first electrode of each first selection transistor T1 is electrically connected to the corresponding data line DATA through a separate connection line 13. In the test phase, the conduction state of the first selection transistor T1 is controlled by the switch signal line sw, so that the test signal is provided to the data line through the signal transmission line TPX to implement panel testing. In the non-test phase, the conduction state of the first selection transistor T1 is controlled by the switch signal line sw, and the touch signal output by the touch electrode 200 is obtained through the signal transmission line TPX to implement touch detection.

[0048] The test circuit has a plurality of gating circuit units 111, and at least some of the gating circuit units 111 include a plurality of first gating transistors T1. The gating circuit unit 111 is provided with a plurality of first gating transistors, which can reduce the equivalent impedance between the touch signal line TP and the electrically connected gating circuit unit 111. In the same gating circuit unit 111, the first gating transistor T1 is electrically connected to the same touch signal line TP, signal transmission line TPX and switch signal line sw. In this manner, the same gating circuit unit 111 can provide test signals to a plurality of data lines DATA at the same time through the same signal transmission line TPX, and the plurality of first gating transistors T1 can be controlled based on the same switch signal line sw, thereby reducing the number of signal transmission lines TPX and switch signal lines sw.

[0049] exist Figure 2 The figure shows only one gating circuit unit 111, and the gating circuit unit 111 has four first gating transistors T1. The number of the first gating transistors T1 in the same gating circuit unit 111 can be set to any number based on the requirements, and is not limited to the following. Figure 2The number of four shown can also be set to 3 or 6. The number of the gating circuit units 111 can be set based on the number of data lines DATA in the display panel and the number of first gating transistors T1 in each gating circuit unit 111. In the embodiment of the present application, the number of data lines DATA in the display panel and the number of gating circuit units 111 are not specifically limited.

[0050] like Figure 3 and Figure 4 As shown, Figure 3 A schematic diagram of a test circuit provided in an embodiment of the present application is shown in FIG. Figure 4 for Figure 3 The schematic diagram of the structure of the gating circuit unit in the test circuit shown in FIG. Figure 2-Figure 4 As shown, the test circuit 11 has multiple gating circuit groups 10, and the gating circuit group 10 has multiple gating circuit units 111; in the same gating circuit group 10, the gating circuit units 111 are electrically connected to the same signal transmission line TPX; the gating circuit units 111 in different gating circuit groups 10 are electrically connected to different signal transmission lines TPX.

[0051] In the embodiment of the present application, a gating circuit group 10 is provided to include a plurality of gating circuit units 111, and a plurality of gating circuit units 111 in the same gating circuit group 10 share the same signal transmission line TPX, thereby greatly reducing the number of signal transmission lines TPX.

[0052] The number of the first enable transistors T1 in each enable circuit unit 111 can be set to be the same, and the number of the enable circuit units 111 in each enable circuit group 10 can be set to be the same, so as to facilitate circuit layout, test drive and touch detection. In other ways, the number of the first enable transistors T1 in each enable circuit unit 111 can be set to be different, and the number of the enable circuit units 111 in each enable circuit group 10 can be set to be different. Alternatively, the number of the first enable transistors T1 in some enable circuit units 111 can be set to be the same, and the number of the first enable transistors T1 in another part of the enable circuit units 111 can be different. Similarly, the number of the enable circuit units 111 in some enable circuit groups 10 can be set to be different, and the number of the enable circuit units 111 in another part of the enable circuit groups 10 can be different. This is not limited here.

[0053] Combination Figure 3 and Figure 4As shown, each gating circuit group 10 includes Y gating circuit units 111, where Y is a positive integer greater than 1; in the same gating circuit group 10, the gating circuit units 111 are respectively connected to a switch signal line sw, and the gating circuit groups 10 are electrically connected to Y switch signal lines sw, and each gating circuit group 10 is electrically connected to the same Y switch signal lines. In the embodiment of the present application, Y=30 is used as an example for explanation, and each gating circuit group 10 includes 30 gating circuit units 111, which are electrically connected to 30 switch signal lines sw and 30 touch signal lines TP. Obviously, Y can be set to any positive integer greater than 1 based on demand, and is not limited to Y being 30. In the embodiment of the present application, there is no limitation on the value of Y.

[0054] In the embodiment of the present application, the same gating circuit group 10 is electrically connected to Y switch signal lines sw. In the same gating circuit group 10, the Y switch signal lines sw are electrically connected to the gating circuit units 111 in a one-to-one correspondence, and different gating circuit units 111 are electrically connected to different switch signal lines sw. All gating circuit groups 10 share the Y switch signal lines sw, thereby greatly reducing the number of switch signal lines sw.

[0055] Combination Figure 3 and Figure 4 As shown, the test circuit 11 has N gating circuit groups 10, where N is a positive integer greater than 1; the arrangement and extension direction of the gating circuit units 111 in the gating circuit group 10 is a first direction F1, and the plurality of gating circuit units 111 are arranged in sequence in a straight line direction, which is the extension direction thereof, and the first direction F1 is parallel to the straight line; in the same gating circuit group 10, along the first direction F1, Y ( Figure 4 The value of Y is 30) the gating circuit unit 111 is sequentially the 1st gating circuit unit to the Yth gating circuit unit. Along the second direction Y, the switch signal line sw is sequentially the 1st switch signal line sw1 to the Yth switch signal line swY. The test circuit 11 has N ( Figure 3 Where N is 12) signal transmission line TPX, along the first direction F1, the signal transmission lines TPX are sequentially the first signal transmission line TPX1 to the Nth signal transmission line TPXN. Among them, in the gating circuit group 10, the yth gating circuit unit is electrically connected to the yth switch signal line swy, y is a positive integer not greater than Y; the gating circuit unit 111 in the nth gating circuit group is electrically connected to the nth signal transmission line TPXn, n is a positive integer not greater than N. The second direction F2 is perpendicular to the first direction F1.

[0056] By setting the values ​​of Y and N, multiple gating circuit units 111 in the same gating circuit group 10 can share the same signal transmission line TPX, and different gating circuit groups 10 can share Y switch signal lines sw, which greatly reduces the number of signal transmission lines TPX and switch signal lines sw. In addition, multiple gating circuit groups 10 are arranged in sequence in the first direction F1, and the corresponding electrically connected multiple signal transmission lines TPX are arranged in sequence in the first direction F1, and multiple switch signal lines common to multiple gating circuit groups 10 are arranged in sequence in the second direction F2, which is convenient for wiring and does not require complicated winding.

[0057] In the embodiment of the present application, the first direction F1 may be set to be perpendicular to the extension direction of the data line DATA in the display area AA, and the second direction F2 may be set to be parallel to the extension direction of the data line DATA in the display area AA, and point from the display area AA to the test circuit 11 .

[0058] In the non-testing stage, when performing touch detection, the same gating circuit group 10 is connected to Y touch signal lines TP to perform touch detection in time division to determine the touch signal line TP outputting the touch signal at the current moment.

[0059] The values ​​of Y and N are related to the number of data lines DATA in the display panel, and can be set based on demand, and the embodiments of the present application do not specifically limit this. For example, taking a display panel having 1440 columns of sub-pixels as an example, each column of sub-pixels is electrically connected to a data line DATA, and there are 1440 data lines DATA in total, N=12, Y=30 can be set, and each gating circuit unit 111 has 4 first gating transistors T1, 4*Y*N=1440.

[0060] For example, taking Y=30 and N=12, in the first direction F1, Figure 4 The 30 gate circuit units 111 in the first gate circuit group are sequentially the first gate circuit unit to the 30th gate circuit unit, and are correspondingly electrically connected to the first touch signal line TP1 to the 30th touch signal line TP30. Figure 3In the embodiment, there are 30 switch signal lines sw, which are sequentially from the first switch signal line sw1 to the 30th switch signal line sw30 in the second direction F2, and there are 12 gating circuit groups 10, which are electrically connected to 12 signal transmission lines TPX, which are sequentially from the first signal transmission line TPX1 to the 12th signal transmission line TPX12, and there are 360 ​​touch signal lines TP in total, which are sequentially from the first touch signal line TP1 to the 360th touch signal line TP1 in the first direction F1. Touch signal line TP360, the 30 enabling circuit units 111 in the 1st enabling circuit group correspond to the electrical connection of the 1st touch signal line TP1 to the 30th touch signal line TP30, the 30 enabling circuit units 111 in the 2nd enabling circuit group correspond to the electrical connection of the 31st touch signal line TP31 to the 60th touch signal line TP60,…, the 30 enabling circuit units 111 in the 12th enabling circuit group correspond to the electrical connection of the 331st touch signal line TP331 to the 360th touch signal line TP360.

[0061] It can be seen that for a display panel with 1440 columns of sub-pixels, based on the technical solution of the embodiment of the present application, the same selection circuit unit 111 can provide test signals for 4 data lines at the same time, and only requires 30 switch signal lines sw and 12 signal transmission lines TPX, greatly reducing the number of wiring.

[0062] like Figure 5 As shown, Figure 5 A schematic diagram of a display array in a display panel provided in an embodiment of the present application, wherein the display panel has a display array, wherein the display array has a plurality of sub-pixels P arranged in an array, and wherein the display array has three color sub-pixels P, and the three color sub-pixels P are red sub-pixels R, green sub-pixels G, and blue sub-pixels B, respectively. The colors of any three adjacent sub-pixels P in the same row are set to be different. In any two adjacent columns of sub-pixels P, one column of sub-pixels P is arranged alternately with red sub-pixels R and blue sub-pixels B, and the other sub-pixels P are all green sub-pixels G. Thus, each pixel unit has four sub-pixels P, and the four sub-pixels P form a 2×2 Bayer array, with one blue sub-pixel B, one red sub-pixel R, and two green sub-pixels G. Such an arrangement can simulate the human eye's sensitivity to green to achieve color restoration, and at the same time, this arrangement facilitates color restoration.

[0063] It should be noted that the number of rows and columns of sub-pixels P in the display array is set based on demand. Figure 5 This is only a schematic illustration and does not represent the actual number of rows and columns of sub-pixels P in the display panel. In addition, in the display panel provided in the embodiment of the present application, the arrangement of sub-pixels P in the display array is not limited to Figure 5The arrangement shown in the figure may also be RYYB, RGBW or other arrangements, which are not specifically limited in the embodiments of the present application.

[0064] like Figure 6 As shown, Figure 6 A schematic diagram of another test circuit provided in an embodiment of the present application, combined with Figure 2-Figure 6 As shown, the border area BB has a plurality of second selection transistors T2 corresponding to the first selection transistors T1 one by one, and the second selection transistors T2 and the first selection transistors T1 both have a gate, a first electrode, and a second electrode. The first electrode of the second selection transistor T2 is electrically connected to the first electrode of the corresponding first selection transistor T1; wherein, in the test phase, the first selection transistor T1 and the second selection transistor T2 are turned on in time-sharing manner to respectively provide test signals for the electrically connected data lines DATA, and after the test phase, the gate of the second selection transistor T2 inputs a turn-off signal, so that the second electrode of the second selection transistor T2 is disconnected from the data line DATA.

[0065] In an embodiment of the present application, the first selection transistor T1 already existing in the panel is reused to form the test circuit 11 of the present application. During the test phase, the first selection transistor T1 in the test circuit 11 of the present application and the second selection transistor T2 already existing in the panel are used to provide test signals to the sub-pixel P in the same data line DATA in a time-sharing manner, thereby increasing the test efficiency.

[0066] The first selection transistor T1 can be set to PMOS or NMOS based on requirements, and the second selection transistor T2 can be set to PMOS or NMOS based on requirements.

[0067] Figure 6 Three adjacent data lines DATA are shown in i-1 ,DATA i and DATA i+1 , each data line is connected to a first selection transistor T1 and a second selection transistor T2. The gates of the three first selection transistors T1 are respectively electrically connected to a switch signal line sw, and the switch signal line sw is used to control the conduction state of the first selection transistor T1. The gates of the second transistors T2 are respectively electrically connected to a control signal line sw' to control the conduction state of the second selection transistor T2. When the test is completed, the control signal line sw' inputs a constant shutdown signal, so that the second selection transistor T2 is turned off, so that the second electrode of the second selection transistor T2 is disconnected from the data line DATA.

[0068] The technical solution of the present application reuses the first selection transistor T1 in the shorting bar of the VT test in the display panel to form a selection circuit unit 111. Specifically, the second electrodes of four first selection transistors T1 that input the same color sub-pixel test signal are short-circuited to form a selection circuit unit 111. For example, the second electrodes of four first selection transistors T1 that input the red sub-pixel test signal r are short-circuited to form a selection circuit unit 111, the second electrodes of four first selection transistors T1 that input the green sub-pixel test signal g are short-circuited to form a selection circuit unit 111, and the second electrodes of four first selection transistors T1 that input the blue sub-pixel test signal b are short-circuited to form a selection circuit unit 111.

[0069] The display area AA is assumed to have M data lines DATA sequentially arranged in the first direction F1, where M is a positive integer and a multiple of 3. The M data lines DATA are sequentially arranged from the first data line DATA1 to the Mth data line DATA in the first direction F1. M The M data lines DATA include three data line groups, which are the first data line group, the second data line group and the third data line group. The M data lines DATA are connected to the M first selection transistors T1. In the first direction F1, the M first selection transistors T1 can be arranged in sequence based on the connected data lines DATA, or can be arranged in sequence in the first direction F1 in other sorting ways. Flexible line layout can be achieved through cross-lines and vias, which is not specifically limited in the embodiments of the present application.

[0070] A plurality of data lines DATA in the first data line group satisfy the first general formula a m =3m-2, that is, the first data line DATA1, the fourth data line DATA4, the seventh data line DATA7, ..., the ath data line m Data line DATA 3m-2 All belong to the first data line group.

[0071] The plurality of data lines DATA in the second data line group satisfy the second general formula b m =3m-1, that is, the second data line DATA2, the fifth data line DATA5, the eighth data line DATA8, ..., the bth data line m Data line DATA 3m-1 All belong to the second data line group.

[0072] The plurality of data lines DATA in the third data line group satisfy the third formula c m =3m, namely, the third data line DATA3, the sixth data line DATA6, the ninth data line DATA9, ..., the cth data line m Data line DATA 3mAll belong to the third data line group.

[0073] Among them, a m 、b m and c m All are less than M. m is related to M, m=M / 3.

[0074] In the same data line group, the data lines DATA are respectively connected to a first selection transistor T1. In the test phase, the second electrodes of the first selection transistors T1 are all input with the test signal of the same color sub-pixel. Figure 6 For example, the second electrode of the first selection transistor T1 connected to each data line DATA in the first data line group can be set to input the red sub-pixel test signal r during the test phase, the second electrode of the first selection transistor T1 connected to each data line DATA in the second data line group can be set to input the green sub-pixel test signal g during the test phase, and the second electrode of the first selection transistor T1 connected to each data line DATA in the third data line group can be set to input the blue sub-pixel test signal b during the test phase.

[0075] In the same data line group, all data lines DATA are divided into a plurality of data line subgroups, each data line subgroup has X data lines DATA arranged in sequence in the first direction F1, X is a positive integer greater than 1, and m is an integer multiple of X. X first selection transistors T1 electrically connected to the X data lines DATA in the same data line subgroup form a selection circuit unit 111, and if X=4, each selection circuit unit 111 has four first selection transistors T1. In the same data line group, Y adjacent selection circuit units 111 are set as a selection circuit group 10.

[0076] For example, M=1440, X=4, and Y=30. In the same data line group, there are 480 data lines DATA, and the corresponding 480 first selection transistors T1 are divided into 120 selection circuit units 111. The 120 selection circuit units 111 are divided into 4 selection circuit groups 10. Three data line groups form 12 selection circuit groups 10. Each selection circuit group 10 is electrically connected to 30 touch signal lines TP, totaling 30*12 touch signal lines TP. In this way, the same selection circuit group 10 is connected to 30 touch signal lines TP, and the touch signal is output in time-sharing through the same signal transmission line TPX, requiring a total of 12 signal transmission lines TPX. The signal transmission line TPX is connected to the touch chip, and the touch chip is used to perform touch detection based on the touch signal. The touch chip and the display control chip 14 can be the same chip. In this case, the display control chip is not only used to drive the sub-pixel P for image display, but also can perform touch detection based on the touch signal output by the signal transmission line TPX, or the touch chip and the display control chip 14 are two independent chips.

[0077] For example, for the first data line group, 30 gate circuit units 111 connected to the red sub-pixel test signal r constitute a gate circuit group 10, and the corresponding 30 touch signal lines TP output touch signals in time-sharing through the same signal transmission line TPX.

[0078] like Figure 7 As shown, Figure 7 The schematic diagram of the arrangement of the signal transmission lines in the display panel provided in the embodiment of the present application, in the test stage, in order to facilitate the probe to uniformly input the same color sub-pixel test signal, a plurality of signal transmission line groups are set, and the signal transmission line group has a plurality of signal transmission lines TPX; the plurality of signal transmission lines TPX in the same signal transmission line group are arranged adjacently. All signal transmission lines TPX can be arranged in sequence in the first direction F1. For example, three signal transmission line groups 21, 22, and 23 can be set.

[0079] All signal transmission lines TPX for inputting red sub-pixel test signals r can be arranged adjacent to each other, all signal transmission lines TPX for inputting green sub-pixel test signals g can be arranged adjacent to each other, and all signal transmission lines TPX for inputting blue sub-pixel test signals b can be arranged adjacent to each other, so as to facilitate the connection test between the test signal input probe and the signal transmission line TPX. As described in the above embodiment, when there are 1440 data lines DATA and 12 signal transmission lines TPX are set correspondingly, there are 4 signal transmission lines TPX for inputting red sub-pixel test signals r, and the 4 signal transmission lines TPX are arranged adjacent to each other in sequence, forming a transmission line group 21; there are 4 signal transmission lines TPX for inputting green sub-pixel test signals g, and the 4 signal transmission lines TPX are arranged adjacent to each other in sequence, forming a transmission line group 22; there are 4 signal transmission lines TPX for inputting blue sub-pixel test signals b, and the 4 signal transmission lines TPX are arranged adjacent to each other in sequence, forming a transmission line group 23.

[0080] In the embodiment of the present application, the display panel has a plurality of sub-pixels P, and the plurality of sub-pixels include: a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels; for example, the first sub-pixel can be set as a red sub-pixel R, the second sub-pixel can be set as a green sub-pixel G, and the third sub-pixel can be set as a blue sub-pixel B. There are three signal transmission line groups 21, 22, and 23; at the same time in the test phase, a plurality of signal transmission lines TPX in the same signal transmission line group input the same test signal, and the three signal transmission line groups are used for different test signals respectively. In this way, the signal transmission lines TPX corresponding to the first data line group mentioned above all input the red sub-pixel test signal r, the signal transmission lines TPX corresponding to the second data line group all input the green sub-pixel test signal, and the signal transmission lines TPX corresponding to the third data line group all input the blue sub-pixel test signal, and the display test of all sub-pixels is realized through the second selection transistor T2 corresponding to the first selection transistor T1.

[0081] like Figure 8 As shown, Figure 8 The schematic diagram of the arrangement of the switch signal lines in the display panel provided in the embodiment of the present application, in the test stage, in order to facilitate the contact between the probe and the switch signal line sw, so that the first selection transistor T1 is turned on for testing, all the switch signal lines sw are arranged adjacent to each other in sequence, and there are no other wirings between adjacent switch signal lines sw. The switch signal lines sw can be arranged in sequence in the second direction F2. The switch signal lines sw can be connected to the touch chip, and during touch detection, a control signal is provided to it through the touch chip to control its conduction state. As mentioned above, when there are 30 switch signal lines sw, the 30 switch signal lines sw can be sequentially from the 1st switch signal line sw1 to the 30th switch signal line sw30 in the second direction F2.

[0082] like Fig. 9 As shown, Fig. 9 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, combined with Figure 2-Figure 4 , Figure 6 and Fig. 9 The border area BB has a binding area CC, and the binding area CC has a pad electrically connected to the data line DATA, and the pad is used to fix the display control chip 14; the first selection transistor T1 is located on the side of the binding area CC away from the display area AA, and the selection circuit unit 111 is located on the side of the binding area CC away from the display area AA. The multiple connection lines 13 connected to the same selection circuit unit 111 can be arranged continuously and adjacently in the first direction F1, which is convenient for subsequent unified cutting and disconnection. It should be noted that Fig. 9The gating circuit unit 111 is shown, and the position of the gating circuit unit 111 is used to represent the position of the first gating transistor T1 relative to the binding region CC. The first gating transistor T1 is not shown, and the structure and connection principle of the first gating transistor T1 can refer to the above description.

[0083] like Fig.10 As shown, Fig.10 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, combined with Figure 2-Figure 4 , Figure 6 , Fig. 9 and Fig.10 The border area BB has a plurality of second selection transistors T2 corresponding to the data lines DATA one by one, and the second selection transistor T2 has a gate, a first electrode, and a second electrode; the first electrode of the second selection transistor T2 is electrically connected to the first electrode of the corresponding first selection transistor T1; the second selection transistor T2 is located between the display area AA and the binding area CC. The first selection transistor T1 and the second selection transistor T2 are respectively arranged on both sides of the binding area CC, so as to facilitate the cutting and disconnection of the connection line 13 connected to the selection circuit unit 111. It should be noted that Fig.10 The gating circuit unit 111 is shown, and the position of the first gating transistor T1 relative to the binding area CC is represented by the position of the gating circuit unit 111, and the first gating transistor T1 is not shown. The structure and connection principle of the first gating transistor T1 can refer to the above description; the position of the second gating transistor T2 relative to the binding area CC is represented by the position of the circuit module corresponding to the gating circuit unit 111 one by one, and the second gating transistor T2 is not shown. The circuit module includes four second gating transistors T2 corresponding to the gating circuit unit 111.

[0084] In the embodiment of the present application, the sub-pixel P has a pixel transistor. The first selection transistor T1 and the second selection transistor T2 are in the same layer as the pixel transistor, and the first selection transistor T1 and the second selection transistor T2 are formed at the same time as the pixel transistor, and there is no need to manufacture the first selection transistor T1 and the second selection transistor T2 by a separate process, so the manufacturing process is simple and the manufacturing cost is low.

[0085] In the embodiment of the present application, the sub-pixel has a pixel transistor; the first selection transistor T1 is in the same layer as the pixel transistor. Based on wiring requirements, the second transistor T2 is in the same layer as the pixel transistor or in a different layer.

[0086] The display panel in the embodiment of the present application may be an LCD panel or an OLED panel. The OLED panel may be a hard panel or a flexible panel.

[0087] In the embodiment of the present application, as described above, the number of first selection transistors T1 in each selection circuit unit 111 can be set to be the same. In other embodiments, Fig.11 As shown, the first gate transistor T1 in the gate circuit unit 111 is set differently.

[0088] like Fig.11 As shown, Fig.11 A schematic diagram of the structure of another display panel provided in an embodiment of the present application, based on the above embodiment, Fig.11 In the shown manner, the signal transmission line TP is used to connect the touch chip; the display panel has a plurality of touch electrodes 200, the plurality of touch electrodes 200 include at least a first touch electrode 201 and a second touch electrode 202, the distance from the first touch electrode 201 to the touch chip is greater than the distance from the second touch electrode 202 to the touch chip; wherein, the number of first selection transistors T1 in the selection circuit unit 111 correspondingly connected to the first touch electrode 201 is greater than the number of first selection transistors T1 in the selection circuit unit 111 correspondingly connected to the second touch electrode 202.

[0089] Fig.11 In the example, the first touch electrode 201 is connected to a gating circuit unit 111 with four first gating transistors T1, and the second touch electrode 202 is connected to a gating circuit unit 111 with two first gating transistors T1. The number of first gating transistors T1 connected to each touch electrode 200 can be set based on the needs, and is not limited to Figure 4 The method shown.

[0090] Since the distance between the touch electrode 200 and the touch chip is different, the length of the connection between the two is different. The different lengths of the connection lead to uneven impedance, which affects the accuracy of touch control. Fig.11 In the manner shown, a touch electrode 200 having a greater distance from the touch chip is connected to a smaller number of first selection transistors T1, and a touch electrode 200 having a smaller distance from the touch chip is connected to a larger number of first selection transistors T1, thereby reducing the difference in connection resistance of touch electrodes 200 having different distances from the touch chip and improving touch accuracy.

[0091] It should be noted that, in the technical solution of the present application, a plurality of touch electrodes 200 may be arranged in an array, and the distance between the touch electrode 200 and the touch chip is the distance in the opposite direction of the extension of the touch trace TP in the display area AA. In the touch electrodes 200 arranged in the array, if the extension direction is the column direction of the array, the distances between each touch electrode 200 and the touch chip in the same column are not the same, and the number of first selection transistors T1 connected to each touch electrode 200 gradually increases from the display area to the direction of the touch chip, and the distances between each touch electrode 200 and the touch chip in the same row are the same, and the same number of first selection transistors T1 are connected to the touch chip accordingly.

[0092] Based on the above embodiments, another embodiment of the present application further provides an electronic device, such as Fig.12 As shown, Fig.12 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device includes a display panel 41. The display panel 41 is a display panel of any one of the above embodiments.

[0093] The electronic device may be a mobile phone, a tablet computer, or a smart wearable device, etc. The electronic device may use the display panel of the above embodiment to reduce the number of wirings and facilitate narrow frame and full screen design.

[0094] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the electronic device disclosed in the embodiment, since it corresponds to the display panel disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the corresponding part of the display panel.

[0095] It should be noted that in the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0096] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0097] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel has a display area and a frame area, and the display panel includes: A plurality of sub-pixels are arranged in the display area, and the sub-pixels are electrically connected to the data lines; A touch electrode located in the display area; A touch signal line electrically connected to the touch electrode; A test circuit is disposed in the border area; the test circuit comprises a signal transmission line, and the signal transmission line is electrically connected to the touch signal line; A connecting line, wherein the connecting line corresponds to the data line one by one, in a test phase, the signal transmission line is connected to the data line through the connecting line, and the signal transmission line inputs a test signal to the data line, and in a non-test phase, the connecting line is disconnected from the test circuit, and the signal transmission line outputs a touch signal detected by the touch electrode; After the test phase is completed, the connection line between the test circuit and the data line is cut off, so that the connection line is disconnected from the test circuit in the non-test phase; The test circuit has a plurality of gating circuit units sequentially arranged along a first direction, the gating circuit units include a plurality of first gating transistors, each having a gate, a first electrode, and a second electrode; the test circuit also has a switch signal line; the gate of the first gating transistor is electrically connected to the switch signal line, the first electrode of the first gating transistor is electrically connected to the touch signal line, and is electrically connected to the corresponding data line through the connecting line, and the second electrode of the first gating transistor is electrically connected to the signal transmission line; The border area has a binding area, the binding area has a pad electrically connected to the data line, and the pad is used to fix the electrically connected display control chip; the first selection transistor is located on the side of the binding area away from the display area; the multiple connecting lines connected to the same selection circuit unit are arranged continuously and adjacently in the first direction.

2. The display panel according to claim 1, characterized in that: In the same selection circuit unit, the first selection transistor is electrically connected to the same touch signal line, the signal transmission line and the switch signal line, and the first selection transistor is electrically connected to the data line in a one-to-one correspondence.

3. The display panel according to claim 2, characterized in that: The signal transmission line is used to connect the touch control chip; The display panel has a plurality of touch electrodes, the plurality of touch electrodes at least include a first touch electrode and a second touch electrode, and a distance from the first touch electrode to the touch chip is greater than a distance from the second touch electrode to the touch chip; The number of the first gating transistors in the gating circuit unit correspondingly connected to the first touch control electrodes is greater than the number of the first gating transistors in the gating circuit unit correspondingly connected to the second touch control electrodes.

4. The display panel according to claim 2, characterized in that: The test circuit has a plurality of gating circuit groups, and the gating circuit group has a plurality of the gating circuit units; In the same gating circuit group, the gating circuit units are electrically connected to the same signal transmission line; and the gating circuit units in different gating circuit groups are electrically connected to different signal transmission lines.

5. The display panel according to claim 4, characterized in that: Each of the gating circuit groups includes Y gating circuit units, where Y is a positive integer greater than 1; in the same gating circuit group, the gating circuit units are respectively connected to one of the switch signal lines, the gating circuit groups are electrically connected to Y of the switch signal lines, and each of the gating circuit groups is electrically connected to the same Y switch signal lines.

6. The display panel according to claim 5, characterized in that: The test circuit has N gating circuit groups, where N is a positive integer greater than 1; in the same gating circuit group, along the first direction, the Y gating circuit units are sequentially from the 1st gating circuit unit to the Yth gating circuit unit; Along the second direction, the switch signal lines are sequentially the 1st switch signal line to the Yth switch signal line; the second direction is perpendicular to the first direction; The test circuit has N signal transmission lines, and along the first direction, the signal transmission lines are sequentially from the first signal transmission line to the Nth signal transmission line; Among them, in the gating circuit group, the yth gating circuit unit is electrically connected to the yth switch signal line, y is a positive integer not greater than Y; the gating circuit unit in the nth gating circuit group is electrically connected to the nth signal transmission line, n is a positive integer not greater than N.

7. The display panel according to claim 1, characterized in that: The border area has a plurality of second gating transistors corresponding to the first gating transistors one by one, the second gating transistors having a gate, a first electrode and a second electrode; the first electrode of the second gating transistor is electrically connected to the first electrode of the corresponding first gating transistor; Among them, during the test phase, the first selection transistor and the second selection transistor are turned on in a time-sharing manner to provide the test signal to the electrically connected data lines respectively. After the test phase, the gate of the second selection transistor inputs a shutdown signal to disconnect the second electrode of the second selection transistor from the data line.

8. The display panel according to claim 1, characterized in that: The border area has a plurality of second selection transistors corresponding to the data lines one by one, the second selection transistors having a gate, a first electrode and a second electrode; the first electrode of the second selection transistor is electrically connected to the first electrode of the corresponding first selection transistor; The second gate transistor is located between the display area and the binding area.

9. The display panel according to claim 7 or 8, characterized in that: The sub-pixel has a pixel transistor; The first selection transistor and the second selection transistor are in the same layer as the pixel transistor.

10. The display panel according to claim 1, characterized in that: The sub-pixel has a pixel transistor; The first selection transistor and the pixel transistor are in the same layer.

11. The display panel according to claim 1, characterized in that: A plurality of signal transmission line groups are provided, wherein the signal transmission line group has a plurality of the signal transmission lines; A plurality of the signal transmission lines in the same signal transmission line group are arranged adjacent to each other.

12. The display panel according to claim 11, characterized in that: The plurality of sub-pixels include: a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels; There are three signal transmission line groups; at the same time in the test phase, multiple signal transmission lines in the same signal transmission line group input the same test signal, and the three signal transmission line groups are used for different test signals respectively.

13. An electronic device, characterized in that: Comprising the display panel as described in any one of claims 1-12.

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