Power and data routing structure for organic light emitting diode displays

Abstract

The present disclosure relates to power and data routing structures for organic light emitting diode displays, and discloses an organic light emitting diode display that can have thin film transistor circuitry formed on a substrate. The display and substrate can have rounded corners. A pixel definition layer can be formed on the thin film transistor circuitry. Openings in the pixel definition layer can be provided with emissive material that overlaps respective anodes of organic light emitting diodes. A cathode layer can cover the array of pixels. A ground power path can be used to distribute a ground voltage to the cathode layer. The ground power path can be formed from a metal layer that is shorted to the cathode layer using a portion of the metal layer that forms an anode of a diode, can be formed from a grid-like metal pattern, can have L-shaped path segments, can include laser-deposited metal on the cathode layer, and can have other structures that facilitate distribution of the ground power.

Description

[0001] This application is a divisional application of the invention patent application with application number 201780003465.4, application date January 19, 2017, entitled "Power Supply and Data Routing Structure for Organic Light Emitting Diode Display". Technical Field

[0002] This invention relates generally to electronic devices, and more particularly to electronic devices having an organic light-emitting diode display. Background Technology

[0003] Electronic devices typically include displays. For example, an electronic device may have an organic light-emitting diode (OLED) display based on OLED pixels. Each pixel may have pixel circuitry including a corresponding light-emitting diode. Thin-film transistor (TFT) circuitry in the pixel circuitry can be used to control the application of current to the light-emitting diode in that pixel. The TFT circuitry may include a driving transistor. The driving transistor and the light-emitting diode in the pixel circuitry may be connected in series between a positive power supply and a ground power supply.

[0004] Signals in OLED displays, such as power signals, can suffer unwanted voltage drops due to resistive losses in the conductive paths used to distribute these signals. These voltage drops can, if not carefully managed, impede the proper functioning of the OLED display. Distributing power and data signals in displays with layouts limited by signal routing space also presents challenges.

[0005] Therefore, it is desirable to provide an improved method for distributing signals such as power and data signals on displays such as organic light-emitting diode displays. Summary of the Invention

[0006] Organic light-emitting diode (OLED) displays may have thin-film transistor (TFT) circuitry formed on a substrate. Both the display and the substrate may have rounded corners. A pixel definition layer may be formed on the TFT circuitry. Openings in this pixel definition layer may contain emitting material overlapping with the corresponding anode of the organic light-emitting diode.

[0007] The cathode layer may cover the pixel array. A ground power path can be used to distribute a ground voltage to the cathode layer. The ground power path may be formed of a metal layer that uses a portion of the metal layer forming the anode of the diode and is shorted to the cathode layer. It may be formed of a grid-like metal pattern, may have L-shaped path segments, may include laser-deposited metal located on the cathode layer, and may have other structures to facilitate the distribution of the ground power. Grid-like metal patterns (e.g., metal power grid paths), metal patterns with L-shaped path segments, and other structures can also be used to facilitate the distribution of positive power supply voltages. These power path structures can accommodate displays and substrates with rounded corners. Attached Figure Description

[0008] Figure 1 This is an illustration of an exemplary electronic device with a display according to an implementation scheme.

[0009] Figure 2 This is a diagram of an exemplary organic light-emitting diode pixel circuit according to an implementation scheme.

[0010] Figure 3 This is an illustration of an exemplary organic light-emitting diode display according to an implementation scheme.

[0011] Figure 4 A cross-sectional side view of a portion of the effective area of ​​an exemplary organic light-emitting diode display according to an embodiment.

[0012] Figure 5 This is a cross-sectional side view of a portion of the invalid boundary region of an exemplary organic light-emitting diode display according to an embodiment.

[0013] Figure 6 This is an illustration of an exemplary grid pattern that can be used as a grounding power path in a display according to an embodiment.

[0014] Figure 7 To illustrate the implementation scheme Figure 6 A diagram illustrating how the grounding power path is used in a display with rounded corners.

[0015] Figure 8 , Figure 9 and Figure 10 An exemplary power path layout for a display with a flexible tail portion is shown according to an embodiment.

[0016] Figure 11 This is a top view of the corner portion of a display having a positive power path structure and a ground power path structure according to the implementation scheme.

[0017] Figure 12 and Figure 13 In accordance with the implementation plan Figure 11 A cross-sectional side view of a portion of the display.

[0018] Figure 14 A top view of the corner portion of a display having a positive signal routing structure and a ground signal routing structure according to another embodiment.

[0019] Figure 15 , Figure 16 and Figure 17 In accordance with the implementation plan Figure 14 A cross-sectional side view of a portion of the display.

[0020] Figure 18This is an illustration of an exemplary display according to an embodiment, having a power path formed by metal lines, a mesh structure (e.g., a metal power mesh path), and strip paths.

[0021] Figure 19 This illustration shows how a display with data lines having stepped sections, according to an embodiment, can accommodate a corner of a circular display signal routing structure.

[0022] Figure 20 This is a cross-sectional side view of a layer in an exemplary organic light-emitting diode display according to an embodiment.

[0023] Figure 21 This is a top view of an exemplary display with a grid of laser-deposited signal lines for reducing power supply voltage drop according to an embodiment.

[0024] Figure 22 In accordance with the implementation plan Figure 21 A cross-sectional side view of a portion of the display.

[0025] Figure 23 and Figure 24 For the manufacturing period according to the implementation plan Figure 21 A cross-sectional side view of a portion of the display.

[0026] Figure 25 , Figure 26 , Figure 27 and Figure 28 For use in displays such as, according to the implementation scheme Figure 21 A top view of an exemplary pattern of paths such as laser-deposited signal lines in a display.

[0027] Figure 29 This is an illustration of an exemplary gate driver circuit formed from thin-film transistor circuitry on a display substrate according to an embodiment.

[0028] Figure 30 This illustration shows how a laterally offset and rotatable gate driver row block, according to an embodiment, accommodates an exemplary display substrate with curved edges.

[0029] Figure 31 This illustration shows how a data line extension overlapping the effective area of ​​the display, according to an embodiment, can be used to route signals from a diagonal data line segment to a vertical portion of the data line in an exemplary display.

[0030] Figure 32 This illustration shows how display driver circuits, such as gate driver row blocks, which can have different shapes in different rows according to an embodiment, can accommodate curved display substrate edges.

[0031] Figure 33 This is a diagram illustrating a test multiplexer circuit for an exemplary display of the type that can be formed from a portion of a thin-film transistor circuit on a display substrate, according to an embodiment.

[0032] Figure 34 This is an illustration of an exemplary display showing how to test signals routed between a test point at the bottom edge of the display and a test multiplexer circuit along the top edge of the display, according to an embodiment.

[0033] Figure 35 This illustration shows an exemplary display in which test multiplexer circuitry and test points are positioned along a portion of the tail of the display substrate on the lower edge of the display, according to an embodiment.

[0034] Figure 36 and Figure 37 This illustration shows an exemplary display in which test circuitry, according to an embodiment, is arranged to accommodate the edge of a bent display substrate. Detailed Implementation

[0035] Figure 1 An exemplary electronic device of the type that may have an organic light-emitting diode display is shown. Electronic device 10 may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device, a smaller device (such as a wristwatch, a wristband device, a headset or handset device, a device embedded in glasses, or other devices worn on a user's head, or other wearable or micro-devices), a display, a computer monitor containing an embedded computer, a computer monitor not containing an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which an electronic device with a display is installed in an information kiosk or a car), or other electronic device.

[0036] like Figure 1 As shown, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10. This storage and processing circuitry may include storage devices such as hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static or dynamic random access memory), and so on. The processing circuitry in control circuitry 16 can be used to control the operation of device 10. This processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application-specific integrated circuits, etc.

[0037] The input-output circuitry in device 10, such as input-output device 12, can be used to allow data to be provided to device 10 and to allow data to be provided from device 10 to external devices. Input-output device 12 may include buttons, joysticks, scroll wheels, touchpads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, LEDs and other status indicators, data ports, etc. Users can control the operation of device 10 by providing commands via input-output device 12 and can use the output resources of input-output device 12 to receive status information and other outputs from device 10.

[0038] Input-output device 12 may include one or more displays, such as display 14. Display 14 may be a touchscreen display including touch sensors for acquiring touch input from a user, or display 14 may be touch-insensitive. The touch sensor of display 14 may be based on a capacitive touch sensor electrode array, an acoustic touch sensor structure, a resistive touch component, a force-based touch sensor structure, a light-based touch sensor, or other suitable touch sensor arrangement. The touch sensor for display 14 may be formed by electrodes formed on a common display substrate having pixels of display 14, or may be formed by a separate touch sensor panel overlapping the pixels of display 14. If desired, display 14 may be touch-insensitive (i.e., the touch sensor may be omitted).

[0039] The control circuit 16 can be used to run software, such as operating system code and applications, on the device 10. During operation of the device 10, the software running on the control circuit 16 can display images on the display 14.

[0040] Display 14 may be an organic light-emitting diode (OLED) display. In an OLED display, each display pixel contains a corresponding organic light-emitting diode. Figure 2 A schematic diagram of an exemplary organic light-emitting diode pixel is shown. Figure 2 As shown, display pixel 22 may include a light-emitting diode 38. A positive power supply voltage ELVDD can be provided to a positive power supply terminal 34, and a ground power supply voltage ELVSS can be provided to a ground power supply terminal 36. Diode 38 has an anode (terminal AN) and a cathode (terminal CD). The state of drive transistor 32 controls the amount of current flowing through diode 38, and thus controls the amount of emitted light 40 from display pixel 22. Since the cathode CD of diode 38 is coupled to ground terminal 36, the cathode terminal CD of diode 38 may sometimes be referred to as the ground terminal of diode 38.

[0041] To ensure that transistor 32 remains in the desired state between consecutive frames of data, display pixel 22 may include a storage capacitor, such as storage capacitor Cst. A first terminal of storage capacitor Cst may be coupled to the gate of transistor 32 at node A, and a second terminal of storage capacitor Cst may be coupled to the anode AN of diode 38 at node B. A voltage on storage capacitor Cst is applied at node A to the gate of transistor 32 to control transistor 32. One or more switching transistors, such as switching transistor 30, may be used to load data into storage capacitor Cst. When switching transistor 30 is off, data line D is isolated from storage capacitor Cst, and the gate voltage at node A is equal to the data value stored in storage capacitor Cst (i.e., the data value from a previous frame of display data displayed on display 14). When a gate line G (sometimes referred to as a scan line) in a row associated with display pixel 22 is determined, switching transistor 30 is turned on, and a new data signal on data line D is loaded into storage capacitor Cst. The new signal on capacitor Cst is applied to the gate of transistor 32 at node A, thereby regulating the state of transistor 32 and regulating the corresponding amount of light 40 emitted by light-emitting diode 38.

[0042] If necessary, use except Figure 2 Configurations other than the one described above (e.g., configurations including circuitry for compensating for threshold voltage variations in the drive transistor 32, configurations where the emitter enable transistor is coupled in series with the drive transistor 32, configurations with multiple switching transistors controlled by multiple corresponding scan lines, configurations with multiple capacitors, etc.) are used to form circuitry for controlling the operation of the light-emitting diodes of the pixels 22 in the display 14 (e.g., display pixel circuitry such as...). Figure 2 (Transistors, capacitors, etc. in the pixel circuit of a display). Figure 2 The circuitry for pixel 22 is merely exemplary.

[0043] like Figure 3 As shown, the display 14 may include layers, such as a substrate layer 24. The substrate 24 and other layers in the display 14 (if desired) may be formed of material layers such as glass layers, polymer layers (e.g., flexible polyimide sheets or other flexible polymers), etc. The substrate 24 may be planar and / or may have one or more curved portions. The substrate 24 may have a rectangular shape with left and right vertical edges and top and bottom horizontal edges, or it may have a non-rectangular shape. In a configuration where the substrate 24 has a rectangular shape with four corners, these corners may be rounded if desired. If desired, the display substrate 24 may have a tail portion, such as a tail 24T.

[0044] Display 14 may have an array of pixels 22. Pixels 22 form an effective area AA of display 14 for displaying images to a user. Ineffective boundary portions of display 14, such as ineffective areas IA along one or more edges of substrate 24, do not contain pixels 22 and do not display images to the user (i.e., ineffective areas IA have no pixels 22).

[0045] Each pixel 22 may have light-emitting diodes such as Figure 2 The organic light-emitting diode 38 and the associated thin-film transistor circuit (e.g., Figure 2 (Pixel circuitry or other suitable pixel circuitry). The array of pixels 22 may be formed by rows and columns of pixel structures (e.g., pixels formed by structures on the display layer such as substrate 24). The array of pixels 22 may have any suitable number of rows and columns (e.g., ten or more, one hundred or more, or one thousand or more). The display 14 may include pixels 22 of different colors. For example, the display 14 may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light. If desired, the display 14 may be used in a configuration that includes pixels of other colors. The use of a pixel arrangement with red, green, and blue pixels is merely exemplary.

[0046] like Figure 3 As shown in the example, the display substrate 24 may have a tail, such as a tail 24T, which has a width narrower than a portion of the effective area AA of the substrate 24. This arrangement facilitates the accommodation of the tail 24T within the housing of the device 10. If desired, the tail 24T may be curved below the remainder of the display 14 when the display 14 is mounted within the electronic device housing.

[0047] The display driver circuitry 20 of the display 14 may be mounted on a printed circuit board coupled to the tail 24T or may be mounted on the tail 24T. Signal paths such as signal path 26 may be coupled to the display driver circuitry 20 to control circuitry 16. Circuitry 20 may include one or more display driver integrated circuits and / or thin-film transistor circuits. During operation, the control circuitry of device 10 (e.g., Figure 1The control circuit 16) can provide information about the image to be displayed on the display 14 to circuits such as the display driver circuit 20. To display the image on the display pixels 22, the display driver circuit 20 can provide corresponding image data to the data line D, and simultaneously send clock signals and other control signals to the supporting display driver circuits such as the gate driver circuit 18. The gate driver circuit 18 can generate gate line signals (sometimes referred to as scan signals, emit enable signals, etc.) or other control signals for the pixels 22. Gate line signals can be transmitted to the pixels 22 using lines such as gate lines G. One or more gate lines may exist for each row of pixels 22. The gate driver circuit 18 may include integrated circuits and / or thin-film transistor circuitry and can be located along the edges of the display 14 (e.g., along the edges of the display 14). Figure 3 Positioned at the left and / or right edge of the display 14 shown or at other locations in the display 14 (e.g., as part of the circuitry 20 on the tail 24T, along the lower edge of the display 14, etc.). Figure 3 The configuration is merely illustrative.

[0048] The display driver circuit 20 provides data signals to multiple corresponding data lines D. Figure 3 In an exemplary arrangement, data line D extends vertically through display 14. Data line D is associated with a corresponding column of pixels 22.

[0049] use Figure 3 In an exemplary configuration, gate lines G (sometimes referred to as scan lines, emission lines, etc.) extend horizontally through the display 14. Each gate line G is associated with a corresponding row of display pixels 22. If desired, multiple horizontal control lines (gate lines G) may be associated with each row of pixels 22. Gate driver circuitry 18 can determine gate signals on gate lines G in the display 14. For example, gate driver circuitry 18 may receive clock signals and other control signals from display driver circuitry 20 and, in response to the received signals, sequentially determine gate signals on gate lines G, starting with gate line signals G in the first row of display pixels 22. When determining each gate line, data from data line D is loaded into the corresponding row of the display pixel. In this way, control circuitry in device 10, such as display driver circuitry 20, can provide signals to pixels 22 to instruct pixels 22 to generate light for displaying a target image on the display 14.

[0050] Thin-film transistor (TFT) circuitry can be used to form the circuitry for pixel 22 and display driver circuitry (if required), such as circuits 18 and / or 20. Typically, any suitable type of TFT technology (e.g., silicon transistors such as polycrystalline silicon TFTs, semiconductor oxide transistors such as indium gallium zinc oxide transistors, etc.) can be used to form the TFTs in display 14.

[0051] Conductive paths (e.g., one or more signal lines, conductive overlays, and other patterned conductive structures) may be provided in the display 14 to route data signal D and power signals such as positive power signal ELVDD and ground power signal ELVSS to pixel 22. Figure 3 As shown, the signal routing paths for receiving signals D, ELVDD, and ELVSS from the tail portion 24T of the display 14 can be used to provide these signals to the pixels 22 in the effective area AA.

[0052] Figure 4 The image shows a cross-sectional side view of a portion of the effective area AA of display 14, illustrating an exemplary configuration that can be used to form pixel 22. Figure 4 As shown, the display 14 may have a substrate, such as substrate 24. Thin-film transistors, capacitors, and other thin-film transistor circuitry 50 (e.g., pixel circuitry, such as...) Figure 2 An exemplary pixel circuit may be formed on substrate 24. Pixel 22 may include an organic light-emitting diode 38. The anode AN of the diode 38 may be formed of a metal layer 58 (sometimes referred to as an anode metal layer). Each diode 38 may have a cathode CD formed of a conductive cathode structure such as a cathode layer 60. Layer 60 may be, for example, a thin metal layer, such as a magnesium silver layer having a thickness of 10nm-18nm, greater than 8nm, less than 25nm, etc. Layer 60 may cover all pixels 22 in the effective area AA of display 14 and may have a portion extending into the ineffective area IA of display 14 (e.g., such that layer 60 is coupled to a ground power path that provides a ground power supply voltage ELVSS to layer 60).

[0053] Each diode 38 has an organic light-emitting layer (sometimes referred to as an emitting material or emitting layer structure), such as emitting layer 56. Emitting layer 56 is an electroluminescent organic layer that emits light 40 in response to an applied current passing through the diode 38. In a color display, emitting layer 56 in the pixel array of the display includes a red emitting layer for emitting red light with red pixels, a green emitting layer for emitting green light with green pixels, and a blue emitting layer for emitting blue light with blue pixels. In addition to the emitting organic layer in each diode 38, each diode 38 may also include additional layers for improving diode performance, such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer. Layers such as these layers may be formed from organic materials (e.g., materials on the upper and lower surfaces of the electroluminescent material in layer 56).

[0054] Layer 52 (sometimes referred to as the pixel definition layer) has an array of openings containing corresponding portions of the emitting material of layer 56. An anode AN is formed at the bottom of each of these openings and overlaps with the emitting layer 56. Therefore, the shape of the diode openings in the pixel definition layer 52 defines the shape of the light-emitting region of the diode 38.

[0055] The pixel definition layer 52 may be formed of a photosensitive material patterned by photolithography (e.g., a dielectric material that can be processed to form photolithographically defined openings, such as photosensitive polyimide, photosensitive polyacrylate, etc.), a material deposited by a shadow mask, or a material patterned onto the substrate 24 in other ways. If desired, the walls of the diode openings in the pixel definition layer may be sloped, such as... Figure 4 The inclined sidewall 64 is shown in the figure.

[0056] The thin-film circuit 50 may include transistors, such as the exemplary transistor 32. Thin-film transistor circuits, such as... Figure 4 An exemplary thin-film transistor 32 may have an effective region (channel region) formed by a patterned semiconductor layer such as layer 70. Layer 70 may be formed of a semiconductor layer such as a polysilicon layer or a semiconductor oxide material (e.g., indium gallium zinc oxide). Source-drain terminals 72 may contact opposite ends of semiconductor layer 70. Gate 76 may be formed of a patterned gate metal layer or other conductive layer and may overlap with semiconductor 70. Gate insulator 78 may be interposed between gate 76 and semiconductor layer 70. Buffer layer such as dielectric layer 84 may be formed on substrate 24 below shield 74. Dielectric layer such as dielectric layer 82 may cover shield 74. Dielectric layer 80 may be formed between gate 76 and source-drain terminals 72. Layers such as layers 84, 82, 78, and 80 may be formed of dielectrics such as silicon oxide, silicon nitride, other inorganic dielectric materials, or other dielectrics. Additional dielectric layers, such as organic planarization layers PLN1 and PLN2, can be included in the structure of thin-film transistors, such as transistor 32, and can help to planarize display 14.

[0057] Display 14 may have multiple conductive material layers embedded in the dielectric layer of display 14, such as metal layers for routing signals through pixels 22. A shielding layer 74 may be formed from a first metal layer (e.g.). A gate layer 76 may be formed from a second metal layer. Source-drain terminals such as terminal 72 and other structures such as signal lines 86 may be formed from portions of a third metal layer such as metal layer 89. Metal layer 89 may be formed on dielectric layer 80 and may be covered by a planarized dielectric layer PLN1. A fourth metal layer such as metal layer 91 may be used to form a diode via portion 88 and signal line 90. In the active region AA, a fifth metal layer such as anode metal layer 58 may form the anode AN of diode 38. The fifth metal layer in each pixel may have a portion, such as via portion 58P coupled to via portion 88, thereby coupling one source-drain terminal of transistor 32 to the anode AN of diode 38. A sixth metal layer (e.g., a cover film) such as cathode metal layer 60 may be used to form the cathode CD of light-emitting diode 38. Anode layer 58 can be inserted between metal layer 91 and cathode layer 60. Layers such as layers 58, 91, 89, 76, and 74 can be embedded within the dielectric layer of display 14 supported on substrate 24. If desired, fewer metal layers can be provided within display 14, or display 14 can have more metal layers. Figure 4 The configuration is merely illustrative.

[0058] Minimizing ohmic losses (sometimes referred to as IR losses) is desirable when distributing power signals to pixels 22 to ensure efficient operation of display 14 and to generate an image with uniform brightness on display 14. Ohmic losses can be minimized by incorporating low-resistance signal paths into display 14.

[0059] Some layers of the display 14, such as the cathode layer 60, may be very thin. The cathode layer 60 may be formed of a metal such as magnesium silver. To ensure that the cathode CD is thin enough to be transparent, the thickness of layer 60 may be about 10 nm to 18 nm (or other suitable thickness). In this type of configuration, the sheet resistance of layer 60 may be relatively high (e.g., about 10 ohms / square). To reduce the sheet resistance of the cathode and thereby allow the ground supply voltage ELVSS to be distributed to the cathode terminals of the diodes 38 in the pixels 22 with minimal IR loss, the display 14 may be provided with supplementary conductive paths. Such paths can help... Figure 4 The display 14 (or a display with other types of thin film stacking) accommodates a display geometry with a geometry that constrains signal distribution (e.g., a display with rounded corners).

[0060] Using an exemplary configuration, a portion of metal layer 91 can be used to form a signal path, such as signal path 90, serving as a supplementary ELVSS path (i.e., a signal path that can operate in parallel with the ELVSS path formed by cathode layer 60), thereby helping to minimize voltage drop and IR loss when operating display 14. Metal layer 91 can be shorted to cathode layer 60 along one or more edges of display 14 (e.g., along the left edge, right edge, bottom edge, along two or more edges, three or more edges, etc.), and can provide a low-resistance path between the source of the signal ELVSS on tail 24T and the corresponding edge of cathode layer 60 (i.e., potentially having a smaller resistance when a signal is distributed to the edge of layer 60 through signal lines in layer 91 than when a signal is distributed to that portion of layer 60 through the thin metal of layer 60 itself). Reducing IR loss when powering layer 60 helps to decrease power loss when driving diode 38 in the active region AA. Using a portion of layer 91 to form a portion of a ground power supply path for distributing ELVSS in display 14 also allows for a reduction in the width of the inactive region IA.

[0061] Figure 5 This is a cross-sectional side view illustrating how the supplementary ELVSS power distribution path (path 90) is shorted to a portion of the inactive region IA of the display 14 of the cathode layer 60 via a portion of the same metal layer (metal layer 58) used to form the anode AN in the active region AA. Figure 5 As shown, the cathode layer 60 can be coupled to the anode metal layer 58 through an opening in the pixel definition layer 52. The anode metal layer 58 can then be shorted to a portion of the metal layer 91 forming the supplementary path 90 through an opening in the planarization layer PLN2. Peripheral signal lines in the invalid region IA, such as signal line 86 (e.g., signal lines associated with gate line signals, signals of the gate driver circuitry 18, and / or other signals of the display 14), can be formed by a portion of the metal layer 89 under the path 90. If desired, the dielectric layer 92 can cover a portion of the signal line 86. The signal line 86 can be formed on the dielectric layer 80 or other dielectric, which can then be formed on the thin-film circuitry and substrate structure 94 (see, substrate 24 and...). Figure 4 The circuit 50 has a dielectric layer and a metal layer. Figure 5 The arrangement allows the ELVSS path 90 to be stacked on top of other signal lines such as signal line 86, which allows the width of the invalid region IA to be minimized.

[0062] Figure 6 This is a top view illustrating how a display 14 with an anode AN can be accommodated via a mesh-like ELVSS path 90 with openings. It can be used as... Figure 5A shorting path of the type shown is used to short the ELVSS path 90 along the edge 96 of the display 14 to the cathode 60, and if necessary, a through-hole in the active area AA can be used to short it to the cathode 60. When the display 14 includes supplementary ground power paths such as... Figure 6 When a mesh-like path (metallic power mesh path) 90 is used, the sheet resistance of the ground path of the ground power signal ELVSS can be reduced (e.g., less than 0.1 ohms / square or other suitable value). If desired, the supplementary ground path 90 of the signal ELVSS can be non-mesh-like (e.g., path 90 may include vertical lines, horizontal lines, L-shaped segments, combinations of horizontal and vertical lines, sparse mesh, dense mesh, combinations of mesh and non-mesh structures, or other suitable shapes). Figure 6 The grid pattern of path 90 is merely illustrative.

[0063] like Figure 7 As shown, the display 14 may have features such as rounded corners that define the amount of space for signal paths. In this case, the metal strip of path 90 may extend along edge 96 and may be shorted to cathode layer 60. At corner 98, there may not be enough space to form the outer strip of metal layer 91. However, due to the presence of the grid-like portion of metal layer 91 (i.e., the grid-like portion of path 90), low-resistance circuitry will be available for ELVSS (e.g., shorting the metal strip associated with path 90 on the lower edge 96 of display 14 to the paths associated with metal strips associated with path 90 on the left and right edges of display 14). If desired, the ELVDD path in display 14 may have grid-like metal traces (e.g., for forming gate metal layer 76, source-drain layer 86, source-drain layer 90, anode metal layer 58, and / or for forming low-resistance grid-like positive power distribution paths such as those having a grid-like structure). Figure 6 The cathode metal layer 60 has a path of the shape shown in the ELVSS trace. For example, a grid-like portion of the mesh, such as path 90 (metal power grid path), can be used as an ELVDD path.

[0064] Figure 8 , Figure 9 and Figure 10 An exemplary pattern is shown forming ELVSS and ELVDD distribution lines from the tail portion 24T to the lower edge 96 of the display 14. Using such an arrangement, such as routing the power lines ELVDD and ELVSS along the center of the tail portion 24T, power wiring can be performed away from dimensional constraints of the display 14, such as corners 98.

[0065] Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 An exemplary arrangement for distributing the positive power supply voltage ELVDD and the ground power supply voltage ELVSS at corner 98 of display 14 is shown. Figure 11 As shown, the lower edge 96 of the display 14 may have a horizontal ELVSS distribution path 100H (e.g., a metal strip extending along the lower edge of the display 14), and the vertical edge 96 of the display 14 may have a vertical ELVSS distribution path (e.g., a metal strip extending along the left and right edges of the display 14), such as path 100V.

[0066] Paths 100H and 100V may be formed by metal layer 89. A gap may exist between paths 100H and 100V at the corner 98 of display 14 (e.g., display 14 and substrate 24 may have rounded corners that limit the space available for power distribution at corner 98). Path 100H can be shorted to each path 100V using L-shaped paths formed by portions of metal layer 91 at corner 98 and other conductive paths. For example, metal layer 91 may have portions such as portion 90-1 shorted to path 100H, connection 90-3 shorting metal layer 91 to metal layer 89 in path 100V, and L-shaped segments 90-2 shorting portion 90-1 to the corresponding connection point 90-3. The positive power supply (ELVDD) path 102H (e.g., a positive power strip path formed by a metal strip extending parallel to one of the metal strips forming the ELVSS path along the edge of the display 14) can be directly shorted to some vertical ELVDD distribution paths, such as vertical line 104-1 (formed in layer 89). Due to the circular shape of the display 14 at corner 98, the connection between other vertical ELVDD distribution paths, such as vertical line 104-2, and path 102H at corner 98 is disconnected, but the L-shaped path portion, such as path 90-5, coupled between the contacts on path 102H (see, for example, contact 90-4) and the contacts 90-6 of the metal layer 91 of the L-shaped path 90-5 shorted to the metal layer 89 of the vertical line 104, can be reconnected. L-shaped paths can be used to assign ELVSS, and L-shaped paths can also be used to assign ELVDD (e.g., in a configuration using a grid-like ELVDD path in display 14, in which metal strips such as paths 100H and 100V are used as part of the ELVDD path, and / or in other configurations).

[0067] Figure 12 and Figure 13 For the segments taken along line A'-A and line B'-B respectively Figure 11 A cross-sectional side view of display 14. (See image) Figure 12 and Figure 13As shown, the planarization layer material (e.g., planarization layer PLN1) can separate the metal layer 91 of segments 90-2 and 90-5 from the metal lines in layer 89.

[0068] exist Figure 14 In the exemplary arrangement, path 100H and path 102H have been formed by two metal layers (89 and 91). Figure 15 , Figure 16 and Figure 17 Cross-sectional side views (corresponding to along) Figure 14 The cross-sections taken from lines A-A', B-B', and C-C' illustrate how the planarization layer PLN1 distinguishes the upper metal layer 91 from the lower metal lines in segments 90-2 and 90-5. If desired, the paths formed by segments 90-2 and / or 90-5 can be implemented using a mesh-like path, such as... Figure 18 As shown.

[0069] The data line distribution path near corner 98 may be space-constrained due to the shape of corner 98. Data line D at corner 98 can be accommodated using a stepped (stepped) shape, such as... Figure 19 The stepped data line portion D' of the data line D is shown. The data line portion D' extends diagonally between the main portion of the substrate 24 and the tail portion 24T of the substrate 24.

[0070] Figure 20 This is part of a display 14 having pixels 22 of multiple colors (see, for example, red pixel 22, green pixel 22G, and blue pixel 22B). In this exemplary configuration of the display 14, each pixel has an anode AN formed by layer 58, a hole injection layer (HIL) formed by a cover film, a first hole transport layer HTL1 (partially common layer), a second hole transport layer HTL2 (cover film shared by all pixels), an emission material EML, a common electron transport layer (ETL), a cathode CD including a cover cathode layer 60, and a cover layer CPL (e.g., a tuning layer of about 70 nm or other suitable thickness).

[0071] Figure 21 For the display 14 to have, for example Figure 20 A top view of display 14 in an exemplary configuration of pixels 22R, 22G, and 22B. Figure 21As shown, the cathode metal layer 60 can overlap with all pixels in the effective area of ​​the display 14. Layer 60 can be formed of a metal such as magnesium silver or other suitable metal and can be thin enough (e.g., 10nm-18nm, greater than 8nm, less than 25nm, etc.) to be transparent to the light 40 emitted by the diode 38 in the pixel. Layer 60 can be used to distribute the ground supply voltage ELVSS to the cathode CD of the diode 38. Due to the relatively small thickness of layer 60, layer 60 may have a relatively high sheet resistance (e.g., about 10 ohms / square). To reduce... Figure 21 The thin-film resistance of the cathode layer in the arrangement can incorporate supplementary cathode paths such as metal lines 128 (e.g., vertical and / or horizontal lines) into the cathode. Lines 128 can be deposited using any suitable metal deposition technique. For example, lines 128 can be deposited using a laser deposition system that ablates the metal of lines 128 from the target and redeposits it onto the exposed surface of the cathode layer 60 in the vacuum chamber.

[0072] Figure 22 A cross-sectional side view of the display 14, taken along line 120 and observed along direction 122. (See attached image.) Figure 22 As shown, the light-emitting diode 38 may have an anode AN and a cathode CD. The cathode CD may be formed from a portion of a cathode metal layer 60. Supplementary lines 128 (e.g., horizontal and / or vertical supplementary lines formed by a grid pattern or other suitable pattern) may be formed on layer 60 and shorted to layer 60, thereby reducing the sheet resistance of the cathode path used to distribute the ground supply voltage ELVSS to the light-emitting diode 28. In an exemplary arrangement, the thickness D1 of layer 60 is about 10 nm to 18 nm (e.g., greater than 8 nm, less than 25 nm, etc.), and the thickness D2 of line 128 is 10 times greater than the thickness D1 (e.g., D2 may be 5 times or greater than D1, or 20 times or less than D1, etc.).

[0073] Figure 23 and Figure 24 This illustrates how a laser deposition system can be used to deposit metal lines 128 onto metal layer 60. (See diagram.) Figure 23As shown, a target such as target 130 may be placed adjacent to the surface of display 14 after the cathode metal layer 60 has been deposited on the surface of display 14. Target 130 may include a transparent substrate (e.g., glass) such as transparent substrate 134, a heat-absorbing material layer such as layer 136, and a highly conductive material layer such as layer 138. Heat-absorbing layer 136 may be formed of a low-reflectivity metal (e.g., molybdenum, tungsten, etc.) or other suitable material that absorbs the laser beam 140 when the laser 132 emits the laser beam 140. Laser beam 140 may include ultraviolet, visible, and / or infrared light, and may have a diameter of 1 micrometer to 1.2 micrometers, greater than 1 micrometer, less than 5 micrometers, or other suitable size. Laser beam 140 may be a pulsed laser beam (e.g., a beam with a pulse width of 1 fs to 100 ps or greater than 100 ps) to facilitate heating of the illuminated portion of heat-absorbing layer 136. Layer 138 may be formed of a highly conductive metal such as aluminum, zinc, magnesium, silver, etc. It can also be used in configurations formed on substrate 134 by more than two layers of metal or by only a single layer of metal.

[0074] like Figure 24 As shown, when laser 132 applies laser 140 to target 130, portions 138' and 136' of layers 138 and 136 are heated, and portions 138' and 136' are ablated or otherwise removed from target 130 and redeposited on adjacent portions of layer 60 in display 14. The deposited metal of portions 138' and 136' forms conductive lines 128 to help reduce the sheet resistance of the conductive structure (i.e., the cathode layer) used to distribute the ground voltage ELVSS to diode 38.

[0075] Figure 25 , Figure 26 , Figure 27 and Figure 28 This is a top view of a display 14 showing an exemplary pattern that can be used to supplement the cathode line 128 (e.g., a laser-deposited metal line). The line 128 may have a uniform vertical or horizontal layout (see, for example, Figure 25 The exemplary vertical line 128 may have an uneven vertical or horizontal layout (see, for example, Figure 25 An exemplary vertical line 128), or may have uniformity ( Figure 27 ) or uneven ( Figure 28 The grid shape. Other patterns or combinations of these patterns may be used to form the lines 128 if desired, and may be combined with the metal layer 91 (e.g., Figure 6 The cathode structure formed by the path 90) is used in combination. Figure 25 , Figure 26 , Figure 27 and Figure 28 The configuration is merely illustrative.

[0076] Figure 29 This illustration shows how a gate driver circuit 18, which may have a circuitry area, drives a horizontal control signal (gate signal) to the horizontal gate line G of the display 14. (See diagram below.) Figure 29 As shown, for example, gate driver circuit 18 may have blocks of gate driver circuits such as gate driver row blocks 150 interconnected using path 158. Each gate driver row block 150 may include circuitry such as output buffers and other output driver circuitry 152, register circuitry 154 (e.g., linked together via path 158 to form a shift register), and path 156 (e.g., interconnected signal lines, power lines, and other lines). Each gate driver row block 150 may provide one or more gate signals to one or more corresponding gate lines in a corresponding row of pixels in the pixel array within the effective area of ​​display 14.

[0077] Figure 30 The diagram illustrates how the gate driver row blocks 150 can be laterally offset (e.g., by providing blocks 150 with varying horizontal offsets DX along a dimension parallel to the horizontal axis along which the gate line G extends) and / or rotated to different angular orientations (e.g., by rotating blocks 150 so that they have angular orientations with varying angular offsets DA) to accommodate the curved edge 98 of the display substrate 24. Gate driver circuitry with laterally varying gate driver row block positions and / or angularly varying gate driver row block orientations may include a unique lateral position and / or angular orientation for each block 150, or a set of two or more different lateral positions and / or angular orientations may be used to enhance the ability of the gate driver circuitry 18 to accommodate curved edges of the display substrate. Control signals (e.g., clock signals and other timing signals) may be provided to the gate driver circuitry using gate driver circuitry control lines such as lines 18L extending along the tail portion 24T of the substrate 24.

[0078] like Figure 31 As shown, the data line D may have an L-shaped data line extension, such as extension 170, to help distribute the data signal to the curved corner 98 of the display substrate 24 without consuming excessive ineffective boundary area. Extension 170 may be formed in the effective area of ​​the display 14. Figure 31As shown, for example, the data line D on the tail 24L may include diagonal data line segments such as segments 164 and 166. Segments 164 and 166 may be formed from the same layer of metal or may be patterned from two or more different metal layers. For example, alternating diagonal segments such as segments 164 and 166 may be formed from corresponding first and second gate metal layers to increase package density. Data line portions 164 and 166 may be coupled to vertical data line portions such as lines D formed in metal layers such as a second source-drain metal layer 91 using vias 162. Pixel 22 may include vias such as the exemplary via 160 to allow data line D formed by metal layer 91 (i.e., Figure 31 The data line formed by the D (metal layer 91) is connected to the internal path (i.e., the source and drain of the transistor in pixel 22) formed by the metal layer 89. The power lines formed by the metal layer 89 can interweave with the data line D (metal layer 91). The L-shaped extension 170 can be formed by the metal layer 91 and can overlap with the corner of the effective area of ​​the display 14 so as not to intrude into the ineffective area along the edge of the substrate of the display 14.

[0079] Figure 32 This illustration shows how display driver circuitry, such as gate driver row block 150, which can have different shapes in different rows, can accommodate curved portions of substrate 24, such as corners 98, at curved edges of the display substrate. Figure 32 As shown, for example, block 150 is a rectangular block of various shapes with different aspect ratios (i.e., the vertical dimension divided by the horizontal dimension of each block 150 may vary). For example, some blocks of 150 may have relatively small aspect ratios (see, for example, a block with a small height A1 and a large width B1), while other blocks 150 may have relatively large aspect ratios (see, for example, a block with a medium height A2 and a medium width B2). Circuits 152, 154, and 158 in block 150 may be arranged to accommodate a custom device package (outline when viewed from above) for each block 150 or each group of blocks 150. Typically, any suitable type of customization of block 150 can be achieved around curved display edges such as corners 98 (e.g., shape customization, lateral offset customization, corner orientation customization, size customization, circuit assembly customization, etc.). Blocks 150 may be customized individually or the block set may be customized to accommodate curved display substrate edges.

[0080] The test circuit can be implemented on the display 14. For example, testing a multiplexer circuit such as... Figure 33Test multiplexer circuit 176 may be provided along the upper or lower edge of display 14. Circuit 176 can be used to route a relatively small number of test signals to a relatively large number of data lines to facilitate pixel testing during manufacturing. During testing, switch SW can be selectively operated to provide test data to data lines D in display 14. For example, switch SW of circuit 176 can be turned on and off to route test data of red data line D(R), such as TESTDATARED, to red data line D(R), test data of green data line D(G), such as TESTDATAGREEN, to green data line D(G), and test data of blue data line D(B), such as TESTDATABLUE, to blue data line D(B). Line D(R) can be used to route data to red pixels, line D(G) can be associated with green pixels, and line D(B) can be coupled to blue pixels of display 14.

[0081] Test data can be provided to the display 14 from a tester coupled to test points on substrate 24 and / or from circuitry attached to substrate 24. An external tester solution can be used when testing is required before the display driver integrated circuit is attached to substrate 24. Test lines can route signals between test points and test circuitry such as circuit 176 (e.g., the three corresponding multiplexer control signals of the red, green, and blue switches in TESTDATARED, TESTDATAGREEN, TESTDATABLUE, and switch SW). Circuit 176 can be controlled by external test circuitry or other controllers so that data lines of different colors can receive test data in a desired pattern. This allows for independent testing of pixels 22 of different colors in display 14. Upon completion of testing, switch SW can be permanently opened so that data lines D in display 14 are not shorted together and can typically be used to route data signals to pixels 22.

[0082] Figure 34 This is an illustration of an exemplary display with a test circuit. Figure 34 As shown, the test multiplexer circuit 176 and test points 174 can be located on opposite edges of the display 14. For example, test points 174 can be located on the tail portion 24L of the substrate 24 at the lower edge of the display 14, and the test multiplexer circuit 176 can be positioned along the upper edge of the display 14. Test signal lines 172 can be used to route test signals between test points 174 on the lower edge of the display 14 to the test multiplexer circuit 176 along the upper edge of the display 14.

[0083] like Figure 35As shown in the exemplary configuration, the test multiplexer circuit 176 can be positioned along the lower edge of the tail portion 24T of the substrate 24 adjacent to the test point 174. After testing, the test multiplexer circuit 176 and the test point 174 can be removed from the tail 24T (e.g., by using along...). Figure 35 The cutting line 180 forms a cut in the tail 24T to cut off the circuit 176 and the test point 174.

[0084] Figure 36 and Figure 37 This illustrates how the multiplexer test circuit 176 is accommodated along the curved portion of display 14. Figure 36 In an exemplary arrangement, circuit 176 is formed within a curved, tapered region of the effective area of ​​display 14 along the curved edge between block 150 of gate driver circuit 18 and data line D. Figure 37 An exemplary configuration is shown in which an area of ​​test multiplexer circuitry 176, such as test multiplexer circuitry block 176B, is interwoven with an area of ​​gate driver circuitry 18, such as gate driver row block 150. By placing block 176B between corresponding pairs of blocks 150, the gate driver circuitry 18 and test multiplexer circuitry 176 can be effectively packaged along the edges of the active areas. This helps to minimize the width of the inactive areas along the edges of the substrate 24 in which the display driver circuitry 18 and test multiplexer circuitry 176 are formed. (See attached diagram) Figure 30 As described in the gate driver circuit 18, the test multiplexer circuit block 176B may have different position-related shapes (e.g., different sizes, aspect ratios, etc.), angular orientations, and / or lateral positions along dimensions parallel to the gate line G, to help enhance the layout of circuitry in inactive areas of the display 14. If desired, other arrangements or other configurations may be used between the areas of the test multiplexer circuit 176 and the areas of the gate driver circuit 18 to help accommodate curved display substrate edges. Figure 37 The configuration is exemplary.

[0085] According to an embodiment, an organic light-emitting diode (OLED) display having an effective area with a pixel array is provided. The OLED display includes: a substrate; a thin-film transistor (TFT) circuit including a dielectric layer on the substrate; a pixel definition layer on the TFT circuit, the pixel definition layer having openings, each opening containing an organic emitting layer of an OLED and each opening being associated with a corresponding pixel in the pixel array; a cathode layer covering the pixel array; and a metal ground power path embedded in the dielectric layer within the effective area, the metal ground power path carrying a ground power supply voltage to the cathode layer.

[0086] According to another embodiment, the metal ground power path is formed by a first portion of the metal layer, and a second portion of the metal layer forms a via structure that contacts the source-drain terminals of the transistor in the thin-film transistor circuit.

[0087] According to another embodiment, the metal grounding power path or positive power path has a grid shape.

[0088] According to another embodiment, the effective area has rounded corners, and the metal grounding power path or positive power path forms a grid with rounded corners.

[0089] According to another embodiment, the metallic grounded power path or positive power path includes an L-shaped portion.

[0090] According to another embodiment, the organic light-emitting diode display includes a first patterned metal layer and a second patterned metal layer embedded in a dielectric layer, the metal ground power path including a metal segment formed by the second patterned metal layer, and the first patterned metal layer including a metal strip carrying a ground power voltage.

[0091] According to another embodiment, the display has edges and a metal strip extends along at least some of the edges.

[0092] According to another embodiment, the first patterned metal layer includes a positive power supply metal strip extending parallel to one of the metal strips carrying the ground power supply voltage.

[0093] According to another embodiment, the metal segment includes L-shaped portions, and at least some of the L-shaped portions cross the positive power metal strip.

[0094] According to another embodiment, the organic light-emitting diode display includes a positive power distribution path extending from a positive power metal strip to a pixel spanning the effective area.

[0095] According to another embodiment, the effective area has rounded corners, and the L-shaped portion is located at the rounded corners.

[0096] According to another embodiment, the source-drain terminals of the transistor in the thin-film transistor circuit are formed by a first metal layer embedded in the dielectric layer, and the metal ground power path is formed by a second metal layer embedded in the dielectric layer.

[0097] According to another embodiment, the anode of the organic light-emitting diode is formed by a third metal layer embedded in a dielectric layer and inserted between a second metal layer and a cathode layer.

[0098] According to another implementation, a portion of the third metal layer is shorted to the cathode layer by the metal grounding power path formed by the second metal layer.

[0099] According to another embodiment, the metal grounding power path includes a laser-deposited metal line.

[0100] According to another embodiment, the organic light-emitting diode layer includes data lines that provide data to pixels, the data lines including stepped portions.

[0101] According to an embodiment, an organic light-emitting diode (OLED) display with a pixel array is provided, the OLED display comprising: a substrate; a thin-film transistor (TFT) circuit layer on the substrate; a pixel definition layer on the TFT circuit layer, the pixel definition layer having openings, each opening containing an organic emitting layer of an OLED and each opening being associated with a corresponding pixel in the pixel array; a cathode layer covering the pixel array and distributing a ground power supply voltage to the OLEDs in each opening; and a patterned metal mesh shorted to the cathode layer and facilitating the distribution of the ground power supply voltage.

[0102] According to another embodiment, the patterned metal mesh includes laser-deposited metal lines located on the cathode layer.

[0103] According to another embodiment, the cathode layer is formed of a first layer of metal, the patterned metal mesh is formed of a second layer of metal, and the anode of the organic light-emitting diode is formed of a third metal layer interposed between the first and second metal layers.

[0104] According to another embodiment, the organic light-emitting diode display includes laser-deposited metal lines located on a cathode layer.

[0105] According to another embodiment, the substrate has rounded corners.

[0106] According to another embodiment, the organic light-emitting diode display includes data lines that distribute data signals to pixels, the data lines including portions having a stepped shape.

[0107] According to an embodiment, an organic light-emitting diode (OLED) display with a pixel array is provided, the OLED display comprising: a substrate; a thin-film transistor (TFT) circuit layer having a dielectric layer on the substrate; a pixel definition layer on the TFT circuit layer having openings, each opening containing an organic emitter layer of an OLED and each opening being associated with a corresponding pixel in the pixels; and a cathode layer covering the pixel array, the cathode layer receiving a ground power supply voltage and distributing the ground power supply voltage to the organic emitter layers in the openings; a first metal layer embedded in the dielectric layer forming source-drain terminals of the TFT circuit layer; a second metal layer embedded in the dielectric layer and patterned to carry the ground power supply voltage to the cathode layer; and a third metal layer having a first portion patterned to form an anode of an OLED and a second portion shorting the second metal layer to the cathode layer.

[0108] According to another embodiment, the substrate has curved edges.

[0109] According to another embodiment, the organic light-emitting diode display includes: data lines for transmitting data to a pixel array; gate lines extending perpendicularly to the data lines; and gate driver circuitry formed by thin-film transistor circuitry, the gate driver circuitry having gate driver row blocks, each of which is coupled to at least one corresponding gate line in the gate lines.

[0110] According to another embodiment, the gate driver row block includes gate driver row blocks with different aspect ratios.

[0111] According to another embodiment, the organic light-emitting diode display includes a test multiplexer circuit comprising test multiplexer circuit blocks between corresponding pairs of gate driver row blocks.

[0112] According to an embodiment, an organic light-emitting diode (OLED) display is provided, comprising: a thin-film transistor (TFT) circuit; an effective region having a pixel array formed by a portion of the TFT circuit and an ineffective region having no pixels and extending along an edge adjacent to the edge of the effective region; a data line providing data to the pixel array; a gate line extending perpendicular to the data line and providing control signals to the pixel array; and a gate driver circuit formed by a portion of the TFT circuit in the ineffective region, the gate driver circuit extending along a curved portion of the edge of the substrate.

[0113] According to another embodiment, the gate driver circuit has a plurality of gate driver row blocks, each of the plurality of gate driver row blocks being coupled to at least one gate line in a corresponding pixel row of the pixel array.

[0114] According to another embodiment, the gate driver row block includes a first gate driver row block and a second gate driver row block with different shapes in the respective first and second rows of the pixel.

[0115] According to another embodiment, the gate driver row block includes a first gate driver row block and a second gate driver row block having different angular orientations in the respective first and second rows of pixels.

[0116] According to another embodiment, the gate driver row block includes gate driver row blocks in different rows of pixels that are offset by different amounts along a dimension extending parallel to the gate line, such that the gate driver row block accommodates a curved portion of the edge of the substrate.

[0117] According to another embodiment, the organic light-emitting diode display includes a test multiplexer circuit coupled to a data line.

[0118] According to another embodiment, the test multiplexer circuit extends at least partially along a curved portion of the edge of the substrate.

[0119] According to another implementation, the test multiplexer circuit includes a region of test circuitry located between rows of gate driver blocks.

[0120] According to another implementation, the data cable includes an L-shaped data cable section.

[0121] According to another embodiment, the data line has a data line portion extending perpendicular to the gate line, and wherein some of the data lines each have a diagonal portion and an L-shaped extension that couples the diagonal portion to a corresponding data line portion extending perpendicular to the gate line.

[0122] According to an embodiment, an organic light-emitting diode (OLED) display is provided, comprising a thin-film transistor (TFT) circuit; an effective region having a pixel array formed by a portion of the TFT circuit and an ineffective region having no pixels and extending along an edge adjacent to the edge of the effective region; a gate driver circuit formed by a portion of the TFT circuit in the ineffective region; control signals provided from the gate driver circuit to the pixel array; and data lines providing data to the pixel array, the data lines having data line portions extending perpendicularly to the gate lines, wherein some of the data lines each have a diagonal portion and an L-shaped extension coupling the diagonal portion to a corresponding data line portion extending perpendicularly to the gate lines.

[0123] According to another embodiment, the edge of the substrate has a curved portion, and the organic light-emitting diode display includes a power line having an L-shaped segment overlapping the effective area.

[0124] According to another embodiment, the gate driver circuit includes a plurality of gate driver rows, each of the plurality of gate driver rows providing at least one of the control signals to a corresponding gate line of a gate line, the gate driver rows including gate driver rows having different shapes along the curved portion.

[0125] According to another embodiment, the gate driver circuit includes a plurality of gate driver rows, each of the plurality of gate driver rows providing at least one of the control signals to a corresponding gate line of a gate line, the gate driver rows including gate driver rows with different angular orientations along the bend.

[0126] The foregoing description is merely illustrative and various modifications can be made to the described implementation scheme. The described implementation scheme can be implemented individually or in any combination.

Claims

1. A display having a pixel array, the pixels defining an effective area and an ineffective area of ​​the display, the display being an organic light-emitting diode (OLED) display and each pixel including an organic light-emitting diode, the display comprising: A rectangular substrate having rounded corners and four edges, wherein the invalid region does not contain pixels along one or more of the edges of the substrate; A gate layer is formed over the substrate and forms the gate of a thin-film transistor circuit; A shielding layer is inserted between the gate layer and the substrate; A first metal layer forms the source-drain terminals of a thin-film transistor circuit and the signal lines in the effective region, wherein the first metal layer further forms: A horizontal ground power path along the lower horizontal edge of the substrate in the invalid region; A first vertical ground power path along the left vertical edge of the substrate in the invalid region; as well as A second vertical ground power path along the right vertical edge of the substrate in the invalid region; A second metal layer carries a ground power supply voltage, wherein the second metal layer includes a first portion shorted to the first metal layer and a second portion forming an L-shaped path, the L-shaped path being in the effective area and coupling the horizontal ground power supply path to the first vertical ground power supply path and the second vertical ground power supply path. A third metal layer having a first portion and a second portion, wherein the first portion of the third metal layer forms the anode of the organic light-emitting diode; A cathode layer overlapping the first metal layer, the second metal layer, and the third metal layer, wherein the second portion of the third metal layer is shorted to the cathode layer, wherein the cathode layer forms the cathode of the organic light-emitting diode and is shorted to the first vertical ground power path and the second vertical ground power path in the invalid region; A first planarization layer, which overlaps with the gate layer and covers the first metal layer, wherein the second metal layer is formed on the first planarization layer; as well as A second planarization layer overlaps with the first planarization layer and is formed on the second metal layer.

2. The display of claim 1, wherein, The pixel overlaps with the shielding layer.

3. The display according to claim 2 further includes an organic emissive material, said organic emissive material being inserted between the anode and the cathode layers.

4. The display of claim 2, wherein, The shielding layer comprises metal.

5. The display of claim 4, wherein, The signal line extends into the invalid region.

6. The display according to claim 1, further comprising: Rounded corners; Tail section; as well as A data cable that extends from the tail portion to the rounded corner portion.

7. The display of claim 6, wherein, The data line extends diagonally between the tail portion and the rounded corner portion.

8. The display of claim 6, wherein, The data cable spreads out in a fan shape at the tail portion.

9. The display according to claim 1, further comprising: A thin-film transistor circuit including a dielectric layer on the substrate; A pixel definition layer on the thin-film transistor circuit, wherein the pixel definition layer has openings, each opening containing an organic emitting layer of an organic light-emitting diode, and each opening being associated with a corresponding pixel in the pixel; A metal power grid path is embedded in the dielectric layer in the effective region, wherein the metal power grid path is disposed within the rounded corner; A gate driver circuit formed from a portion of the thin-film transistor circuit in the invalid region; and Gate lines that provide control signals from the gate driver circuit to the pixel array.

10. An organic light-emitting diode (OLED) display having an effective region and an ineffective region, the effective region having a pixel array, the OLED display comprising: A rectangular substrate having rounded corners, four edges, and a tail portion, wherein the invalid region does not contain pixels along one or more of the edges of the substrate; A thin-film transistor circuit, the thin-film transistor circuit being mounted on the substrate; A first metal layer forms the source-drain terminals of a thin-film transistor circuit and the signal lines in the effective region, wherein the first metal layer further forms: A horizontal ground power path along the lower horizontal edge of the substrate in the invalid region; A first vertical ground power path along the left vertical edge of the substrate in the invalid region; as well as A second vertical ground power path along the right vertical edge of the substrate in the invalid region; A second metal layer carries a ground power supply voltage, wherein the second metal layer includes a first portion shorted to the first metal layer and a second portion forming an L-shaped path, the L-shaped path being in the effective area and coupling the horizontal ground power supply path to the first vertical ground power supply path and the second vertical ground power supply path. A third metal layer having a first portion and a second portion, wherein the first portion of the third metal layer forms the anode of the organic light-emitting diode; A cathode layer overlapping the first metal layer, the second metal layer, and the third metal layer, wherein the second portion of the third metal layer is shorted to the cathode layer, wherein the cathode layer forms the cathode of the organic light-emitting diode and is shorted to the first vertical ground power path and the second vertical ground power path in the invalid region; A first planarization layer, which overlaps with the gate layer and covers the first metal layer, wherein the second metal layer is formed on the first planarization layer; A second planarization layer overlaps with the first planarization layer and is formed on the second metal layer; as well as A data line that transmits data to the pixel array, wherein the data line fans out at the tail portion.

11. The organic light emitting diode display of claim 10, wherein, The data line extends diagonally between the tail portion and the effective area.

12. The organic light-emitting diode display according to claim 10, wherein, The data line has a vertical portion in the tail portion, and wherein the data line has a horizontal portion perpendicular to the vertical portion at the rounded corner of the substrate.

13. The organic light-emitting diode display according to claim 12, further comprising: The gate layer of the thin-film transistor circuit is formed over the substrate. as well as A shielding layer is inserted between the gate layer and the substrate.

14. The organic light-emitting diode display according to claim 13, wherein, The shielding layer comprises metal.

15. The organic light-emitting diode display according to claim 14, wherein, The pixel overlaps with the shielding layer.

16. The organic light-emitting diode display according to claim 15, wherein, The signal line extends from the valid region to the invalid region.

17. An organic light-emitting diode (OLED) display having an effective region and an ineffective region, the effective region having a pixel array, the OLED display comprising: A rectangular substrate having rounded corners, four edges, and a tail portion, wherein the invalid region does not contain pixels along one or more of the edges of the substrate; A thin-film transistor circuit, the thin-film transistor circuit including a gate layer formed over the substrate; A first metal layer forms the source-drain terminals of a thin-film transistor circuit and the signal lines in the effective region, wherein the first metal layer further forms: A horizontal ground power path along the lower horizontal edge of the substrate in the invalid region; A first vertical ground power path along the left vertical edge of the substrate in the invalid region; as well as A second vertical ground power path along the right vertical edge of the substrate in the invalid region; A second metal layer carries a ground power supply voltage, wherein the second metal layer includes a first portion shorted to the first metal layer and a second portion forming an L-shaped path, the L-shaped path being in the effective area and coupling the horizontal ground power supply path to the first vertical ground power supply path and the second vertical ground power supply path. A third metal layer having a first portion and a second portion, wherein the first portion of the third metal layer forms the anode of the organic light-emitting diode; A cathode layer overlapping the first metal layer, the second metal layer, and the third metal layer, wherein the second portion of the third metal layer is shorted to the cathode layer, wherein the cathode layer forms the cathode of the organic light-emitting diode and is shorted to the first vertical ground power path and the second vertical ground power path in the invalid region; a first planarization layer overlapping the gate layer and covering the first metal layer, wherein the second metal layer is formed on the first planarization layer; A second planarization layer overlaps with the first planarization layer and is formed on the second metal layer; A shielding layer is inserted between the gate layer and the substrate; as well as A data line that transmits data to the pixel array, wherein the data line extends diagonally between the tail portion and the rounded corner.

18. The organic light-emitting diode display according to claim 17, wherein, The data cable spreads out in a fan shape at the tail portion.

Images