Display panel and manufacturing method thereof, and display device

Abstract

The embodiment of the present invention provides a display panel and a method for manufacturing the same, and a display device. The display panel includes a display area and an array detection area located on one side of the display area, the array detection area includes a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on a side of the at least one detection pin away from the substrate, and a covering layer arranged on a side of the inorganic layer away from the substrate, wherein the orthographic projection of the inorganic layer on the substrate at least partially overlaps with the orthographic projection of the at least one detection pin on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display is one of the hot topics in the current display research field. Compared with Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed.

[0003] At present, OLED display panels can be manufactured using oxide thin film transistor (TFT) process technology. Generally speaking, the type of thin film transistor in the pixel driving circuit chip of the OLED display panel manufactured using oxide thin film transistor process technology can be P-type or N-type. However, no matter whether P-type or N-type thin film transistor is selected to implement the pixel driving circuit chip, the current of the organic light emitting diode will change with the threshold voltage offset of the driving transistor, causing the OLED display panel to produce Mura phenomenon of uneven display brightness, thereby affecting the brightness uniformity and brightness stability of the OLED display panel.

[0004] During the Array manufacturing process of OLED display panels, the AT (Array Tester) will inspect the Driver Thin Film Transistor (DTFT) and the Pixel in the AA area (Ative Area), and feed back information such as the type, quantity, and location of defects to the production line, thereby monitoring the Array process and continuously improving it to achieve the goal of improving the yield. Summary of the invention

[0005] Embodiments of the present invention provide a display panel and a method for manufacturing the same, and a display device, so as to avoid display problems such as mosaic line defects on the display panel.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, comprising a display area and an array detection area located on one side of the display area, the array detection area comprising a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on a side of the at least one detection pin away from the substrate, and a covering layer arranged on a side of the inorganic layer away from the substrate, the orthographic projection of the inorganic layer on the substrate at least partially overlapping with the orthographic projection of the at least one detection pin on the substrate.

[0007] In an exemplary embodiment, the at least one detection pin is arranged on the substrate to form at least one detection pin row, and an orthographic projection of the at least one detection pin row on the substrate is located in an orthographic projection of the inorganic layer on the substrate.

[0008] In an exemplary embodiment, a first binding area is further included, the first binding area is located between the array detection area and the display area, the first binding area includes at least one binding pin, and the at least one binding pin is connected to the at least one detection pin.

[0009] In an exemplary embodiment, the row of detection pins includes at least a first end, the first end is located at one end of the row of detection pins close to the first binding area, the inorganic layer includes at least a first edge, the first edge is located on a side of the inorganic layer close to the first binding area, and the orthographic projection of the first edge on the substrate is located at the first end of the row of detection pins on a side of the orthographic projection of the substrate close to the first binding area.

[0010] In an exemplary embodiment, a distance between an orthographic projection of the first edge on the substrate and an orthographic projection of the first end of the detection pin row on the substrate is not less than 30 um.

[0011] In an exemplary embodiment, the orthographic projection of the inorganic layer on the substrate does not overlap with the orthographic projection of the first binding area on the substrate, and the distance between the orthographic projection of the first edge of the inorganic layer on the substrate and the orthographic projection of the edge of the first binding area close to the first edge on the substrate is not less than 5um.

[0012] In an exemplary embodiment, a second binding area is further included, and the second binding area is located on a side of the array detection area away from the display area.

[0013] In an exemplary embodiment, the row of detection pins includes at least a second end, the second end is located at one end of the row of detection pins close to the second binding area, the inorganic layer includes at least a second edge, the second edge is located on a side of the inorganic layer close to the second binding area, and the orthographic projection of the second edge on the substrate is located at the second end of the row of detection pins on a side of the orthographic projection of the substrate close to the second binding area.

[0014] In an exemplary embodiment, a distance between an orthographic projection of the second edge on the substrate and an orthographic projection of the second end of the detection pin row on the substrate is 22 um to 27 um.

[0015] In an exemplary embodiment, the orthographic projection of the inorganic layer on the substrate does not overlap with the orthographic projection of the second binding area on the substrate, and the distance between the orthographic projection of the second edge of the inorganic layer on the substrate and the orthographic projection of the edge of the second binding area close to the second edge on the substrate is not less than 5um.

[0016] In an exemplary embodiment, a driving circuit chip is further included. The driving circuit chip includes at least an output terminal and an input terminal. The output terminal of the driving circuit chip is bound to the first binding area, and the input terminal of the driving circuit chip is bound to the second binding area.

[0017] In an exemplary embodiment, an orthographic projection of the driving circuit chip on the substrate at least partially overlaps an orthographic projection of the at least one detection pin row on the substrate.

[0018] In an exemplary embodiment, the at least one row of detection pins includes at least a first side and a second side arranged opposite to each other, and the inorganic layer includes a third edge and a fourth edge arranged opposite to each other, the third edge is located on a side of the inorganic layer close to the first side, and the fourth edge is located on a side of the inorganic layer close to the second side, the orthographic projection of the third edge of the inorganic layer on the substrate is located on the first side and the orthographic projection of the substrate is away from the at least one row of detection pins; and / or the orthographic projection of the fourth edge of the inorganic layer on the substrate is located on the second side and the orthographic projection of the substrate is away from the at least one row of detection pins.

[0019] In an exemplary embodiment, the distance between the third edge of the inorganic layer and the orthographic projection of the first side on the substrate is not less than 100um; and / or, the distance between the fourth edge of the inorganic layer and the orthographic projection of the second side on the substrate is not less than 100um.

[0020] In an exemplary embodiment, it is characterized in that a surface of the inorganic layer away from the substrate is not higher than a surface of the driving circuit chip close to the substrate.

[0021] In a second aspect, an embodiment of the present invention provides a display device, comprising the aforementioned display panel.

[0022] In a third aspect, an embodiment of the present invention provides a method for manufacturing a display panel, comprising:

[0023] forming at least one detection pin on the substrate;

[0024] Perform array detection via the at least one detection pin;

[0025] An inorganic layer is formed on a side of the at least one detection pin away from the substrate; an orthographic projection of the inorganic layer on the substrate at least partially overlaps with an orthographic projection of the at least one detection pin on the substrate;

[0026] A covering layer is formed on a side of the inorganic layer away from the substrate.

[0027] The present invention provides a display panel and a preparation method thereof, and a display device. An inorganic layer is formed on a detection pin, so that during the binding process of a drive circuit chip, the inorganic layer can block a conductive metal ball, thereby preventing the conductive metal ball from contacting the detection pin, causing a short circuit of the detection pin, and resulting in display problems such as mosaic line defects in a display area.

[0028] Of course, it is not necessary to achieve all of the advantages described above at the same time when implementing any product or method of the present invention. Other features and advantages of the present invention will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by practicing the present invention. The purposes and other advantages of the embodiments of the present invention can be achieved and obtained by the structures specifically pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present invention.

[0030] Figure 1 A top view of a display panel according to an embodiment of the present invention Figure 1 ;

[0031] Figure 2 A cross-sectional view of an array detection area in a display panel according to an embodiment of the present invention;

[0032] Figure 3 An enlarged view of an array detection area in a display panel according to an embodiment of the present invention;

[0033] Figure 4 A top view of a display panel according to an embodiment of the present invention Figure 2 . DETAILED DESCRIPTION

[0034] The specific embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other.

[0035] The inspection of display panels mainly includes array inspection (AT) and box process inspection (ET). For COP (Chip on PI, chip encapsulated on polyimide film) products, array inspection can be used to detect whether the array substrate of the display panel has defects. During the inspection, the array inspection area can be used to apply voltage to the pixels, and the pixels can emit electron beams to generate electronic signals, and the defects of the array substrate can be determined by detecting the electronic signals.

[0036] As the pixel density of display panels continues to increase, the density of data routing in display panels continues to increase, and the routing density of array detection is also increasing. Since array detection is an electrical test in the array process segment, it ensures the monitoring of abnormalities and evaluation of improvements in the process segment, which means that the higher the frequency of array detection of data routing, the higher the accuracy of monitoring the performance of the display panel itself. However, the increase in the routing density of array detection further exacerbates the risk of MDL process.

[0037] The inventor of the present application has found through research that the detection pins in the array detection area are covered by a flat layer. Due to the process of preparing the flat layer, the thickness of the flat layer on the detection pins is relatively thin. During the MDL Bonding process, the conductive gold ball will pierce the flat layer covering the detection pins, causing the conductive gold ball to contact the detection pins, causing adjacent detection pins to short-circuit, thereby causing mosaic line defects in the display area. At the same time, due to the influence of the MDL Bonding process, it is not possible to increase the thickness of the flat layer for protection, otherwise it will affect the binding of the drive circuit.

[0038] An embodiment of the present invention provides a display panel, comprising a display area and an array detection area located on one side of the display area, wherein the array detection area comprises a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on a side of the at least one detection pin away from the substrate, and a covering layer arranged on a side of the inorganic layer away from the substrate, wherein the orthographic projection of the inorganic layer on the substrate at least partially overlaps with the orthographic projection of the at least one detection pin on the substrate.

[0039] Figure 1 A top view of a display panel according to an embodiment of the present invention Figure 1 ; Figure 2 FIG. 1 is a cross-sectional view of an array detection area in a display panel according to an embodiment of the present invention. Figure 2 for Figure 1 Take the cross-sectional view in the A-A' direction as an example. Figure 1 and Figure 2As shown, in a direction parallel to the display panel, the display panel of the embodiment of the present invention includes a display area 10 and an array detection area 200 located on one side of the display area 100. In a direction perpendicular to the display panel, the array detection area 200 includes a substrate 1, a structural film layer 6 disposed on one side of the substrate 1, at least one detection pin 2 disposed on a side of the structural film layer 6 away from the substrate 1, an inorganic layer 3 disposed on a side of the at least one detection pin 2 away from the substrate 1, and a covering layer 4 disposed on a side of the inorganic layer 3 away from the substrate 1, wherein the orthographic projection of the inorganic layer 3 on the substrate 1 at least partially overlaps with the orthographic projection of the at least one detection pin 2 on the substrate 1.

[0040] In an exemplary embodiment, the array detection area 200 is used to detect whether the array substrate of the display panel has defects. During the detection, the array detection area 200 is used to apply voltage to the sub-pixel, and the sub-pixel emits an electron beam to generate an electronic signal, and the defects of the array substrate are determined by detecting the electronic signal. The array detection area 200 is electrically connected to the signal lead in the display panel. Specifically, the signal lead of each column of pixels is respectively connected to a detection pin 2 in the array detection area 200. Among them, the signal lead in the display panel can be a data lead in the display area 100.

[0041] The display panel of the embodiment of the present invention forms an inorganic layer 3 on the detection pin 2. During the binding process of the driving circuit chip, the inorganic layer 3 can block the conductive metal ball 7 to prevent the conductive metal ball 7 from contacting the detection pin 2, causing the detection pin 2 to short-circuit, resulting in display problems such as mosaic line defects in the display area 100.

[0042] In an exemplary embodiment, the detection pin 2 can be arranged in the same layer as the data lead in the display area, and can be made of the same material and the same manufacturing process. The detection pin 2 can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., and can be a single-layer structure or a multi-layer composite structure.

[0043] In an exemplary embodiment, the inorganic layer 3 can be disposed in the same layer as the passivation layer in the display area 100, and can be made of the same material and the same preparation process. The inorganic layer 3 can be any one or more of SiOx, SiNx and SiON, and can be a single layer, a multilayer or a composite layer.

[0044] In an exemplary embodiment, the cover layer 4 can be disposed in the same layer as the planar layer in the display area 100 and can be made of the same material and by the same manufacturing process. The cover layer 4 can be made of an organic material, such as a resin.

[0045] In an exemplary embodiment, the structural film layer 6 may adopt a single-layer structure or a multi-layer structure. For example, the structural film layer 6 may include at least one of an interlayer dielectric layer, a first gate insulating layer, and a second gate insulating layer. Among them, the interlayer dielectric layer in the structural film layer 6 may be arranged in the same layer as the interlayer dielectric layer in the display area 100, and may be prepared by the same material and the same preparation method; the first gate insulating layer in the structural film layer 6 may be arranged in the same layer as the first gate insulating layer in the display area 100, and may be prepared by the same material and the same preparation method; the second gate insulating layer in the structural film layer 6 may be arranged in the same layer as the second gate insulating layer in the display area 100, and may be prepared by the same material and the same preparation method.

[0046] Figure 3 FIG. 1 is an enlarged view of the array detection area in the display panel according to an embodiment of the present invention. Figure 3 for Figure 1 In an exemplary embodiment, as shown in FIG. Figure 3 As shown, the material of the detection pin 2 can be a conductor, for example, metal. The detection pin 2 extends along the first direction to form a long strip; at least one detection pin 2 is arranged along the second direction in the array detection area 200 to form at least one detection pin row 5, and the detection pins 2 in a detection pin row 5 are insulated from each other. The first direction intersects with the second direction, for example, the first direction is perpendicular to the second direction.

[0047] In an exemplary embodiment, Figure 1 As shown, the orthographic projection of at least one detection pin row 5 on the substrate 1 is located in the orthographic projection of the inorganic layer 3 on the substrate 1, that is, the inorganic layer 3 covers all detection pins 2, thereby preventing the conductive metal ball from contacting any detection pin 2 to avoid short circuit of the detection pin 2.

[0048] In some exemplary embodiments, the orthographic projection of the inorganic layer 3 on the substrate 1 may overlap with the orthographic projection of a portion of the detection pin row 5 on the substrate 1 , thereby blocking the conductive metal ball from contacting a portion of the detection pins 2 to avoid short circuiting of the portion of the detection pins 2 .

[0049] Figure 4 A top view of a display panel according to an embodiment of the present invention Figure 2 In an exemplary embodiment, if Figure 1 and Figure 4 As shown, in a direction parallel to the display panel, the display panel of the embodiment of the present invention further includes a first binding area 300, a second binding area 400 and a driving circuit chip 500. The driving circuit chip 500 includes at least an output end and an input end. The output end of the driving circuit chip 500 is bound to the first binding area 300, and the input end of the driving circuit chip 500 is bound to the second binding area 400.

[0050] In an exemplary embodiment, Figure 1 As shown, in a direction parallel to the display panel, the display panel of the embodiment of the present invention further includes a flexible circuit board binding area 600, and the flexible circuit board binding area 600 is located on the side of the second binding area 400 away from the display area 100, and the flexible circuit board binding area 600 is connected to the second binding area 400, and the flexible circuit board binding area 600 is used to bind to the flexible circuit board, so that the electrical signal output by the flexible circuit board is input into the second binding area 400 through the flexible circuit board binding area 600.

[0051] In an exemplary embodiment, Figure 1 As shown, the first binding area 300 and the second binding area 400 are respectively located on opposite sides of the array detection area 200. Specifically, the first binding area 300 is located between the array detection area 200 and the display area 100, and the second binding area 400 is located on the side of the array detection area 200 away from the display area 100, and the orthographic projection of the driving circuit chip 500 on the substrate 1 overlaps at least partially with the orthographic projection of at least one detection pin row 5 on the substrate 1. For example, the orthographic projection of the driving circuit chip 500 on the substrate 1 overlaps with the orthographic projections of all detection pin rows 5 on the substrate 1, so that the driving circuit chip 500 covers the detection pin row 5, thereby hiding the detection pin row 5 under the driving circuit chip 500.

[0052] In an exemplary embodiment, Figure 2 As shown, when the driving circuit chip 500 is bound to the first binding area 300 and the second binding area 400, a conductive metal ball 7 is easily generated, and the conductive metal ball 7 will enter the top of the array detection area 200. The inorganic layer 3 in the array detection area 200 can block the conductive metal ball 7, preventing the conductive metal ball 7 from contacting the detection pin 2, causing the detection pin 2 to short-circuit, resulting in display problems such as mosaic line defects in the display area 100.

[0053] In an exemplary embodiment, Figure 1 As shown, the first binding area 300 includes at least one binding pin, the output end of at least one binding pin is connected to the signal lead in the display area, and the input end of at least one binding pin is connected to at least one detection pin 2 in a one-to-one correspondence, so that at least one detection pin 2 can be connected to the signal lead in the display area through the binding pin of the first binding area 300. When a circuit test is required, according to the actual circuit test, the corresponding level signal is input by the detection pin 2, and the level signal is input to the corresponding signal lead in the display area through the binding pin in the first binding area 300, so as to detect the corresponding pixel in the display area.

[0054] In an exemplary embodiment, Figure 3As shown, the detection pin row 5 includes at least a first end 501, which is located at one end of the detection pin row 5 close to the first binding area 300, and the inorganic layer 3 includes at least a first edge 301, which is located at a side of the inorganic layer 3 close to the first binding area 300, and the orthographic projection of the first edge 301 on the substrate 1 is located at the side of the orthographic projection of the first end 501 of the detection pin row 5 on the substrate 1 close to the first binding area 300, so that the inorganic layer 3 completely covers the first end 501 of the detection pin row 5.

[0055] In an exemplary embodiment, the distance between the orthographic projection of the first edge 301 on the substrate 1 and the orthographic projection of the first end 501 of the detection pin row 5 on the substrate 1 is not less than 30 um, so that the conductive metal ball 7 can be blocked more effectively.

[0056] In an exemplary embodiment, the orthographic projection of the inorganic layer 3 on the substrate 1 does not overlap with the orthographic projection of the first binding area 300 on the substrate 1, and the distance between the orthographic projection of the first edge 301 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the edge of the first binding area 300 close to the first edge 301 on the substrate 1 is not less than 5um, thereby forming a certain distance between the inorganic layer 3 and the first binding area 300, thereby preventing the inorganic layer 3 from hindering the binding of the driving circuit chip to the first binding area 300.

[0057] In an exemplary embodiment, Figure 3 As shown, the detection pin row 5 at least includes a second end 502, and the second end 502 is located at one end of the detection pin row 5 close to the second binding area 400. The second end 502 and the first end 501 are respectively located at two opposite ends of the detection pin row 5. The inorganic layer 3 at least includes a second edge 302, and the second edge 302 is located on the side of the inorganic layer 3 close to the second binding area 400, and the orthographic projection of the second edge 302 on the substrate 1 is located on the side of the orthographic projection of the second end 502 of the detection pin row 5 on the substrate 1 close to the second binding area 400, so that the inorganic layer 3 completely covers the second end 502 of the detection pin row 5.

[0058] In an exemplary embodiment, the distance between the orthographic projection of the second edge 302 on the substrate 1 and the orthographic projection of the second end 502 of the detection pin row 5 on the substrate 1 is 22 um to 27 um, so that the conductive metal ball 7 can be blocked more effectively.

[0059] In an exemplary embodiment, the orthographic projection of the inorganic layer 3 on the substrate 1 does not overlap with the orthographic projection of the second binding area 400 on the substrate 1, and the distance between the orthographic projection of the second edge 302 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the edge of the second binding area 400 close to the second edge 302 on the substrate 1 is not less than 5um, thereby forming a certain distance between the inorganic layer 3 and the second binding area 400, thereby preventing the inorganic layer 3 from hindering the binding of the driving circuit chip to the second binding area 400.

[0060] In an exemplary embodiment, Figure 3 As shown, the detection pin row 5 at least includes a first side 503 and a second side 504 that are arranged oppositely, and the first side 503 and the second side 504 are respectively located on both sides of the detection pin row 5 along the second direction. The inorganic layer 3 includes a third edge 303 and a fourth edge 304 that are arranged oppositely, the third edge 303 is located on the side of the inorganic layer 3 close to the first side 503, and the fourth edge 304 is located on the side of the inorganic layer 3 close to the second side 504, and the orthographic projection of the third edge 303 of the inorganic layer 3 on the substrate 1 is located on the side of the first side 503 on the substrate 1 away from the detection pin row 5; and / or, the orthographic projection of the fourth edge 304 of the inorganic layer 3 on the substrate 1 is located on the side of the second side 504 on the substrate 1 away from the detection pin row 5, so that the inorganic layer 3 covers the first side 503 and / or the second side 504 of the detection pin row 5, thereby ensuring that the inorganic layer 3 can effectively block the electric metal ball 7.

[0061] In an exemplary embodiment, the distance between the orthographic projection of the third edge 303 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the first side 503 on the substrate 1 is not less than 100um; and / or, the distance between the orthographic projection of the fourth edge 304 of the inorganic layer 3 on the substrate 1 and the orthographic projection of the second side 504 on the substrate 1 is not less than 100um, so as to ensure that the inorganic layer 3 can effectively block the electric metal ball 7.

[0062] In an exemplary embodiment, the surface of the inorganic layer 3 away from the substrate 1 is not higher than the surface of the driving circuit chip 500 close to the substrate 1 to prevent the inorganic layer 3 from hindering the binding of the driving circuit chip 500. For example, the thickness of the inorganic layer 3 is 2000A to 4000A.

[0063] In an exemplary embodiment, the inorganic layer 3 can be in a variety of shapes, for example, regular or irregular shapes such as rectangles, circles, diamonds, triangles, and polygons, as long as the orthographic projection of the inorganic layer 3 on the substrate 1 at least partially overlaps with the orthographic projection of at least one detection pin 2 on the substrate 1. Specifically, taking the inorganic layer 3 as a rectangle as an example, the length of the inorganic layer 3 is 25905um; the width of the inorganic layer 3 is 400um.

[0064] In an exemplary embodiment, Figure 1 As shown, in a direction parallel to the display panel, the display panel of the embodiment of the present invention further includes a box test area 700 (CT, CellTest). The box test area 700 is located on the side of the first binding area 300 close to the display area 100. The box test area 700 is connected to the signal lead in the display area 100 and is used to perform a box test on the display area 100.

[0065] An embodiment of the present invention further provides a method for manufacturing a display panel, wherein the display panel includes a display area and an array detection area located on one side of the display area. The method for manufacturing the display panel includes:

[0066] forming at least one detection pin on the substrate;

[0067] Perform array detection via the at least one detection pin;

[0068] An inorganic layer is formed on a side of the at least one detection pin away from the substrate; an orthographic projection of the inorganic layer on the substrate at least partially overlaps with an orthographic projection of the at least one detection pin on the substrate;

[0069] A covering layer is formed on a side of the inorganic layer away from the substrate.

[0070] In an exemplary embodiment, the detection pins can be made of the same material and the same manufacturing process as the data leads in the display area. The detection pins can be made of metal materials, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., and can be a single-layer structure or a multi-layer composite structure.

[0071] In an exemplary embodiment, the inorganic layer can be made of the same material and the same manufacturing process as the passivation layer in the display area. The inorganic layer can be any one or more of SiOx, SiNx and SiON, and can be a single layer, a multilayer or a composite layer.

[0072] In an exemplary embodiment, the cover layer can be made of the same material and the same manufacturing process as the planar layer in the display area. The cover layer 4 can be made of an organic material, such as resin.

[0073] The embodiment of the present invention further provides a display device, comprising any of the above-mentioned display panels. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0074] In the description of the embodiments of the present invention, it should be understood that the terms "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0075] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0076] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A display panel, characterized in that: It comprises a display area and an array detection area located on one side of the display area, wherein the array detection area comprises a substrate, at least one detection pin arranged on one side of the substrate, an inorganic layer arranged on a side of the at least one detection pin away from the substrate, and a covering layer arranged on a side of the inorganic layer away from the substrate; The at least one detection pin is arranged on the substrate to form at least one detection pin row, and the orthographic projection of the at least one detection pin row on the substrate is located in the orthographic projection of the inorganic layer on the substrate; the display panel also includes a second binding area, and the second binding area is located on the side of the array detection area away from the display area; the detection pin row includes at least a second end, and the second end is located at an end of the detection pin row close to the second binding area, and the inorganic layer includes at least a second edge, and the second edge is located on a side of the inorganic layer close to the second binding area, and the orthographic projection of the second edge on the substrate is located at the second end of the detection pin row on the side of the orthographic projection of the substrate close to the second binding area.

2. The display panel according to claim 1, characterized in that: It also includes a first binding area, which is located between the array detection area and the display area. The first binding area includes at least one binding pin, and the at least one binding pin is connected to the at least one detection pin.

3. The display panel according to claim 2, characterized in that: The row of detection pins includes at least a first end, which is located at one end of the row of detection pins close to the first binding area. The inorganic layer includes at least a first edge, which is located at a side of the inorganic layer close to the first binding area. The orthographic projection of the first edge on the substrate is located at the first end of the row of detection pins on a side of the orthographic projection of the substrate close to the first binding area.

4. The display panel according to claim 3, characterized in that: The distance between the orthographic projection of the first edge on the substrate and the orthographic projection of the first end of the detection pin row on the substrate is not less than 30 um.

5. The display panel according to claim 3, characterized in that: The orthographic projection of the inorganic layer on the substrate does not overlap with the orthographic projection of the first binding area on the substrate, and the distance between the orthographic projection of the first edge of the inorganic layer on the substrate and the orthographic projection of the edge of the first binding area close to the first edge on the substrate is not less than 5um.

6. The display panel according to claim 1, characterized in that: The distance between the orthographic projection of the second edge on the substrate and the orthographic projection of the second end of the detection pin row on the substrate is 22 um to 27 um.

7. The display panel according to claim 1, characterized in that: The orthographic projection of the inorganic layer on the substrate does not overlap with the orthographic projection of the second binding area on the substrate, and the distance between the orthographic projection of the second edge of the inorganic layer on the substrate and the orthographic projection of the edge of the second binding area close to the second edge on the substrate is not less than 5um.

8. The display panel according to claim 2, characterized in that: It also includes a driving circuit chip, which includes at least an output terminal and an input terminal. The output terminal of the driving circuit chip is bound to the first binding area, and the input terminal of the driving circuit chip is bound to the second binding area.

9. The display panel according to claim 8, characterized in that: The orthographic projection of the driving circuit chip on the substrate at least partially overlaps with the orthographic projection of the at least one detection pin row on the substrate.

10. The display panel according to claim 1, characterized in that: The at least one row of detection pins includes at least a first side and a second side arranged opposite to each other, the inorganic layer includes a third edge and a fourth edge arranged opposite to each other, the third edge is located on the side of the inorganic layer close to the first side, the fourth edge is located on the side of the inorganic layer close to the second side, the orthographic projection of the third edge of the inorganic layer on the substrate is located on the first side and the orthographic projection of the substrate is away from the at least one row of detection pins; and / or the orthographic projection of the fourth edge of the inorganic layer on the substrate is located on the second side and the orthographic projection of the substrate is away from the at least one row of detection pins.

11. The display panel according to claim 10, characterized in that: The distance between the third edge of the inorganic layer and the orthographic projection of the first side on the substrate is not less than 100um; and / or, the distance between the fourth edge of the inorganic layer and the orthographic projection of the second side on the substrate is not less than 100um.

12. The display panel according to claim 8, characterized in that: A surface of the inorganic layer away from the substrate is not higher than a surface of the driving circuit chip close to the substrate.

13. A display device, characterized in that: A display panel comprising any one of claims 1 to 12.

14. A method for preparing a display panel, characterized in that: include: forming at least one detection pin on the substrate; Perform array detection via the at least one detection pin; An inorganic layer is formed on a side of the at least one detection pin away from the substrate; an orthographic projection of the inorganic layer on the substrate at least partially overlaps with an orthographic projection of the at least one detection pin on the substrate; forming a covering layer on a side of the inorganic layer away from the substrate; Among them, the at least one detection pin is arranged on the substrate to form at least one detection pin row, and the at least one detection pin row's orthographic projection on the substrate is located in the orthographic projection of the inorganic layer on the substrate; the display panel also includes a second binding area, and the second binding area is located on the side of the array detection area away from the display area; the detection pin row includes at least a second end, and the second end is located at the end of the detection pin row close to the second binding area, and the inorganic layer includes at least a second edge, and the second edge is located on the side of the inorganic layer close to the second binding area, and the orthographic projection of the second edge on the substrate is located at the second end of the detection pin row on the side of the orthographic projection of the substrate close to the second binding area.

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