Array substrate, detection method thereof and spliced ​​display panel

Abstract

The present invention discloses an array substrate, a detection method thereof and a spliced ​​display panel, wherein pixels in the array substrate include: sub-pixels of at least three colors and a pixel driving chip for driving each sub-pixel to emit light; each sub-pixel includes at least one inorganic light-emitting diode; the display area also includes: a positive electrode signal line connected to the positive electrode of the inorganic light-emitting diode, a data signal line, a scan line and a reference signal line connected to the pixel driving chip; the pixel driving chip is used to write the signal of the data signal line into sub-pixels of different colors in a time-sharing manner under the control of the scan line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a detection method thereof, and a spliced ​​display panel. Background Art

[0002] Compared to organic light-emitting diodes (OLEDs), sub-millimeter or even micrometer-scale light-emitting diodes based on the principle of inorganic light-emitting diodes are self-luminous devices like OLEDs, and like OLEDs, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. In addition, since inorganic light-emitting diodes emit light based on metal semiconductors (rather than organic matter) with more stable properties and lower resistance, they also have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life than OLEDs. Summary of the invention

[0003] The present disclosure provides an array substrate, a detection method thereof, and a spliced ​​display panel. The specific scheme is as follows:

[0004] In a first aspect, an embodiment of the present disclosure provides an array substrate, wherein:

[0005] The array substrate comprises a display area and a frame area; the display area has a plurality of pixels arranged in a matrix, a plurality of scan lines, a plurality of data lines, a plurality of positive signal lines and a plurality of reference signal lines;

[0006] Each of the plurality of pixels comprises: sub-pixels of at least three colors and a pixel driving chip for driving each of the sub-pixels to emit light;

[0007] Each of the sub-pixels includes at least one inorganic light emitting diode;

[0008] The pixel driving chip is connected to the positive electrode of the inorganic light emitting diode in each of the sub-pixels driven by the pixel driving chip, at least one data signal line among the plurality of data lines, at least one scan line among the plurality of scan lines, and at least one reference signal line among the plurality of reference signal lines;

[0009] The pixel driving chip is used to write the signal of the data signal line into sub-pixels of different colors in a time-sharing manner under the control of the scan line, wherein the reference signal line is used to provide a negative signal to the pixel driving chip to form a current path between the inorganic light-emitting diode and the pixel driving chip.

[0010] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0011] The plurality of pixels include N pixel rows arranged along a first direction and M pixel columns arranged along a second direction; N and M are both integers greater than 1;

[0012] The plurality of scan lines extend along the first direction and are arranged along the second direction, the plurality of data signal lines extend along the second direction and are arranged along the first direction, the plurality of positive signal lines extend along the second direction and are arranged along the first direction, and the plurality of reference signal lines extend along the second direction and are arranged along the first direction;

[0013] The first direction and the second direction are different.

[0014] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0015] Each of the pixel rows corresponds to a scan line among the multiple scan lines, and each of the pixel columns corresponds to a data signal line among the multiple data lines, a reference signal line among the multiple reference signal lines, and a positive signal line among the multiple positive signal lines.

[0016] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0017] The pixel comprises: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel;

[0018] Each of the pixel rows corresponds to one scan line among the plurality of scan lines, and each of the pixel columns corresponds to one data signal line among the plurality of data lines, one reference signal line among the plurality of reference signal lines, and two positive signal lines among the plurality of positive signal lines;

[0019] One of the two positive signal lines is connected to the positive electrode of the inorganic light emitting diode in the first color sub-pixel, and the other positive signal line is connected to the positive electrodes of the inorganic light emitting diodes in the third color sub-pixel and the second color sub-pixel.

[0020] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0021] The display area further includes a scan signal routing line connected to each of the plurality of scan lines in a one-to-one correspondence, and the scan signal routing line extends along the second direction.

[0022] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0023] N=M, one side of each pixel column is correspondingly provided with one scanning signal line, and only one scanning signal line is provided between two adjacent pixel columns.

[0024] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0025] N>M, at least one scanning signal wiring is respectively arranged on both sides of at least one pixel column;

[0026] At least one scanning signal wiring is arranged between at least some of two adjacent pixel columns, and the number of scanning signal wirings between two adjacent pixel columns does not exceed two.

[0027] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0028] The scan line is located in the first metal layer; the scan signal line, the data signal line, the reference signal line and the positive signal line are located in the second metal layer.

[0029] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0030] The frame area located at one end of the data signal line includes a bending area, a wiring area and a binding area which are sequentially away from the display area;

[0031] The binding area is provided with at least one first chip and at least one second chip;

[0032] The scanning signal wiring and the data signal wiring are sequentially connected to the first chip through wiring located in the bending area and the wiring area;

[0033] The reference signal line and the positive signal line are bound and connected to the second chip in sequence through the routing lines located in the bending area and the wiring area.

[0034] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0035] The binding area is provided with a plurality of the first chips and a plurality of the second chips;

[0036] The first chip and the second chip are spaced apart and distributed in the binding area.

[0037] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0038] The routing lines in the bending area are all located in the second metal layer.

[0039] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0040] In the wiring area, the wiring connected to the scanning signal wiring and the wiring connected to the data signal line are both located in the first metal layer;

[0041] In the wiring area, the wiring connected to the reference signal line and the wiring connected to the positive signal line are both located in the second metal layer.

[0042] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0043] In the wiring area, the wiring connected to the scanning signal wiring and the wiring connected to the data signal line are both located in the second metal layer;

[0044] In the wiring area, the wiring connected to the reference signal and the wiring connected to the positive signal line are both located in the first metal layer.

[0045] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0046] It is stipulated that the scanning signal line, the data signal line, the reference signal line and the positive signal line are all vertical signal lines;

[0047] The border area further includes: a first signal input area located at a side of the binding area away from the wiring area, and a second signal input area located at an end of the data signal line away from the bending area;

[0048] The first signal input area is provided with first input electrodes corresponding to each of the vertical signal lines one by one, and each of the vertical signal lines in the display area is sequentially connected to the corresponding first input electrode through the wiring located in the bending area and the wiring area;

[0049] The second signal input area is provided with second input electrodes connected to the vertical signal lines in a one-to-one correspondence.

[0050] Optionally, in the array substrate provided in the embodiment of the present disclosure,

[0051] The frame area located at one end of the scan line includes a third signal input area;

[0052] The frame area located at the other end of the scan line includes a fourth signal input area;

[0053] The third signal input area is provided with third input electrodes connected to the scanning lines in a one-to-one correspondence;

[0054] The fourth signal input region is provided with fourth input electrodes connected to the scan lines in a one-to-one correspondence.

[0055] In a second aspect, an embodiment of the present disclosure further provides a spliced ​​display panel, which includes a plurality of any of the above array substrates provided by the embodiments of the present disclosure.

[0056] In a third aspect, an embodiment of the present disclosure further provides a method for detecting any of the above array substrates, wherein the longitudinal signal lines and the scanning lines in the display area are both lines to be detected, and the detection method comprises:

[0057] For each of the lines to be detected, inputting a test signal to one of the input electrodes connected to the line to be detected;

[0058] Detecting whether another input electrode connected to the line to be detected has a signal output, and if not, determining that the line to be detected is broken;

[0059] Detect whether there are signal outputs from input electrodes of other lines to be detected except the line to be detected input with the test signal. If so, determine that a short circuit occurs between the line to be detected input with the test signal and other lines to be detected whose input electrodes have signal outputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0061] Figure 2 A schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0062] Figure 3 A schematic diagram of the structure of a pixel in an array substrate provided by an embodiment of the present disclosure;

[0063] Figure 4 A schematic diagram of the structure of a pixel in another array substrate provided by an embodiment of the present disclosure;

[0064] Figure 5 A schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0065] Figure 6 A schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0066] Figure 7 A schematic diagram of an array layout structure corresponding to a pixel in an array substrate provided in an embodiment of the present disclosure;

[0067] Figure 8 A schematic diagram of another array layout structure corresponding to a pixel in an array substrate provided in an embodiment of the present disclosure;

[0068] Fig. 9 A schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0069] Fig.10 A schematic diagram of a partial cross-sectional structure of a wiring area in an array substrate provided in an embodiment of the present disclosure;

[0070] Fig.11 A schematic diagram of the cross-sectional structure of a scanning signal routing line in an array substrate provided in an embodiment of the present disclosure;

[0071] Fig.12 A schematic diagram of the cross-sectional structure of a reference signal line in an array substrate provided in an embodiment of the present disclosure;

[0072] Fig.13 A schematic structural diagram of another array substrate provided in an embodiment of the present disclosure;

[0073] Fig.14 A flow chart of a method for detecting an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] The inventors found that sub-millimeter LEDs and micro LEDs have problems such as poor brightness uniformity at low current density, so sub-millimeter LEDs and micro LEDs must be driven with high current density to emit light. The current density of micro inorganic LEDs is at least two orders of magnitude greater than that of organic LEDs, so micro inorganic LEDs cannot be driven by pixel circuits formed by thin film transistors like organic LEDs. If pixel circuits formed by thin film transistors are used for driving, the size of the thin film transistors needs to be larger to generate high current density. The large size of thin film transistors will lead to poor uniformity and relatively high power consumption. In addition, the pixel circuits in existing organic LEDs cannot be directly applied to micro inorganic LEDs.

[0075] In view of this, embodiments of the present disclosure provide an array substrate, a detection method thereof, and a spliced ​​display panel.

[0076] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present disclosure are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present disclosure. The drawings of the present disclosure are only used to illustrate the relative position relationship and do not represent the true proportion.

[0077] It should be noted that specific details are described in the following description to facilitate a full understanding of the present disclosure. However, the present disclosure can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present disclosure. Therefore, the present disclosure is not limited to the specific implementation methods disclosed below. The subsequent description of the specification is a preferred implementation method for implementing the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0078] The array substrate, its detection method and the spliced ​​display panel provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0079] An array substrate provided in an embodiment of the present disclosure is as follows: Figure 1 and Figure 2 As shown, the array substrate includes a display area A1 and a frame area A2; the display area A1 has a plurality of pixels 1 arranged in a matrix, a plurality of scan lines Sn, a plurality of data lines Dm, a plurality of positive signal lines Hm and a plurality of reference signal lines Vm;

[0080] like Figure 3 As shown, each pixel 1 among the multiple pixels includes: sub-pixels 01 of at least three colors and a pixel driving chip 02 for driving each sub-pixel 01 to emit light;

[0081] Each sub-pixel 01 includes at least one inorganic light emitting diode;

[0082] The pixel driving chip 2 is connected to the positive electrode of the inorganic light emitting diode in each sub-pixel 01 driven by it, at least one data signal line Dm among the plurality of data lines, at least one scan line Sn among the plurality of scan lines, and at least one reference signal line Vm among the plurality of reference signal lines;

[0083] The pixel driver chip 2 is used to write the signal of the data signal line Dm into sub-pixels 01 of different colors in a time-sharing manner under the control of the scan line Sn, wherein the reference signal line Vm is used to provide a negative signal to the pixel driver chip 2 to form a current path between the pixel driver chip 2 and the inorganic light-emitting diode.

[0084] The array substrate provided in the embodiment of the present disclosure, the pixels include: sub-pixels of at least three colors and a pixel driving chip that drives each sub-pixel to emit light; each sub-pixel includes at least one inorganic light-emitting diode; the display area also includes: a positive signal line connected to the positive electrode of the inorganic light-emitting diode, a data signal line, a scan line and a reference signal line connected to the pixel driving chip; the pixel driving chip is used to write the signal of the data signal line into sub-pixels of different colors in a time-sharing manner under the control of the scan line. That is, in the embodiment of the present disclosure, the pixel driving chip is used to directly drive each pixel to realize display. In addition, since each pixel is directly driven by the pixel driving chip, a large current density can be provided to the micro inorganic light-emitting diode.

[0085] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, the inorganic light emitting diode may be a sub-millimeter light emitting diode (Mini Light Emitting Diode, abbreviated as Mini LED in English) or a micro light emitting diode (Micro Light Emitting Diode, abbreviated as Micro LED in English), which is not limited here.

[0086] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, each sub-pixel includes at least one inorganic light emitting diode, for example, each sub-pixel includes one inorganic light emitting diode, two inorganic light emitting diodes, three inorganic light emitting diodes or a plurality of inorganic light emitting diodes, which are not limited here. The drawings of the specification take the example that each sub-pixel includes two inorganic light emitting diodes for illustration.

[0087] Optionally, in the array substrate provided in the embodiment of the present disclosure, Figure 1 and Figure 3 As shown, the display area A1 includes N pixel rows arranged along a first direction X and M pixel columns arranged along a second direction; N and M are both integers greater than 1;

[0088] A plurality of scan lines Sn extend along the first direction X and are arranged along the second direction Y, a plurality of data signal lines Dm extend along the second direction Y and are arranged along the first direction X, a plurality of positive signal lines Hm extend along the second direction Y and are arranged along the first direction X, and a plurality of reference signal lines Vm extend along the second direction Y and are arranged along the first direction X;

[0089] The first direction X and the second direction Y are different. Optionally, in order to reduce the wiring of the display area, in the array substrate provided in the embodiment of the present disclosure, Figure 1 and Figure 3As shown, each pixel row corresponds to a scan line Sn among multiple scan lines, and each pixel column corresponds to a data signal line Dm among multiple data lines, a reference signal line Vm among multiple reference signal lines, and a positive signal line Hm among multiple positive signal lines.

[0090] In a specific implementation, the difference in current conversion efficiency between the first color inorganic light emitting diode and the second color inorganic light emitting diode is small, while the difference in current conversion efficiency between the first color inorganic light emitting diode and the second color inorganic light emitting diode and the third color inorganic light emitting diode is large. Therefore, the size of the electrical signal that the positive electrode of the first color inorganic light emitting diode needs to receive is different from the size of the electrical signal that the positive electrode of the second color inorganic light emitting diode and the third color inorganic light emitting diode need to receive. When sub-pixels of different colors in the same pixel correspond to the same positive signal line, the signal provided by the positive signal line is required to enable the first color inorganic light emitting diode, the second color inorganic light emitting diode and the third color inorganic light emitting diode to emit maximum brightness, thereby increasing power consumption. Optionally, in the array substrate provided in the embodiment of the present disclosure, such as Figure 2 and Figure 4 As shown, pixel 1 includes: a first color sub-pixel 01 (R), a second color sub-pixel 01 (B) and a third color sub-pixel 01 (G);

[0091] Each pixel row corresponds to a scan line Sn among the plurality of scan lines, and each pixel column corresponds to a data signal line Dm among the plurality of data lines, a reference signal line Vm among the plurality of reference signal lines, and two positive signal lines Hm1 and Hm2 among the plurality of positive signal lines;

[0092] One of the two positive signal lines Hm1 and Hm2 is connected to the positive electrode of the inorganic light emitting diode in the first color sub-pixel 01 (R), and the other positive signal line Hm2 is connected to the positive electrodes of the inorganic light emitting diodes in the third color sub-pixel 01 (G) and the second color sub-pixel 01 (B). In this way, the positive electrodes of the inorganic light emitting diodes in the third color sub-pixel 01 (G) and the second color sub-pixel 01 (B) receive the same signal, while the positive electrode of the inorganic light emitting diode in the first color sub-pixel 01 (R) receives a larger signal amplitude than the signals received by the other two color sub-pixels, thereby preventing the positive electrodes of the three color sub-pixels from receiving the signal of the one that needs the largest signal amplitude among the three color sub-pixels, thereby reducing power consumption.

[0093] In a specific implementation, the first color, the second color and the third color can be one of red, blue and green respectively, for example, the first color is red, the second color is blue, and the third color is green, which is not limited here. Optionally, in the array substrate provided in the embodiment of the present disclosure, Figure 5 As shown, the display area A1 further includes a scanning signal line Cn connected to each scanning line Sn in a one-to-one correspondence with each of the plurality of scanning lines, and the scanning signal line Cn extends along the second direction Y. In this way, a scanning signal can be provided to the corresponding scanning line Sn through the scanning signal line Cn, so that a signal source for providing a scanning signal can be arranged at both ends of the scanning signal line Cn, avoiding the need to arrange a chip for providing a scanning signal at both ends of the scanning line Sn.

[0094] Optionally, in the array substrate provided in the embodiment of the present disclosure, Figure 5 As shown, when the number N of pixel rows and the number M of pixel columns in the display area A1 are the same, that is, N=M;

[0095] One side of each pixel column is correspondingly provided with a scanning signal wiring line Cn, and only one scanning signal wiring line Cn is provided between two adjacent pixel columns.

[0096] Optionally, in the array substrate provided in the embodiment of the present disclosure, Figure 6 As shown, when the number N of pixel rows in the display area A1 is greater than the number M of pixel columns, that is, N>M;

[0097] At least one scanning signal line Cn (for example, Figure 6 The second pixel column in the image has a scanning signal line C1 on its left side and two scanning signal lines C2 and C3 on its right side); at least one scanning signal line Cn is provided between at least some adjacent two pixel columns.

[0098] In a specific implementation, each K adjacent pixel columns are used as a set of repeating units. In each set of repeating units, at least one scanning signal line is provided on both sides of one pixel column, for example, two scanning signal lines are provided on one side and one scanning signal line is provided on the other side; and at most one scanning signal line is provided on both sides of the remaining K-1 pixel columns, for example, one scanning signal line is provided on one side and no scanning signal line is provided on the other side (for example, the pixel column is located at the outermost side of the display panel) or only one scanning signal line is provided (for example, the pixel column is located at the non-outermost side of the display panel). Wherein, K = (min[N,M]) / |NM|.

[0099] Taking N=135 and M=120 as an example, two scanning signal lines need to be set on both sides of 15 pixel columns. To make the 15 pixel columns evenly distributed in the 120 pixel columns, at least one scanning signal line needs to be set on both sides of one pixel column in every 8 pixel columns. Each 8 adjacent pixel columns are a set of repeating units, and there are 15 sets of repeating units in total. In each set of repeating units, at least one scanning signal line is set on both sides of one pixel column, and at most one scanning signal line is set on both sides of the remaining 7 pixel columns.

[0100] Optionally, in the array substrate provided in the embodiment of the present disclosure, Figure 7 and Figure 8 As shown, the scan line Sn is disposed in the first metal layer; the scan signal line Cn, the data signal line Dm, the reference signal line Vm and the positive signal lines Hm1 and Hm2 are disposed in the second metal layer.

[0101] In the embodiments of the present disclosure, two structures are "arranged in the same layer" or "located in the same layer", which may mean that the two structures are formed in the same film forming process, or the two structures are formed in the same patterning process, or they are in the same layer in a stacking relationship, or they are at an equal distance from the substrate.

[0102] Specifically, in the array substrate provided in the embodiment of the present disclosure, the first metal layer may be located on a side of the second metal layer away from the base substrate 100, or the second metal layer may be located on a side of the first metal layer away from the base substrate 100, which is not limited here.

[0103] In specific implementation, Figure 7 and Figure 8 As shown, the pixel driver chip ( Figure 7 and Figure 8 The pixel driver chip (not shown) has a first signal terminal O1, a second signal terminal O2, a third signal terminal O3, a fourth signal terminal O4, a fifth signal terminal O5 and a sixth signal terminal O6. The first signal terminal O1 is connected to the cathode R- of the first color inorganic light emitting diode, the second signal terminal O2 of the pixel driver chip is connected to the cathode G- of the third color inorganic light emitting diode, the third signal terminal O3 of the pixel driver chip is connected to the cathode B- of the second color inorganic light emitting diode, the fourth signal terminal O4 of the pixel driver chip is connected to the scan line Sn, the fifth signal terminal O5 of the pixel driver chip is connected to the data signal line Dn through the via P1, the sixth signal terminal O6 of the pixel driver chip is connected to the reference signal line Vm through the via P2, the anode R+ of the first color inorganic light emitting diode is connected to the anode signal line Hm1 through the via P5, the anode G+ of the third color inorganic light emitting diode is connected to the anode signal line Hm2 through the via P4, and the anode B+ of the second color inorganic light emitting diode is connected to the anode signal line Hm2 through the via P4.

[0104] Figure 7 FIG. 1 is a schematic diagram showing a structure in which a column of pixels is provided with only one scanning signal line Cn on both sides of the row direction. Figure 7 In the example, the scan signal wiring Cn is connected to the scan line Sn through the via P3.

[0105] Figure 8 A column of pixels is provided with scanning signal lines (Cn and Cn) on both sides of the row direction. n+1 ) structural diagram, in Figure 8 In the example, the scanning signal line Cn is connected to the scanning line Sn through the via P3. n+1 With other scan lines ( Figure 8 (not shown) connection.

[0106] Optionally, in the array substrate provided in the embodiment of the present disclosure, Fig. 9 As shown, the frame area A2 located at one end of the data signal line Dm includes a bending area A21, a wiring area A22 and a binding area A23 which are sequentially away from the display area A1;

[0107] The binding area 23 is provided with at least one first chip IC1 and at least one second chip IC2;

[0108] The scanning signal wiring Cn and the data signal wiring Dm are sequentially connected to the first chip IC1 through wiring located in the bending area A21 and the wiring area A22;

[0109] The reference signal line Vm and the positive signal line Hm are bound and connected to the second chip IC2 in sequence through the wiring located in the bending area A21 and the wiring area A22.

[0110] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, the binding area may be provided with only one first chip and one second chip, so as to reduce the number of chips.

[0111] In a specific implementation, when the binding area A23 is only provided with a first chip IC1 and a second chip IC2. Fig.13 As shown, the first chip IC1 is located on the left and the second chip IC2 is located on the right. Then the routing on the left side of the wiring area A22 is closer to the first chip IC1 and farther from the second chip IC2, and the routing on the right side of the wiring area A22 is farther from the first chip IC1 and closer to the second chip IC2. That is, the distances from the left and right routings of the wiring area A22 to the same chip are different, resulting in a large difference in the routing lengths of the wiring area, that is, the loading of the routing is inconsistent, resulting in uneven display.

[0112] In the specific implementation, the scanning signal line provides a digital voltage signal, which is used to control when the signal on the data signal line is written into the pixel driver chip. Therefore, the conduction current on the scanning signal line and the data signal line is small, and it is not sensitive to the IR drop generated by the wiring area wiring. Therefore, in the wiring area, the corresponding wiring width can be set relatively narrow and / or the length can be set relatively long. The signals on the reference signal line and the positive signal line are both fixed voltage signals, but because they are connected in series in the current path of the inorganic light-emitting diode, and the current of the mA level will flow through the current path, the IR drop generated by the wiring in the wiring area will affect the signal of the current path. Therefore, the requirements for the width and length of the wiring in the wiring area are high, and it is necessary to increase the line width and / or shorten the line length as much as possible.

[0113] Therefore, in the array substrate provided in the embodiment of the present disclosure, if Fig. 9 As shown, the binding area A23 is provided with a plurality of first chips IC1 and a plurality of second chips IC2; the first chip IC1 and the second chip IC2 are distributed at intervals in the binding area A23, thereby reducing the length difference of the wiring in the wiring area.

[0114] Furthermore, the first driver chip can be set near the center of the binding area, and the second chip can be set near both sides of the binding area, so that the length of the wiring connected to the first chip can be set relatively long, and the length of the wiring connected to the second chip can be set relatively short.

[0115] Furthermore, in the array substrate provided in the embodiment of the present disclosure, different chips are required to provide signals due to the different functions of the signal lines, but a single chip can also be used to provide different types of signals. In this case, the pin distribution of the chip can also be set with reference to the above rules, for example, the pins that provide signals to the scan signal lines and the data signal lines are set in the middle area of ​​the chip, and the pins that provide signals to the reference signal lines and the positive signal lines are set at both ends of the chip. Optionally, in the array substrate provided in the embodiment of the present disclosure, if Fig. 9 As shown, the traces 03 in the bending area A21 are all located in the second metal layer.

[0116] Optionally, in the array substrate provided in the embodiment of the present disclosure, Fig. 9 and Fig.10 As shown, in the wiring area A22, the wiring 041 connected to the scan signal wiring Cn and the wiring 042 connected to the data signal line Dm are both located in the first metal layer;

[0117] In the wiring area A22, the wiring 051 connected to the reference signal line Vm and the wiring 052 connected to the positive signal line Hm are both located in the second metal layer. Fig.10In the example, the second metal layer is located between the first metal layer and the base substrate 100. Specifically, a planarization layer 101 is further arranged between the first metal layer and the second metal layer, and a protection layer 102 is further arranged above the first metal layer.

[0118] In a specific implementation, the material of the planarization layer can be a non-polar material such as silicon oxide or silicon nitride, or an organic material such as resin, which is not limited here.

[0119] In a specific implementation, the material of the protective layer can be a non-polar material such as silicon oxide or silicon nitride, or an organic material such as resin, which is not limited here.

[0120] Alternatively, optionally, in the array substrate provided by the embodiment of the present disclosure, in the wiring area, the wiring connected to the scan signal wiring and the wiring connected to the data signal wiring are both located in the second metal layer;

[0121] In the wiring area, the wiring connected to the reference signal and the wiring connected to the positive signal line are both located in the first metal layer.

[0122] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, in the wiring area, the wiring is arranged in two metal layers, which can solve the problem of limited space in the wiring area.

[0123] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, after the array substrate manufacturing process is completed, the wiring area and the binding area are bent to the back of the display panel through the bending area, thereby reducing the frame of the display panel.

[0124] In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, if Fig. 9 As shown, it is stipulated that the scanning signal line Cn, the data signal line Dm, the reference signal line Vm and the positive signal line Hm are all vertical signal lines;

[0125] The frame area A2 further includes: a first signal input area A24 located at a side of the binding area A23 away from the wiring area A22, and a second signal input area A25 located at an end of the data signal line Dm away from the bending area A21;

[0126] The first signal input area A24 is provided with first input electrodes Tp1 corresponding to each longitudinal signal line, and each longitudinal signal line in the display area A1 is sequentially connected to the corresponding first input electrode Tp1 through the wiring located in the bending area A21 and the wiring area A22;

[0127] The second signal input area A25 is provided with second input electrodes Tp2 connected to the vertical signal lines in a one-to-one correspondence.

[0128] For example, in wiring area A22, wiring 041 connected to scanning signal wiring Cn and wiring 042 connected to data signal line Dm are both located in the first metal layer; in wiring area A22, wiring 051 connected to reference signal line Vm and wiring 052 connected to positive signal line Hm are both located in the second metal layer.

[0129] Specifically, Fig.11 As shown, the scanning signal line Cn located in the second metal layer is sequentially bound to the first chip IC1 in the binding area A23 through the line 03 located in the bending area A21 and located in the second metal layer, the line 041 located in the wiring area A22 and located in the first metal layer, and connected to the first input electrode Tp1 in the first signal input area A24 through the transparent conductive layer 103. Among them, the film layer relationship of the data signal line is the same as that of the scanning signal line, which will not be repeated here.

[0130] Specifically, Fig.12 As shown, the reference signal line Vm located in the second metal layer is sequentially connected to the second chip IC2 in the binding area A23 through the first metal layer and the transparent conductive layer 103 through the routing line 03 located in the bending area A21 and located in the second metal layer, and the routing line 051 located in the wiring area A22 and located in the second metal layer, and is connected to the first input electrode Tp1 in the first signal input area A24. The film layer relationship of the positive signal line is the same as that of the reference signal line, which will not be repeated here.

[0131] Optionally, in the array substrate provided in the embodiment of the present disclosure, Fig. 9 As shown, the border area A2 located at one end of the scanning line Sn includes a third signal input area A26; the border area located at the other end of the scanning line Sn includes a fourth signal input area A27; the third signal input area A26 is provided with a third input electrode Tp3 connected to each scanning line Sn in a one-to-one correspondence; the fourth signal input area A27 is provided with a fourth input electrode Tp4 connected to each scanning line Sn in a one-to-one correspondence.

[0132] In specific implementation, by inputting signals to the input electrodes and detecting signals from other input electrodes, it is possible to detect whether each vertical signal line on the array substrate is normal. After the detection is completed and confirmed to be a good product, the signal input area can be cut off without affecting the subsequent use of the panel.

[0133] Based on the same inventive concept, the embodiment of the present disclosure further provides a detection method for any array substrate provided by the embodiment of the present disclosure, which stipulates that the vertical signal lines and scanning lines in the display area are all lines to be detected, such as Fig.14 As shown, the detection method includes:

[0134] S101 . For each line to be detected, input a test signal to one of the input electrodes connected to the line to be detected.

[0135] S102, detecting whether another input electrode connected to the line to be detected has a signal output, and if not, determining that the line to be detected is broken.

[0136] S103, detecting whether the input electrodes of other lines to be detected except the line to be detected with the test signal input have signal outputs, and if so, determining that a short circuit occurs between the line to be detected with the test signal input and other lines to be detected with signal outputs from the input electrodes.

[0137] The detection method provided by the embodiment of the present disclosure can detect whether a short circuit or a break occurs in the line to be detected by inputting a signal to an input electrode and detecting signals of other input electrodes. The detection method is simple. Moreover, the cost can be reduced by applying the detection method to the preparation process of the array substrate.

[0138] In specific implementation, in the detection method provided in the embodiment of the present disclosure, the order of step S102 and step S103 is not limited. Step S102 may be performed first, and then step S103; or step S103 may be performed first, and then step S102, which is not limited here.

[0139] The application of the detection method of the array substrate provided by the embodiment of the present disclosure is described below through examples.

[0140] In the specific implementation, taking the second metal layer located below the first metal layer as an example, in production, the second metal layer is first prepared, and the scanning signal line, the data signal line, the reference signal line and the positive signal line are formed in the second metal layer; for the reference signal line and the positive signal line, the first input electrode of the first signal input area and the second input electrode of the second signal input area can be used in cooperation with each other to detect whether the reference signal line and the positive signal line are normal, for example: input a test signal to the first input electrode of the reference signal line, detect whether there is a signal output on the second input electrode connected to the reference signal line, if yes, it is determined that the reference signal line is normal, if not, it is determined that the reference signal line is broken, and the reference signal line is repaired. Detect whether there is a signal output on the first input electrode or the second input electrode connected to other signal lines except the reference signal line, if not, it is determined that there is no short circuit between the reference signal line and other signal lines, if yes, it is determined that the reference signal line and other signal lines are short-circuited, and the short-circuited signal line is repaired. When all reference signal lines and positive signal lines are normal, the planarization layer is deposited and vias are formed in the planarization layer. At this time, the reference signal lines and positive signal lines are repeatedly tested. When the test results are normal, the second metal layer is deposited, a scan line is formed in the second metal layer, and the signal connection between the data signal line and the scan signal line and the first output electrode is completed. At this time, the first input electrode of the first signal input area, the second input electrode of the second signal input area, the third input electrode of the third signal input area, and the fourth input electrode of the fourth signal input area can be used in conjunction with each other to detect whether all signal lines on the array substrate are normal. If a short circuit or open circuit occurs, it is repaired until all signal lines are normal and then the subsequent process is continued. This avoids the subsequent scrapping of the array substrate due to abnormal signal lines, thereby reducing the production cost.

[0141] Based on the same inventive concept, the embodiment of the present disclosure further provides a spliced ​​display panel, including multiple array substrates provided by the embodiment of the present disclosure. Since the principle of solving the problem by the spliced ​​display panel is similar to that of the aforementioned array substrate, the implementation of the spliced ​​display panel can refer to the implementation of the aforementioned array substrate, and the repeated parts will not be repeated.

[0142] In a specific implementation, in the spliced ​​display panel provided in the embodiment of the present disclosure, the second signal input area, the third signal input area and the fourth signal input area in the array substrate can be cut after the array substrate process is completed without affecting the subsequent splicing process; the wiring area and the binding area are bent to the back of the display panel through the bending area, thereby reducing the width of the display panel frame.

[0143] In specific implementation, the spliced ​​display panel provided by the embodiment of the present disclosure has multiple array substrates that bend the wiring area and the binding area to the back of the display panel through the bending area. It has the advantages of a small number of composition processes, no need for back-side processes, low process complexity, and a small frame, and has high technical value.

[0144] The above-mentioned array substrate, its detection method and spliced ​​display panel provided by the embodiment of the present disclosure, the pixels in the array substrate include: sub-pixels of at least three colors and a pixel driving chip that drives each sub-pixel to emit light; each sub-pixel includes at least one inorganic light-emitting diode; the display area also includes: a positive signal line connected to the positive electrode of the inorganic light-emitting diode, a data signal line, a scan line and a reference signal line connected to the pixel driving chip; the pixel driving chip is used to write the signal of the data signal line into sub-pixels of different colors in a time-sharing manner under the control of the scan line. That is, in the embodiment of the present disclosure, the pixel driving chip is used to directly drive each pixel to realize display. In addition, since each pixel is directly driven by the pixel driving chip, a large current density can be provided to the micro inorganic light-emitting diode.

[0145] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein: The array substrate includes a display area and a frame area; the display area includes a plurality of scan lines, a plurality of data lines, a plurality of positive signal lines, a plurality of reference signal lines, and a plurality of pixels arranged in an array; the plurality of pixels include N pixel rows arranged along a first direction and M pixel columns arranged along a second direction; N and M are both integers greater than 1; The plurality of scan lines extend along the first direction and are arranged along the second direction, the plurality of data lines extend along the second direction and are arranged along the first direction, the plurality of positive signal lines extend along the second direction and are arranged along the first direction, and the plurality of reference signal lines extend along the second direction and are arranged along the first direction; The first direction and the second direction are different; The pixel comprises: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel and a pixel driving chip driving the first color sub-pixel, the second color sub-pixel and the third color sub-pixel to emit light; Each of the pixel rows corresponds to one scan line among the plurality of scan lines, and each of the pixel columns corresponds to one data line among the plurality of data lines, one reference signal line among the plurality of reference signal lines, and two positive signal lines among the plurality of positive signal lines; Each of the sub-pixels includes at least one inorganic light-emitting diode; the first positive signal line of the two positive signal lines is connected to the positive electrode of the inorganic light-emitting diode in the first color sub-pixel, and the second positive signal line is connected to the positive electrodes of the inorganic light-emitting diodes in the third color sub-pixel and the second color sub-pixel; the signal amplitude of the first positive signal line is greater than the signal amplitude of the second positive signal line; The pixel driving chip is connected to the cathode of the inorganic light emitting diode in each of the sub-pixels driven by the pixel driving chip, at least one data line among the plurality of data lines, at least one scan line among the plurality of scan lines, and at least one reference signal line among the plurality of reference signal lines; The pixel driving chip is used to write the signal of the data line into sub-pixels of different colors in a time-sharing manner under the control of the scan line, wherein the reference signal line is used to provide a negative signal to the pixel driving chip to form a current loop between the inorganic light-emitting diode and the pixel driving chip.

2. The array substrate according to claim 1, wherein: The display area further includes a scan signal routing line connected to each of the plurality of scan lines in a one-to-one correspondence, and the scan signal routing line extends along the second direction.

3. The array substrate according to claim 2, wherein: N=M, one side of each pixel column is correspondingly provided with one scanning signal line, and only one scanning signal line is provided between two adjacent pixel columns.

4. The array substrate according to claim 2, wherein: N>M, at least one scanning signal wiring is respectively arranged on both sides of at least one pixel column; At least one scanning signal wiring is arranged between at least some of two adjacent pixel columns, and the number of scanning signal wirings between two adjacent pixel columns does not exceed two.

5. The array substrate according to claim 2, wherein: The scan line is located in the first metal layer; the scan signal line, the data line, the reference signal line and the positive signal line are located in the second metal layer.

6. The array substrate according to claim 5, wherein: The frame area located at one end of the data line includes a bending area, a wiring area and a binding area which are sequentially away from the display area; The binding area is provided with at least one first chip and at least one second chip; The scanning signal wiring and the data wiring are sequentially connected to the first chip through wiring located in the bending area and the wiring area; The reference signal line and the positive signal line are bound and connected to the second chip in sequence through the routing lines located in the bending area and the wiring area.

7. The array substrate according to claim 6, wherein: The binding area is provided with a plurality of the first chips and a plurality of the second chips; The first chip and the second chip are spaced apart and distributed in the binding area.

8. The array substrate according to claim 6, wherein: The routing lines in the bending area are all located in the second metal layer.

9. The array substrate according to claim 6, wherein: In the wiring area, the wiring connected to the scanning signal wiring and the wiring connected to the data line are both located in the first metal layer; In the wiring area, the wiring connected to the reference signal line and the wiring connected to the positive signal line are both located in the second metal layer.

10. The array substrate according to claim 6, wherein: In the wiring area, the wiring connected to the scanning signal wiring and the wiring connected to the data line are both located in the second metal layer; In the wiring area, the wiring connected to the reference signal and the wiring connected to the positive signal line are both located in the first metal layer.

11. The array substrate according to claim 6, wherein: It is stipulated that the scanning signal line, the data line, the reference signal line and the positive signal line are all vertical signal lines; The border area further includes: a first signal input area located at a side of the binding area away from the wiring area, and a second signal input area located at an end of the data line away from the bending area; The first signal input area is provided with first input electrodes corresponding to each of the vertical signal lines one by one, and each of the vertical signal lines in the display area is sequentially connected to the corresponding first input electrode through the wiring located in the bending area and the wiring area; The second signal input area is provided with second input electrodes connected to the vertical signal lines in a one-to-one correspondence.

12. The array substrate according to claim 11, wherein: The frame area located at one end of the scan line includes a third signal input area; The frame area located at the other end of the scan line includes a fourth signal input area; The third signal input area is provided with third input electrodes connected to the scanning lines in a one-to-one correspondence; The fourth signal input region is provided with fourth input electrodes connected to the scan lines in a one-to-one correspondence.

13. A spliced ​​display panel, wherein: It comprises a plurality of array substrates as described in any one of claims 1 to 12.

14. A method for detecting an array substrate according to claim 11 or 12, wherein: It is stipulated that the vertical signal lines and the scanning lines in the display area are both lines to be detected, and the detection method includes: For each of the lines to be detected, inputting a test signal to one of the input electrodes connected to the line to be detected; Detecting whether another input electrode connected to the line to be detected has a signal output, and if not, determining that the line to be detected is broken; Detect whether there are signal outputs from input electrodes of other lines to be detected except the line to be detected input with the test signal. If so, determine that a short circuit occurs between the line to be detected input with the test signal and other lines to be detected whose input electrodes have signal outputs.

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