Electronic components, circuit board assemblies, and methods for manufacturing electronic components

Abstract

An electronic component includes a component body. The component body has a dielectric and internal electrodes. The electronic component also includes at least one external electrode. Each external electrode includes a base layer, a plating layer, and a capping layer. The base layer is formed on a plurality of surfaces of the component body. The base layer is connected to the internal electrodes and comprises metal. The plating layer is formed on a mounting surface of the base layer and on a side of the base layer connected to the internal electrodes. The capping layer is formed on at least a portion of the surface of the base layer opposite to the mounting surface of the base layer. The capping layer is less wetted by solder compared to the plating layer.

Description

Technical Field

[0001] This invention relates to electronic components, circuit board assemblies, and methods for manufacturing electronic components. Background Technology

[0002] To reduce the mounting area of ​​electronic components and to minimize the size of electronic devices, external electrodes are typically formed on the component body, which contains internal electrodes. These external electrodes are then soldered to a circuit board, allowing the electronic components to be mounted on the board.

[0003] External electrodes can be formed not only on the mounting surface of the component body, but also on the sides and top surface of the component body. In this configuration, wet solder moves upwards along the sides of the external electrodes to the top surface of the external electrodes, increasing the height of the circuit board.

[0004] To prevent wet solder from moving upward along the side of the terminal electrode (solder wetting) and reaching the upper surface of the terminal electrode, JP-2014-53599A discloses a structure in which the side portions of the first and second terminal electrodes formed on the side of the electronic component are covered by an oxide film. Summary of the Invention

[0005] However, if the side portions of the terminal electrodes are covered with an oxide film and excessive solder is provided, the amount of solder that diffuses from the mounting surface into unwanted directions can increase, potentially hindering the high-density mounting of multiple electronic components. Furthermore, in a typical configuration that allows solder to wet the entire surface of the external electrode, the solder can wet upwards along the side of the external electrode and reach its upper surface. As a result, the final height of the circuit board with multiple components mounted on it may be greater than originally designed.

[0006] Therefore, an object of the present invention is to provide an electronic component that can regulate the amount of solder diffusing from the mounting surface while preventing solder from wetting the surface opposite to the mounting surface. Another object of the present invention is to provide a method for manufacturing such an electronic component. Yet another object of the present invention is to provide a circuit board apparatus that can regulate the amount of solder diffusing from the mounting surface while preventing solder from wetting the surface opposite to the mounting surface.

[0007] According to a first aspect of the invention, an electronic component is provided, comprising a component body and at least one external electrode. The component body includes a dielectric body and an internal electrode. Each external electrode includes a base layer, a plating layer, and a capping layer. The base layer is formed on a plurality of surfaces of the component body, connected to the internal electrode, and comprising metal. The plating layer is formed on a mounting surface of the base layer and on a side surface of the base layer to which the internal electrode is connected. The capping layer is formed on at least a portion of the surface of the base layer opposite to the mounting surface. The capping layer is less wetted by solder compared to the plating layer.

[0008] A substrate layer can be formed on the side of the component body and extend from the side to the front and rear surfaces, as well as the top and bottom surfaces of the component body. A mounting surface can be located below the bottom surface of the component body. A cover layer can be disposed on the top surface of the substrate layer. Plating layers can be formed on the front and rear surfaces of the substrate layer.

[0009] The capping layer may include an oxide film of the metal in the base layer.

[0010] The base layer may include a first co-material that coexists with the metal. The cover layer may include a second co-material.

[0011] The first common material included in the base layer and the second common material included in the cover layer can have the same composition.

[0012] The first comaterial can be a ceramic oxide that includes a dielectric. The second comaterial can also be a ceramic oxide that includes a dielectric.

[0013] The coating layer can be a resist film including resin.

[0014] The base layer may include glass components.

[0015] The capping layer may include a glass phase having the same composition as the glass components included in the base layer.

[0016] The metal in the base layer may be a metal or alloy containing at least one selected from Cu, Fe, Zn, Al and Ni.

[0017] The coating may include a Ni coating and a Sn coating formed on the Ni coating.

[0018] The cover layer can be set in a strip pattern on the surface of the base layer opposite to the mounting surface of the base layer, such that the strip pattern is continuous along the edges of the base layer that contact the side, front and rear surfaces of the base layer.

[0019] The base layer may have a chamfered surface on its edges. At least a portion of the end of the cover layer may extend along the chamfered surface of the base layer.

[0020] The angle formed by the tangent of the face opposite to the mounting surface of the external electrode and the chamfered surface at the position where the end of the cover layer contacts the side of the base layer can be greater than 45 degrees.

[0021] The internal electrode may include at least one first internal electrode layer and at least one second internal electrode layer. The component body may include a laminate, wherein the first internal electrode layer and the second internal electrode layer are stacked alternately, with a dielectric (layer) interposed therebetween. The at least one external electrode may include a first external electrode and a second external electrode disposed on opposite sides of the laminate. The first internal electrode layer may be connected to the first external electrode. The second internal electrode layer may be connected to the second external electrode.

[0022] According to a second aspect of the invention, a circuit board apparatus is provided, comprising a circuit board and any of the aforementioned electronic components mounted on the circuit board. The electronic components are connected to the circuit board via a solder layer adhered to a mounting surface of a plating layer, the solder layer wetting the sides of external electrodes.

[0023] According to a third aspect of the present invention, a method for manufacturing an electronic component is provided. The method includes: forming a component body comprising a dielectric and internal electrodes; applying an electrode material comprising a metal to a side surface of the component body and a surrounding surface of the side surface of the component body; sintering the electrode material to form a metal-containing base layer on the side surface of the component body and the surrounding surface of the side surface of the component body; forming a cover layer covering the surface of the base layer; removing the cover layer from a mounting surface and a side surface of the base layer while leaving the cover layer on a surface opposite to the mounting surface of the base layer; and forming a plating layer on the mounting surface and a side surface of the base layer. The cover layer has less solder wettability than the plating layer.

[0024] The step of forming a capping layer over the surface of the substrate may include oxidizing a metal to form a metal oxide film on the surface of the substrate.

[0025] Electrode materials may include glass components.

[0026] The step of forming a capping layer on the surface of the substrate layer may include: surface-forming a glass phase composed of glass components on the surface of the substrate layer when sintering the electrode material.

[0027] The steps of removing the cover layer from the mounting surface and sides of the base layer may include sandblasting the cover layer present on the mounting surface of the base layer.

[0028] According to one aspect of the invention, it is possible to prevent solder from wetting the surface opposite to the mounting surface while adjusting the amount of solder that diffuses out of the mounting surface. Attached Figure Description

[0029] Figure 1 This is a perspective view showing the construction of a multilayer ceramic capacitor according to a first embodiment of the present invention.

[0030] Figure 2 yes Figure 1The image shows a cross-sectional view of the multilayer ceramic capacitor taken longitudinally.

[0031] Figure 3 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to a second embodiment of the present invention.

[0032] Figure 4A This is a cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0033] Figure 4B This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0034] Figure 4C This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0035] Figure 4D This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0036] Figure 4E This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0037] Figure 4F This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0038] Figure 4G This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0039] Figure 4H This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0040] Figure 4I This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0041] Figure 4J This is another cross-sectional view used to describe a method for manufacturing a multilayer ceramic capacitor according to the second embodiment.

[0042] Figure 5A It is shown Figure 4I A floor plan showing an example of the processing.

[0043] Figure 5B This shows the section cut along the longitudinal direction. Figure 5A A cross-sectional view of the process.

[0044] Figure 6AThis is a cross-sectional view showing an exemplary construction of the end of the capping layer of a multilayer ceramic capacitor according to a third embodiment of the present invention.

[0045] Figure 6B This is a cross-sectional view showing an exemplary construction of the interface between the ends of the base layer and the capping layer of a multilayer ceramic capacitor according to a third embodiment.

[0046] Figure 7A This is a cross-sectional view showing the construction of a circuit board device according to a fourth embodiment of the present invention, wherein a multilayer ceramic capacitor is mounted on the circuit board.

[0047] Figure 7B This is a cross-sectional view showing the construction of a circuit board on which a multilayer ceramic capacitor according to the first comparative example is mounted.

[0048] Figure 7C This is a cross-sectional view showing the construction of a circuit board on which a multilayer ceramic capacitor according to the second comparative example is mounted.

[0049] Figure 8 This is a plan view showing the construction of a multilayer ceramic capacitor according to a fifth embodiment of the present invention.

[0050] Figure 9 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to a sixth embodiment of the present invention.

[0051] Figure 10 This is a perspective view showing the structure of an electronic component according to a seventh embodiment of the present invention.

[0052] Figure 11 This is a perspective view showing the structure of an electronic component according to an eighth embodiment of the present invention. Detailed Implementation

[0053] In the following, some embodiments of the invention will be described in detail with reference to the accompanying drawings. It should be noted that the following embodiments are not intended to limit the invention, and not all combinations of features described in the embodiments are necessary in the construction of the invention. The construction of the embodiments can be appropriately modified or changed according to the specifications of the device to which the invention is applied and various conditions (conditions and / or environment of using the device). The scope of the invention is defined by the claims and is not limited to the following embodiments. Furthermore, for ease of understanding of each feature and structure, the features and structures shown in the accompanying drawings mentioned in the following description may differ from actual features and structures in proportion, shape, etc.

[0054] First Embodiment

[0055] Figure 1 This is a perspective view showing the structure of a multilayer ceramic capacitor 1A according to a first embodiment of the present invention. Figure 2 yes Figure 1 The cross-sectional view of the multilayer ceramic capacitor 1A shown is taken along the longitudinal direction.

[0056] refer to Figure 1 and Figure 2 The multilayer ceramic capacitor 1A includes a component body (component assembly) 2 and two external electrodes (external electrodes) 6A and 6B. The component body 2 includes a laminate 2A, a lower cover layer 5A, and an upper cover layer 5B. The laminate 2A includes internal electrode layers 3A and 3B and a dielectric layer 4.

[0057] The lower cover layer 5A is positioned below the stack 2A, while the upper cover layer 5B is positioned on top of the stack 2A. The inner electrode layers 3A and 3B are stacked alternately, with dielectric layers 4 interposed between them. The component body 2 may have a generally cuboid shape. Similarly, the stack 2A may have a generally cuboid shape. The component body 2 may be chamfered along its ridgeline. In the following description, the direction in which the two sides of the component body 2 face each other may be referred to as the longitudinal direction DL, the direction in which the front and rear surfaces of the component body 2 face each other may be referred to as the transverse direction DW, and the direction in which the upper and lower surfaces of the component body 2 face each other may be referred to as the stacking direction DS.

[0058] External electrodes 6A and 6B are disposed on opposite sides of the component body 2, such that external electrode 6A is separated from external electrode 6B. Each of external electrodes 6A and 6B is present on the associated side of the component body 2 and extends from the side of the component body 2 to the front surface, rear surface, upper surface, and lower surface of the component body 2. External electrode 6A has the same construction as external electrode 6B.

[0059] Internal electrode layers 3A and 3B are arranged at different positions along the longitudinal direction DL within the laminate 2A. Specifically, internal electrode layer 3A may be positioned closer to the left side of the component body 2 than internal electrode layer 3B, and internal electrode layer 3B may be positioned closer to the opposite side (right side) of the component body 2 than internal electrode layer 3A. The end of internal electrode layer 3A is led out to the end of dielectric layer 4 on one side of the longitudinal direction DL of component body 2 and connected to external electrode 6A. The end of internal electrode layer 3B is led out to the opposite end of dielectric layer 4 on the other side of the longitudinal direction DL of component body 2 and connected to external electrode 6B.

[0060] On the other hand, in a direction orthogonal to the side surfaces of the component body 2 (longitudinal DL) (lateral DW), the ends of the internal electrode layers 3A and 3B are covered by the dielectric layer 4. In the lateral DW, the position of the end of the internal electrode layer 3A can be aligned with the position of the end of the internal electrode layer 3B.

[0061] In one example, the external dimensions of the multilayer ceramic capacitor 1A can satisfy the following conditions: the length is greater than the width, and the width is greater than the height; or the length is greater than the width, and the width is greater than or equal to the height. For example, the multilayer ceramic capacitor 1A can have a height of 1.0 mm, a width of 0.5 mm, and a height of 0.15 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm. The internal electrode layers 3A and 3B, and the dielectric layer 4 can each have a thickness ranging from 0.05 μm to 5 μm in the stacking direction DS. For example, the thickness of the internal electrode layer 3A is 0.3 μm, the thickness of the internal electrode layer 3B is 0.3 μm, and the thickness of the dielectric layer 4 is 0.3 μm.

[0062] The materials used for the internal electrode layers 3A and 3B can be selected from metals such as copper (Cu), nickel (Ni), titanium (Ti), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), tantalum (Ta), and tungsten (W), or can be alloys including any of these metals.

[0063] The material used for dielectric layer 4 may include, for example, a ceramic material with a perovskite structure as a main component. Including 50 at% or more of the main component is sufficient. The ceramic material used for dielectric layer 4 may be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium zirconate, titanium dioxide, etc.

[0064] The main components of the materials of the lower cover layer 5A and the upper cover layer 5B can be, for example, ceramic materials. If the main components of the lower cover layer 5A and the upper cover layer 5B are ceramic materials, then the main components of the ceramic materials of the lower cover layer 5A and the upper cover layer 5B can be the same as the main components of the ceramic materials of the dielectric layer 4.

[0065] Each of the external electrodes 6A and 6B includes a base layer (bottom layer) 7 formed on the component body 2 and a plating layer 9 formed on the base layer 7. Each of the external electrodes 6A and 6B has a mounting surface M1, a side surface M2, and a top surface M3. The mounting surface M1 is the surface facing the circuit board on which the multilayer ceramic capacitor 1A will be mounted. The mounting surface M1 is located below the bottom surface of the component body 2. The top surface M3 is the surface opposite to the mounting surface M1.

[0066] The surface (upper surface M3) of each of the external electrodes 6A and 6B, excluding the mounting surface M1 and side surface M2, is covered by a cover layer 8. A plating layer 9 is formed on the mounting surface M1 and side surface M2 of the base layer 7 of each of the external electrodes 6A and 6B. It should be noted that the plating layer 9 can be formed not only on the mounting surface M1 and side surface M2 of the base layer 7 of the component body 2, but also on the front surface M4 and rear surface M4 of the base layer 7 of the component body 2. At the mounting surface M1, side surface M2, and front and rear surfaces M4, the thickness of each of the external electrodes 6A and 6B is, for example, in the range of 10 μm to 40 μm.

[0067] The conductive material of the substrate layer 7 may include a metal or alloy as a main component, such as at least one selected from Cu, iron (Fe), zinc (Zn), aluminum (Al), Ni, Pt, Pd, Ag, Au, and tin (Sn). Each of the substrate layers 7 may include particles of a common material. When the particles of the common material are mixed in each substrate layer 7 in the form of islands, the common material can reduce the difference between the coefficient of thermal expansion of the element body 2 and the coefficient of thermal expansion of the substrate layer 7, and can alleviate the stress applied to the substrate layer 7. The common material is, for example, a ceramic component as a main component of the dielectric layer 4. Each of the substrate layers 7 may include a glass component. When the glass component is mixed in each substrate layer 7, the glass component can, for example, increase the densification of the substrate layer 7. The glass component is, for example, an oxide of barium (Ba), strontium (Sr), calcium (Ca), Zn, Al, silicon (Si), boron (B), etc.

[0068] A capping layer 8 is formed on the upper surface M3 of the base layer 7 of each of the external electrodes 6A and 6B. The capping layer 8 comprises an oxide film formed by the oxidation of the metal in the base layer 7 and a surface layer made of a co-material of the base layer 7 exposed on the surface of the base layer 7. The oxide film and the co-material of the base layer 7 coexist on the surface of each capping layer 8. The material used for the capping layer 8 comprises an oxide film of the metal used as a conductive material of the base layer 7. The material used for the capping layer 8 may further comprise the co-material of the base layer 7. The oxide film has a thickness, for example, from 0.05 μm to 3 μm. The composition of the oxide film is, for example, nickel oxide or copper oxide. The co-material in the base layer 7 is, for example, a ceramic oxide that is the main component of the dielectric layer 4, and the main component of this ceramic oxide is barium titanate. The metal oxide film and the co-material coexist on the surface of each capping layer 8, and therefore wet solder does not easily move to the surface of the capping layer 8.

[0069] Each of the base layer 7 and the capping layer 8 may include a metallic component included in the element body 2. This metallic component may be, for example, Mg. The metallic component may also additionally contain small amounts of Ni, Cr, Sr, Al, Na, or Fe. In this configuration, each of the base layer 7 and the capping layer 8 may include, for example, a compound containing Mg, Ni, or O, a metal used as a conductive material in the base layer 7, a metal included in the element body 2, and a compound containing oxygen.

[0070] The materials used for coating 9 include, for example, metals as main components, such as Cu, Ni, Al, Zn, or Sn, or alloys of two or more of these metals. Each coating 9 can be a coating made of a single metal component, or it can have a multilayer structure comprising multiple different metal components. Figure 2 As shown, for example, each plating layer 9 can have a three-layer structure consisting of a Cu plating layer 9A formed on the substrate layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A improves the adhesion between the plating layer 9 and the substrate layer 7. The Ni plating layer 9B improves the thermal resistance of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C improves the wettability of the solder on the plating layer 9. The plating layer 9 is formed on a portion of each substrate layer 7 and is electrically continuous with the internal electrode layer. Furthermore, each plating layer 9 can be electrically continuous with terminals on the circuit board via solder. When the metal composition of the substrate layer 7 is Cu, the Cu plating layer 9A may not be formed. If the Cu plating layer 9A is not formed, each plating layer 9 can have a two-layer structure consisting of a Ni plating layer 9B and a Sn plating layer 9C formed on the Ni plating layer 9B.

[0071] According to the first embodiment described above, the upper surface M3 of each of the external electrodes 6A and 6B is covered with a capping layer 8, and a plating layer 9 is formed on the mounting surface M1 and side surface M2 of each external electrode 6A and 6B. This configuration allows solder to wet the side surface M2 of each external electrode 6A and 6B while preventing solder from wetting the upper surface M3 of each external electrode 6A and 6B. Therefore, even if excessive solder is provided, the above configuration can prevent any increase in the height of the multilayer ceramic capacitor 1A mounted on the circuit board, while preventing solder from diffusing out of the mounting area of ​​the multilayer ceramic capacitor 1A (or reducing the amount of solder diffusing out of the mounting area of ​​the capacitor 1A). Therefore, it is possible to mount multiple electronic components on the circuit board with high density while preventing the height of the circuit board on which the electronic components are mounted from exceeding the design value. Furthermore, the capping layer on the upper surface of the component body 2 can alleviate mechanical stress applied from above (if any) and can prevent any cracks, breaks, or fragmentation of the component body 2.

[0072] Second Embodiment

[0073] Figure 3 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to a second embodiment of the present invention. Figures 4A to 4H , Figure 4I and Figure 4J These are a series of cross-sectional views illustrating a method for manufacturing a multilayer ceramic capacitor according to a second embodiment. It should be noted that... Figures 4C to 4H , Figure 4I and Figure 4J For ease of explanation, only two internal electrode layers 3A and two internal electrode layers 3B are shown, which are stacked alternately via a dielectric layer 4.

[0074] exist Figure 3 In step S1, an organic binder and an organic solvent, used as dispersants and forming aids, are added to the dielectric material powder, which is then pulverized and mixed to produce a slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may include additives. Additives are, for example, oxides or glasses of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0075] Next, as Figure 3 The steps shown in step S2 and Figure 4A As shown, a slurry comprising ceramic powder is applied in sheet form onto a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a polyethylene terephthalate (PET) film. The slurry can be applied by blade coating, die coating, gravure coating, etc. Step S2 is repeated to prepare multiple green sheets 24.

[0076] Next, as Figure 3 The steps shown in step S3 and Figure 4B As shown, the conductive paste, which will become the internal electrode, is applied in a predetermined pattern to the green sheet prepared in step S1 to form a shape as shown. Figure 1On each of the green sheets 24 of the internal electrode layers 3A and 3B shown, a plurality of internal electrode patterns 23 are formed on the green sheet 24. In step S3, a plurality of internal electrode patterns 23 may be formed on a single green sheet 24 such that the internal electrode patterns 23 are separated from each other in the longitudinal direction of the green sheet 24. The conductive paste for the internal electrodes includes metal powder used as the material for the internal electrode layers 3A and 3B. For example, if the metal used as the material for the internal electrode layers 3A and 3B is Ni, then the conductive paste for the internal electrodes includes Ni powder. The conductive paste for the internal electrodes includes a binder, solvent, and additives. The conductive paste for the internal electrodes may include a ceramic material, which is a major component of the dielectric layer 4, as a co-material. The conductive paste for the internal electrodes can be applied by screen printing, inkjet printing, gravure printing, etc.

[0077] Next, as Figure 3 The steps shown in step S4 and Figure 4C As shown, a multilayer block 25 (a block of green sheets 24) is manufactured by stacking green sheets 24 on which internal electrode patterns 23 are formed and green sheets 24A on which internal electrode patterns are not formed, in a predetermined order. The green sheet 24A on which internal electrode patterns 23 are not formed serves as the outer layer. In step S4, the green sheets 24 on which internal electrode patterns 23 are formed are divided into two groups: green sheets 24 on which internal electrode patterns 23A are formed and green sheets 24 on which internal electrode patterns 23B are formed. Then, the green sheets 24 on which internal electrode patterns 23A and green sheets 24 on which internal electrode patterns 23B are formed are stacked alternately in the stacking direction, such that the internal electrode patterns 23A on the green sheet 24 and the internal electrode patterns 23B on the next or adjacent green sheet 24 are alternately shifted in the longitudinal direction of the green sheet 24. Furthermore, three types of portions are defined in the green sheet block 25. Specifically, the green sheet block 25 is defined by a portion in which only the internal electrode pattern 23A is stacked in the stacking direction, a portion in which the internal electrode patterns 23A and 23B are stacked alternately in the stacking direction, and a portion in which only the internal electrode pattern 23B is stacked in the stacking direction.

[0078] Next, as Figure 3 As shown in step S5 and Figure 4D As shown, for in Figure 3 The laminate 25 obtained in step S4 is pressed to press the green sheet 24 together. The laminate 25 can be pressed by, for example, sandwiching the laminate 25 between resin films and applying hydrostatic pressure to the laminate 25.

[0079] Next, as Figure 3 The steps shown in step S6 and Figure 4EAs shown, the pressed laminate 25 is cut, separating it into multiple component bodies, each component body having a cuboid shape. Each component body has six surfaces. As indicated by the multiple vertical dashed lines 27, the cutting of the laminate 25 is performed at portions where only the internal electrode pattern 23A exists in the stacking direction and at portions where only the internal electrode pattern 23B exists in the stacking direction. The laminate 25 can be cut, for example, by a blade cutter. The resulting component bodies 2 are... Figure 4F As shown in the image.

[0080] like Figure 4F As shown, in each individual component body 2, internal electrode layers 3A and 3B are stacked alternately, with a dielectric layer 4 inserted between them. Internal electrode layer 3A is exposed on one side of component body 2, and internal electrode layer 3B is exposed on the other side of component body 2.

[0081] Next, as Figure 3 As shown in step S7, remove in Figure 3 The adhesive included in each component body 2 obtained in step S6. To remove the adhesive, the component body is heated, for example, in a N2 atmosphere at approximately 350°C.

[0082] Next, as Figure 3 As shown in step S8, the conductive paste for the substrate (bottom layer) 7 is applied to the substrate. Figure 3 In step S7, the adhesive is removed from two sides of each element body 2 and from the edges of the remaining four surfaces of the element body 2 that are in contact with these two sides. The conductive paste is then dried. The conductive paste for the base layer includes powder or filler of a metal used as the conductive material of the base layer 7. For example, if the metal used as the conductive material of the base layer 7 is Ni, the conductive paste for the base layer includes Ni powder or Ni filler. The conductive paste for the base layer includes, for example, a ceramic component as a co-material, which is the main component of the dielectric layer 4. For example, ceramic oxide particles (D-50 particle size of 0.8 μm to 4 μm) with barium titanate as the main component are mixed into the conductive paste for the base layer as a co-material. The conductive paste for the base layer also includes an adhesive and a solvent.

[0083] Next, as Figure 3 The steps shown in step S9 and Figure 4G As shown, for in Figure 3In step S8, the component body 2, to which conductive paste for the base layer is applied, undergoes sintering, such that the internal electrode layers 3A and 3B are integrated with the dielectric layer 4 in each component body 2, and the base layer 7 is formed and integrated with the component body 2. The component body 2 is sintered, for example, in a sintering furnace at a temperature range of 1000 to 1350°C for 10 minutes to 2 hours. If a base metal such as Ni or Cu is used in the internal electrode layers 3A and 3B, the component body 2 can be sintered while maintaining a reducing atmosphere inside the sintering furnace to prevent oxidation of the internal electrode layers 3A and 3B.

[0084] Next, as Figure 3 The steps shown in step S10 and Figure 4H As shown, the metal exposed on the surface of each substrate layer 7 is oxidized, such that a capping layer 8 comprising an oxide film of the metal is formed on the surface of each substrate layer 7. The capping layer 8 may include the same material as the substrate layer 7. In the oxidation of the metal exposed on the surface of each substrate layer 7, a re-oxidation process can be performed, for example, in an N2 gas atmosphere, at a temperature range of 600°C to 1000°C. Oxygen can be added to the atmosphere gas during the re-oxidation process, such that the oxide film of the metal exposed on the surface of each substrate layer 7 is formed to a sufficient thickness.

[0085] Next, as Figure 3 As shown in step S11 and Figure 4I As shown, a pre-plating treatment is performed. Specifically, the oxide film is removed from the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of each substrate layer 7 by sandblasting (polishing), exposing the metal included in the substrate layer 7 at the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of the substrate layer 7. During the sandblasting process, as... Figure 5A As shown, component bodies 2 are placed on substrate 31 within a sandblasting apparatus, with the mounting surface M1 of each component body 2 facing upwards and the upper surface M3 in contact with substrate 31. Then, sandblasting media is projected directly onto the component bodies 2 from above. The sandblasting media projected directly from above reaches the side, front, and rear surfaces of each component body 2, but does not reach the upper surface M3. Therefore, the oxide film on the substrate layer 7 can be removed from the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of each substrate layer 7, while the oxide film remains on the upper surface M3 of the substrate layer 7.

[0086] Next, as Figure 3 As shown in step S12 and Figure 4JAs shown, a plating layer 9 is formed on the mounting surface M1 and side surface M2 of each substrate layer 7. For example, each plating layer 9 can be formed by sequentially performing Cu plating, Ni plating, and Sn plating. During this plating process, the component body 2, with the oxide film removed from the mounting surface M1 and side surface M2 of the substrate layer 7, is placed in a tank along with the plating solution. The tank can then be rotated using electricity supplied to it. As a result, a plating layer 9 can be formed on the substrate layer 7 of each component body 2. During this plating process, since an oxide film exists on the upper surface M3 of the substrate layer 7, no plating layer is formed on the substrate layer 7 on the upper surface M3 of the component body 2.

[0087] Figure 5A It is shown Figure 4I A floor plan diagram illustrating an example of the process. Figure 5B This shows the section cut along the longitudinal direction. Figure 5A A cross-sectional view of the process.

[0088] like Figure 5A and Figure 5B As shown, multiple component bodies 2 are arranged on a substrate 31. In each component body 2, an oxide film is formed on the surface of each base layer 7. When the component body 2 is arranged on the substrate 31, the upper surface M3 of each component body 2 is fixed to the substrate 31 via a fixing strap 32, such that the mounting surface M1 of the component body 2 faces upward. Then, a blasting medium 34 is projected onto the component body 2 from a nozzle 33 located directly above it. The blasting medium 34 is, for example, zircon particles or alumina particles.

[0089] The conditions used to project the blasting medium during sandblasting can include the projection speed, projection volume, and projection area. The projection speed is set by adjusting the pressure and path of the blasting medium 34. The projection volume is set by adjusting the medium circulation and projection time. The projection area is set by adjusting the nozzle shape and the distance between the component body 2 and the nozzle 33.

[0090] The blasting medium 34 projected from nozzle 33 reaches the opposite sides, front surface, and rear surface of each component body 2. Therefore, the oxide film on the substrate layer 7 is removed from the mounting surface M1, the two sides M2, the front surface M4, and the rear surface M4 of each component body 2, while the oxide film remains on the upper surface M3 of the substrate layer 7. The amount of oxide film blasted (polished) from the mounting surface M1, sides M2, front surface M4, and rear surface M4 of each substrate layer 7 can be set within a range that allows the formation of a coating 9 on the mounting surface M1, sides M2, front surface M4, and rear surface M4 of the substrate layer 7.

[0091] According to the second embodiment described above, the oxide film on the substrate layer 7 is removed from the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of the external electrodes 6A and 6B by sandblasting. This allows for the selective and efficient formation of the plating layer 9 on the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of the external electrodes 6A and 6B, while the upper surface M3 of the external electrodes 6A and 6B remains covered by the capping layer 8. Therefore, the above manufacturing method prevents an increase in the number of manufacturing processes and prevents the height of the circuit board on which electronic components are mounted from exceeding the design value. Furthermore, it enables the high-density mounting of multiple electronic components on the circuit board.

[0092] In the above manufacturing method, the sandblasting process is used to remove the cover layer 8 from the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of the external electrodes 6A and 6B. However, the present invention is not limited to this manufacturing method. Instead of the sandblasting process, isotropic dry etching (e.g., plasma etching) or chemical polishing (e.g., wet etching) can be used.

[0093] Third Embodiment

[0094] Figure 6A This is a cross-sectional view showing an exemplary construction of the end of the capping layer of a multilayer ceramic capacitor according to a third embodiment of the present invention.

[0095] refer to Figure 6A The substrate 7 includes a chamfered surface 7C on its edges. The chamfered surface 7C of the substrate 7 may have a shape obtained by cutting off the edges of the substrate 7, or it may have a curved shape. For example, the radius of curvature of the chamfered surface 7C of the substrate 7 may be in the range of 1 μm to 50 μm.

[0096] exist Figure 6A In this structure, at least a portion of the end of the cover layer 8 extends along the chamfered surface 7C of the base layer 7. This configuration prevents wet solder from reaching the upper surface M3 of the base layer 7 while ensuring that wet solder reaches and covers a sufficient area from the side M2 ​​of the base layer 7 to the left end of the cover layer 8.

[0097] At the location where the left end of the cover layer 8 contacts the side surface M2 of the base layer 7, the angle θ formed by the tangent of the upper surface M3 of the external electrode 6A and the chamfered surface 7C can be greater than 45 degrees. This structure effectively prevents solder from reaching the upper surface M3 from the side surface M2. The angle θ can be determined by... Figure 5A and Figure 5B The sandblasting process shown is controlled by adjusting the conditions used to project the sandblasting medium.

[0098] Figure 6BThis is a cross-sectional view showing an exemplary construction of the interface between the ends of the base layer 7 and the capping layer 8 of a multilayer ceramic capacitor according to a third embodiment. Figure 6B Cut along a plane parallel to the side M2 ​​of the base layer 7.

[0099] refer to Figure 6B Corrugations 8C are formed at the ends of the cover layer 8 on the chamfered surface 7C of the base layer 7. These corrugations 8C are due to... Figure 5B This is caused by the variation in the blasting medium 34 that has reached the side M2 ​​of the component body 2. By controlling the aforementioned variation in the blasting medium 34 by changing the position of the blasting nozzle 33 during the blasting process, the height difference TH of the corrugations 8C at the end of the cover layer 8 can be limited to, for example, a range of 0.1 μm to 10 μm. This makes it virtually impossible for any crack to propagate linearly, even if solder has wetted the end of the cover layer 8.

[0100] According to the third embodiment described above, the end of the cover layer 8 is positioned along the chamfered surface 7C of the base layer 7. This configuration ensures that a sufficient area is wetted by solder and prevents solder from diffusing outward from the mounting area of ​​the multilayer ceramic capacitor 1A.

[0101] Fourth embodiment

[0102] Figure 7A This is a cross-sectional view showing the construction of a circuit board device according to a fourth embodiment of the present invention. The circuit board device includes a circuit board 41, and a multilayer ceramic capacitor 1A is mounted on the circuit board 41.

[0103] refer to Figure 7AGrounding electrodes 42A and 42B are formed on circuit board 41. Multilayer ceramic capacitor 1A is connected to grounding electrodes 42A and 42B via solder layers 43A and 43B respectively adhered to tin plating layers 9C and 9C on external electrodes 6A and 6B. The upper surface M3 of each external electrode 6A and 6B is covered with a capping layer 8. Plating layers 9A to 9C are formed on the mounting surface M1 and side surface M2 of each external electrode 6A and 6B. When the multilayer ceramic capacitor 1A is mounted to circuit board 41 by soldering, this configuration allows solder to wet and be absorbed by the side surface M2, front surface M4, and rear surface M4 of each external electrode 6A and 6B, while preventing solder from wetting the upper surface M3 of each external electrode 6A and 6B. Therefore, even if excessive solder is supplied to grounding electrodes 42A and 42B, solder diffusion outward from grounding electrodes 42A and 42B is prevented, while also preventing the height of circuit board 41 on which the multilayer ceramic capacitor 1A is mounted from exceeding the design value. Multiple capacitors 1A can be mounted on the same circuit board in a similar manner. Therefore, the above configuration can reduce the spacing between electronic components 1A mounted on the circuit board 41 and increase the density of mounted electronic components 1A, while suppressing short circuits between electronic components 1A mounted on the circuit board 41.

[0104] In this configuration, the wet solder can move upwards to cover the Sn plating layer 9C. Therefore, compared to a configuration in which a cover layer 8 is formed on the side surface M2 of the external electrodes 6A and 6B, the area for absorbing solder can be increased.

[0105] Furthermore, as the wet solder moves upward to the side surface M2 of the external electrodes 6A and 6B, the multilayer ceramic capacitor 1A can be supported on the circuit board 41 at the mounting surface M1 and side surface M2 of the external electrodes 6A and 6B. Therefore, compared to a device that only supports the multilayer ceramic capacitor 1A on the circuit board 41 at the mounting surface M1 of the external electrodes 6A and 6B, the mounting strength of the multilayer ceramic capacitor 1A can be improved. Therefore, even if the circuit board 41 is used as an automotive circuit board and the circuit board 41 experiences vibration during vehicle operation, the multilayer ceramic capacitor 1A can resist vibration and will not fall off the circuit board 41.

[0106] Furthermore, any stress applied to the component body 2 from above can be absorbed by the base layer 7 and the capping layer 8 on the upper surface M3 of the external electrodes 6A and 6B. Therefore, the construction of this embodiment can reduce the possibility of any cracks appearing in the component body 2.

[0107] According to the fourth embodiment described above, the cover layer 8 is disposed on the upper surface M3 of the external electrodes 6A and 6B, while allowing solder to wet the mounting surface M1 and side surface M2 of the external electrodes 6A and 6B. Therefore, the mounting density of electronic components 1A on the circuit board 41 can be increased, while the reliability of the multilayer ceramic capacitor 1A mounted on the circuit board 41 can be improved.

[0108] First Comparative Example

[0109] Figure 7B This is a cross-sectional view showing the construction of a circuit board assembly in which a multilayer ceramic capacitor 1A' according to the first comparative example is mounted on a circuit board 41.

[0110] refer to Figure 7B The multilayer ceramic capacitor 1A' includes external electrodes 6A' and 6B', which respectively replace... Figure 7A The external electrodes 6A and 6B are shown. Each of the external electrodes 6A' and 6B' includes a capping layer 8', a Cu plating layer 9A', a Ni plating layer 9B', and a Sn plating layer 9C' to respectively replace... Figure 7A The coating layer 8, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C are shown in the figure.

[0111] The surfaces of the external electrodes 6A' and 6B', excluding the mounting surface M1 (side surface M2 and top surface M3), are covered with a capping layer 8'. A Cu plating layer 9A', a Ni plating layer 9B', and a Sn plating layer 9C' are formed on the mounting surface M1 of the base layer 7 of the external electrodes 6A' and 6B'.

[0112] Ground electrodes 42A' and 42B' are formed on circuit board 41. Multilayer ceramic capacitor 1A' is connected to ground electrodes 42A' and 42B' via solder layers 43A' and 43B' adhered to the Sn plating layer 9C' of external electrodes 6A' and 6B'. Since the sides M2 of external electrodes 6A' and 6B' are covered by a capping layer 8', no solder wets the sides M2 of external electrodes 6A' and 6B'. Therefore, if excessive solder is supplied, solder layers 43A' and 43B' diffuse from the mounting surface M1 onto circuit board 41, which may hinder the high-density mounting of electronic components 1A' on circuit board 41.

[0113] Second Comparative Example

[0114] Figure 7C This is a cross-sectional view showing the construction of a circuit board assembly according to the second comparative example, in which the multilayer ceramic capacitor 1A'' is mounted on a circuit board 41.

[0115] refer to Figure 7C The multilayer ceramic capacitor 1A'' includes external electrodes 6A'' and 6B'', which respectively replace... Figure 7A The external electrodes 6A and 6B are shown. Each of the external electrodes 6A' and 6B' includes a Cu plating 9A', a Ni plating 9B'', and a Sn plating 9C'', replacing... Figure 7A The coating layer 8, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C are shown in the figure.

[0116] Cu plating 9A'', Ni plating 9B'', and Sn plating 9C'' are formed on the mounting surface M1, side surface M2, and upper surface M3 of the base layer 7 of the external electrodes 6A'' and 6B''.

[0117] The multilayer ceramic capacitor 1A'' is connected to the ground electrodes 42A and 42B via solder layers 43A'' and 43B'' adhered to the Sn plating layers 9C'' and 9C'' of the external electrodes 6A'' and 6B''. In this configuration, solder wets the upper surface M3 via the sides M2 and M2 of the external electrodes 6A'' and 6B'', forming solder layers 43A'' and 43B'' protruding from the upper surfaces M3 and M3 of the external electrodes 6A'' and 6B''. Therefore, the height of the circuit board assembly in which the multilayer ceramic capacitor 1A'' is mounted on the circuit board 41 is greater than the originally designed height.

[0118] Fifth embodiment

[0119] Figure 8 This is a plan view showing the structure of a multilayer ceramic capacitor 1B as seen from the cover layers 8A and 8B according to a fifth embodiment of the present invention.

[0120] refer to Figure 8 ,replace Figure 1 The multilayer ceramic capacitor 1B shown includes capping layers 8A and 8B. The multilayer ceramic capacitor 1B can have a similar design to... Figure 1 The structure of the multilayer ceramic capacitor 1A shown is the same as that of the multilayer ceramic capacitor 1B, except that the multilayer ceramic capacitor 1B includes cover layers 8A and 8B instead. Figure 1 The capping layer 8 is shown. Capping layers 8A and 8B are located in the respective portions including boundary regions, where, on the upper surfaces M3 of the outer electrodes 6A and 6B, the ends of capping layers 8A and 8B contact the side surfaces M2 of the base layer 7A and 7B. For example, each of capping layers 8A and 8B can be formed as a strip pattern (U-shape) continuous along the outer peripheries on three sides of the upper surface M3 of each outer electrode 6A and 6B, such that each of capping layers 8A and 8B covers the ends of the upper surface M3 of each outer electrode 6A and 6B. The outer periphery of the upper surface M3 of each outer electrode 6A and 6B includes a side (edge) contacting the side surface M2, a side contacting the front surface M4, and a side contacting the rear surface M4. When viewed from above, each of capping layers 8A and 8B has a rectangle with an open side.

[0121] During the process of forming capping layers 8A and 8B on the upper surfaces M3 of external electrodes 6A and 6B respectively, the internal regions of capping layers 8A and 8B on the upper surfaces M3 of external electrodes 6A and 6B can be covered with resist films, and then, by bonding... Figure 5A and Figure 5B The described method involves sandblasting the upper surfaces M3 and M3 of the external electrodes 6A and 6B.

[0122] According to the fifth embodiment described above, cover layers 8A and 8B are formed on the upper surface M3 of the external electrode 6A and the upper surface M3 of the external electrode 6B, respectively, and plating layers 9 are formed on the mounting surface M1 and side surface M2 of the external electrode 6A and the mounting surface M1 and side surface M2 of the external electrode 6B, respectively. Therefore, any increase in the height of the multilayer ceramic capacitor 1B mounted on the circuit board is prevented, while preventing solder from diffusing outward from the mounting area of ​​the multilayer ceramic capacitor 1B. Electronic components can be mounted on the circuit board with high density, while maintaining the height of the circuit board assembly on which the electronic components are mounted on the circuit board not exceeding the designed height.

[0123] In the above embodiments, each of the capping layers 8 (8A, 8B) includes an oxide film of a metal that serves as the conductive material of the base layer 7 (7A, 7B). Alternatively, the capping layers 8 (8A, 8B) may include a glass phase with the same composition as the glass composition included in the base layer 7 (7A, 7B).

[0124] Sixth Embodiment

[0125] Figure 9 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to a sixth embodiment of the present invention. It should be noted that, in conjunction with... Figure 3 The described method forms a capping layer 8 comprising an oxide film of a metal serving as the conductive material of the substrate layer 7, and Figure 9 The capping layer 8 formed by the method comprises a glass phase with the same composition as the glass components included in the base layer 7.

[0126] Figure 9 Steps S21 to S27 are respectively similar to Figure 3 Steps S1 to S7. Specifically, steps S21 to S27, in a similar manner to steps S1 to S7, form the component body 2 from which the adhesive has been removed. The component body 2 has six surfaces.

[0127] Next, as Figure 9 As shown in step S28, sintering is performed in Figure 9In step S27, the binder-coated component body 2 has been removed to integrate the internal electrode layers 3A and 3B with the dielectric layer 4. For example, the component body 2 is sintered in a sintering furnace at a temperature range of 1000°C to 1350°C for ten minutes to two hours. If a base metal such as Ni or Cu is used in the internal electrode layers 3A and 3B, the component body 2 can be sintered in the sintering furnace while the furnace interior is maintained in a reducing atmosphere to prevent oxidation of the internal electrode layers 3A and 3B.

[0128] After step S28, as Figure 9 As indicated in step S29, a conductive paste for the substrate layer is applied to two opposite sides of the element body 2 and the edge portions of the remaining four surfaces adjacent to those two sides, and then the conductive paste for the substrate layer is dried. The conductive paste for the substrate layer includes powder or filler of a metal used as the conductive material of the substrate layer 7. For example, if the metal used as the conductive material of the substrate layer 7 is Cu, the conductive paste for the substrate layer includes Cu powder or Cu filler. The conductive paste for the substrate layer includes sintering aids for glass (e.g., SiO2, etc.). The amount of sintering aids for glass can be in the range of, for example, 11 wt% to 13 wt%.

[0129] Next, the component body 2, to which conductive paste for the substrate layer has been applied, is sintered to form a substrate layer 7 integral with the component body 2. For example, the component body 2 is sintered in a furnace at 850°C for at least 15 minutes. On the surface of each substrate layer 7 sintered under these conditions, a glass phase with the same composition as the glass component contained in the surface of the substrate layer 7 is formed, thereby forming a capping layer 8 on the substrate layer 7. During installation, the surface of each substrate layer 7 where the glass phase has been surfaced is not electroplated or welded. It should be noted that the higher the sintering temperature, the longer the sintering time, or the greater the amount of sintering aid in the glass, the easier it is for the glass phase to surface onto the surface of the substrate layer 7. Therefore, the thickness of the glass phase can be controlled by adjusting the sintering temperature, sintering time, and amount of sintering aid.

[0130] Next, as Figure 9 As shown in steps S30 and S31, by... Figure 3 The processes in steps S11 and S12 are similar to the pre-plating treatment and the subsequent plating process.

[0131] According to the sixth embodiment described above, a capping layer 8 comprising a glass phase is formed, the composition of which is the same as that of the glass components included in the base layer 7, and the remaining structure can be similar to that of the first to fifth embodiments. This capping layer 8 also prevents solder from wetting the surfaces of the external electrodes 6A and 6B covered by the capping layer 8.

[0132] Seventh Embodiment

[0133] Figure 10 This is a perspective view showing the construction of an electronic component 61 according to a seventh embodiment of the present invention. In the seventh embodiment, a chip inductor 61 is described as an example of an electronic component.

[0134] refer to Figure 10 The chip inductor 61 includes a component body 62 and external electrodes 66A and 66B. The component body 62 includes a coil pattern 63, internal electrode layers 63A and 63B, and a magnetic material 64. The component body 62 may have a generally cuboid shape. The external electrodes 66A and 66B are located on opposite sides of the component body 62, such that external electrode 66A is separated from external electrode 66B. Each of the external electrodes 66A and 66B is present on an associated side of the component body 62 and extends from side M2 ​​to the front, rear, upper, and lower surfaces of the component body 62.

[0135] The coil pattern 63 and the internal electrode layers 63A and 63B are covered by magnetic material 64. However, one end of the internal electrode layer 63A extends out of the magnetic material 64 at one side of the component body 62 and is connected to the external electrode 66A. One end of the internal electrode layer 63B extends out of the magnetic material 64 at the other side of the component body 62 and is connected to the external electrode 66B.

[0136] The materials for the coil pattern 63 and the internal electrode layers 63A and 63B can be selected, for example, from metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or can be alloys of any of these metals. The magnetic material 64 is, for example, ferrite.

[0137] Each of the external electrodes 66A and 66B includes a base layer (bottom layer) 67 and a plating layer 69. Each of the external electrodes 66A and 66B has a mounting surface M1, a side surface M2, a top surface M3, a front surface M4, and a rear surface M4. The mounting surface M1 is the surface facing the circuit board on which the chip inductor 61 is to be mounted. The top surface M3 is the surface opposite to the mounting surface M1.

[0138] The conductive material used for the substrate 67 may include a metal or alloy as the main component, which includes at least one selected from, for example, Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. Each substrate 67 includes a co-material. The co-material is, for example, a ceramic component that is the main component of the magnetic material 64. Each substrate 67 may include a glass component. The glass component is, for example, an oxide of Ba, Sr, Ca, Zn, Al, Si, B, etc.

[0139] In addition to the mounting surface M1, side surface M2, front surface M4, and rear surface M4, the surface (upper surface M3) of each of the external electrodes 66A and 66B is covered with a capping layer 68. The capping layer 68 may comprise an oxide film of a metal serving as the conductive material of the base layer 67, or a glass phase comprising the same composition as the glass component included in the base layer 67. A plating layer 69 is formed on the mounting surface M1, side surface M2, front surface M4, and rear surface M4 of the base layer 67 in each of the external electrodes 66A and 66B.

[0140] According to the seventh embodiment described above, a cover layer 68 is disposed on the upper surface M3 of the external electrodes 66A and 66B of the chip inductor 61. This prevents the height of the chip inductor 61 mounted on the circuit board from increasing, while also preventing solder from spreading out of the mounting area of ​​the chip inductor 61.

[0141] Eighth embodiment

[0142] Figure 11 This is a perspective view showing the structure of the electronic component 71 according to the eighth embodiment of the present invention. Figure 11 A chip resistor 71 is shown as an example of an electronic component.

[0143] refer to Figure 11 The chip resistor 71 includes a component body 72, external electrodes 76A and 76B, and a protective film 75. The component body 72 includes a resistor body 73, an internal electrode layer 73B, and a substrate 74. The component body 72 may have a generally cuboid shape. The external electrodes 76A and 76B are located on opposite sides of the component body 72, such that the external electrodes 76A and 76B are separated from each other. Each of the external electrodes 76A and 76B is present on an associated side of the component body 72 and extends from the side to the upper and lower surfaces of the component body 72.

[0144] A resistor body 73 and an internal electrode layer 73B are disposed on a substrate 74 and covered by a protective film 75. One end of the resistor body 73 is connected to the internal electrode layer 73B on the substrate 74. The internal electrode layer 73B extends to one side of the component body 72 and is connected to an external electrode 76B. It should be noted that another internal electrode layer (not shown) is connected to the other end of the resistor body 73 and extends to the other side of the component body 72, such that this internal electrode layer is connected to an external electrode 76A.

[0145] The material of resistor body 73 can be, for example, selected from metals such as Ag and Pd, or can be an alloy comprising any of these metals. Alternatively, the material for resistor body 73 can be a metal oxide, such as ruthenium oxide. The material for internal electrode layer 73B can be selected from metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or can be an alloy comprising any of these metals. The material for substrate 74 is, for example, a ceramic oxide, such as alumina. The material for protective film 75 is, for example, glass or resin.

[0146] Each of the external electrodes 76A and 76B includes a base layer 77 and a plating layer 79. Each of the external electrodes 76A and 76B has a mounting surface M1, a side surface M2, and a top surface M3. The mounting surface M1 is the surface of the circuit board on which the chip resistor 71 is to be mounted. The top surface M3 is the surface opposite to the mounting surface M1.

[0147] The conductive material used for the substrate 77 may include a metal or alloy as the main component, which includes at least one selected from, for example, Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. Each substrate 77 includes a common material. The common material is, for example, a ceramic composition, which is the main component of the substrate 74. The substrate 77 may include a glass composition. The glass composition is, for example, an oxide of Ba, Sr, Ca, Zn, Al, Si, B, etc.

[0148] In addition to the mounting surface M1 and the side surface M2, the surface (upper surface M3) of each of the external electrodes 76A and 76B is covered with a capping layer 78. Each of the capping layers 78 may include an oxide film of a metal that serves as the conductive material of the base layer 77, or a glass phase with the same composition as the glass component included in the base layer 77. A plating layer 79 is formed on the mounting surface M1 and the side surface M2 of the base layer 77 of each of the external electrodes 76A and 76B.

[0149] According to the eighth embodiment described above, a cover layer 78 is disposed on the upper surface M3 of the outer electrodes 76A and 76B of the chip resistor 71. This prevents the height of the chip resistor 71 mounted on the circuit board from increasing, while also preventing solder from spreading out of the mounting area of ​​the chip resistor 71.

[0150] In the above embodiment, a capping layer is provided on the upper surface of the external electrodes to prevent solder from wetting the upper surface of the external electrodes. Alternatively, a capping layer that is less wettable than the plating on each external electrode can be provided on the upper surface of each external electrode. The wettability of the solder can be determined, for example, by the contact angle. In the above alternative configuration, the contact angle of the solder on the capping layer is greater than the contact angle of the solder on the plating layer. The contact angle can be measured, for example, as follows: An article is immersed in a bath of molten solder and then lifted out of the solder bath. Subsequently, a cross-section of the article perpendicular to the surface to be observed is examined, and the angle of contact between the solder and the surface is measured as the contact angle.

[0151] In the foregoing embodiments, a two-terminal element was used as an example of an electronic component. Alternatively, electronic components with three or more terminals, such as transistors or transformers, can be used as electronic components.

[0152] Each cover layer 8 may be composed of a resist film comprising resin, instead of the materials described in the foregoing embodiments. When a resist film is used as the cover layer 8, the cover layer 8 can be formed to the desired thickness.

[0153] This application is based on and claims priority to Japanese Patent Application No. 2020-95333, filed on June 1, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. An electronic component, comprising: The main body of the component includes the dielectric and internal electrodes; and At least one external electrode, Each of the at least one external electrode includes: A base layer, formed on multiple surfaces of the component body, is connected to the internal electrodes and comprises metal, wherein the base layer is formed on the side surfaces of the component body, and also on the front, rear, upper, and lower surfaces of the component body. A plating layer is formed on the mounting surface of the substrate layer and on the side of the substrate layer connected to the internal electrode, but not on the upper surface of the substrate layer opposite to the mounting surface, wherein the mounting surface is located below the lower surface of the component body. A cover layer is formed on the upper surface of the base layer opposite to the mounting surface of the base layer, and the cover layer is less wetted by solder compared to the plating layer.

2. The electronic component according to claim 1, wherein, The coating is formed on the front and rear surfaces of the substrate.

3. The electronic component according to claim 1 or 2, wherein, The covering layer includes an oxide film of the metal in the base layer.

4. The electronic component according to claim 1 or 2, wherein, The base layer includes a first co-material that coexists with the metal, and the cover layer includes a second co-material.

5. The electronic component according to claim 4, wherein, The first common material included in the base layer and the second common material included in the cover layer have the same composition.

6. The electronic component according to claim 5, wherein, Each of the first comaterial and the second comaterial is a ceramic oxide comprising the dielectric.

7. The electronic component according to claim 1 or 2, wherein, The coating layer is a resist film comprising resin.

8. The electronic component according to claim 1 or 2, wherein, The base layer comprises a glass component, and the capping layer comprises a glass phase having the same composition as the glass component comprised in the base layer.

9. The electronic component according to claim 1 or 2, wherein, The metal in the substrate layer is a metal containing at least one selected from Cu, Fe, Zn, Al and Ni, or an alloy containing at least one selected from Cu, Fe, Zn, Al and Ni.

10. The electronic component according to claim 1 or 2, wherein, The coating includes a Ni coating and a Sn coating formed on the Ni coating.

11. The electronic component according to claim 1 or 2, wherein, The cover layer is arranged in a strip pattern on the surface of the base layer opposite to the mounting surface of the base layer, such that the strip pattern is continuous along the edges of the base layer that contact the side, front and rear surfaces of the base layer.

12. The electronic component according to claim 1 or 2, wherein, The base layer has a chamfered surface on its edges, and at least a portion of the end of the cover layer extends along the chamfered surface of the base layer.

13. The electronic component according to claim 12, wherein, The angle formed by the tangent of the chamfered surface at the position where the end of the cover layer contacts the side of the base layer is greater than 45 degrees.

14. The electronic component according to claim 1 or 2, wherein, The internal electrode includes at least one first internal electrode layer and at least one second internal electrode layer. The component body includes a laminate, wherein the at least one first internal electrode layer and the at least one second internal electrode layer are stacked alternately, and the dielectric is inserted therein. The at least one external electrode includes a first external electrode and a second external electrode disposed on opposite sides of the laminate. The at least one first internal electrode layer is connected to the first external electrode, and the at least one second internal electrode layer is connected to the second external electrode.

15. A circuit board assembly, comprising: Circuit board; as well as An electronic component according to any one of claims 1 to 14, mounted on the circuit board, the electronic component being connected to the circuit board via a solder layer, the solder layer being adhered to the mounting surface of the plating on the electronic component, the solder layer being wetted to the side of the external electrode of the electronic component.

16. A method for manufacturing an electronic component, the method comprising the following steps: Forming a component body including a dielectric and internal electrodes; Electrode material containing metal is applied to the side surface of the component body and the surrounding surface of the side surface of the component body; The electrode material is sintered to form a base layer containing the metal on the side surface of the element body and the surrounding surface of the side surface of the element body; A cover layer is formed covering the surface of the base layer; Remove the cover layer from the mounting surface and side surface of the base layer, while leaving the cover layer on the surface opposite the mounting surface of the base layer; and A plating layer is formed on the mounting surface and the side surface of the base layer, and the cover layer is less wetted by solder compared to the plating layer.

17. The method of manufacturing an electronic component according to claim 16, wherein, The step of forming a cover layer covering the surface of the substrate layer includes: oxidizing the metal to form an oxide film of the metal on the surface of the substrate layer.

18. The method of manufacturing an electronic component according to claim 16, wherein, The electrode material comprises a glass component, and the step of forming a capping layer covering the surface of the substrate layer comprises: surface-forming a glass phase composed of the glass component on the surface of the substrate layer during sintering of the electrode material.

19. The method of manufacturing an electronic component according to any one of claims 16 to 18, wherein, The step of removing the cover layer from the mounting surface and the side surface of the base layer includes sandblasting the cover layer present on the mounting surface of the base layer.

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