Control Circuit

Abstract

The present invention provides a control circuit capable of suppressing characteristic deviation. The control circuit controls a Doherty amplifier including a carrier amplifier and a peak amplifier, and includes a resistor whose resistance value can be irreversibly adjusted and determines the bias of the peak amplifier based on the resistance value.

Description

Technical Field

[0001] The invention relates to a control circuit for controlling a Doherty amplifier. Background Art

[0002] Patent Document 1 below describes a technique related to a bias circuit of a Doherty amplifier. Patent Document 2 below describes a technique for compensating for temperature characteristics of an amplifier circuit.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2012-199746

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-171170

[0007] In the technology described in Patent Document 1, the gate voltage of the FET (Field Effect Transistor) of the peak amplifier is set to a voltage offset from the gate voltage of the FET of the carrier amplifier. This is based on the fact that when the FETs constituting the carrier amplifier and the peak amplifier are from the same wafer batch and manufactured at the same time, it can be expected that the drain current characteristics of the gate voltage of the FETs of the peak amplifier and the carrier amplifier are roughly the same.

[0008] However, the technology described in Patent Document 1 does not take into account the variations in output power-gain characteristics and output power-phase characteristics of the peak amplifier and the carrier amplifier caused by variations in operating thresholds due to individual differences between the peak amplifier and the carrier amplifier. Summary of the invention

[0009] Problems to be solved by the invention

[0010] The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress the variation in characteristics.

[0011] Means for solving problems

[0012] A control circuit according to one aspect of the present invention controls a Doherty amplifier including a carrier amplifier and a peak amplifier, and includes a resistor whose resistance value can be irreversibly adjusted and determines a bias of the peak amplifier based on the resistance value.

[0013] Effects of the Invention

[0014] According to the present invention, it is possible to suppress variations in characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 : is a figure which shows the structure of the Doherty amplifier of a comparative example.

[0016] Figure 2 It is a diagram showing the input-output characteristics of a class AB amplifier.

[0017] Figure 3 : is a graph showing the input-output characteristics of a class C amplifier.

[0018] Figure 4 1 is a diagram showing a circuit configuration of a power amplifier module that is a concept of the present invention.

[0019] Figure 5 It is a diagram showing a circuit configuration of a power amplifier module according to the first embodiment.

[0020] Figure 6 is a diagram showing the characteristics of the Doherty amplifier.

[0021] Figure 7 is a diagram showing the characteristics of the Doherty amplifier.

[0022] Figure 8 It is a diagram showing another example of a resistor array.

[0023] Fig. 9 It is a diagram showing a first adjustment process of the power amplifier module according to the first embodiment.

[0024] Fig.10 It is a diagram showing a second adjustment process of the power amplifier module according to the first embodiment.

[0025] Fig.11 It is a diagram showing the third adjustment process of the power amplifier module according to the first embodiment.

[0026] Fig.12 It is a diagram showing a circuit configuration of a power amplifier module according to the second embodiment.

[0027] Fig.13 It is a diagram showing a circuit configuration of a power amplifier module according to a third embodiment.

[0028] Fig.14 It is a diagram showing a circuit configuration of a power amplifier module according to a fourth embodiment.

[0029] Fig.15 It is a diagram showing a circuit configuration of a power amplifier module according to a fifth embodiment.

[0030] Fig.16 It is a diagram showing a circuit configuration of a power amplifier module according to a sixth embodiment.

[0031] Explanation of symbols

[0032] 1. 1A, 1B, 1C, 1D, 1E power amplifier modules;

[0033] 2, 2A, 2B, 2C, 2E 1st integrated circuit;

[0034] 3, 3A, 3B, 3C, 3D, 3E 2nd integrated circuit;

[0035] 11. Driver amplifier;

[0036] 12 Carrier amplifier;

[0037] 13 Peaking amplifier;

[0038] 14, 15 phase shifter;

[0039] 16 matching circuit;

[0040] 17 1st bias circuit;

[0041] 18. 2nd bias circuit;

[0042] 31 variable constant current output circuit;

[0043] 32, 32A resistor array;

[0044] 41 Subtraction circuit;

[0045] AMP1, AMP2, AMP3, AMP4 buffer amplifiers;

[0046] D11, D12, D21, D22, DR1, DR2, DD1, DD2 diodes;

[0047] Q1, Q2, Q11, Q21, QD1, QDD transistors;

[0048] Iref, Iref2 reference current output circuit;

[0049] Vref, Vref2 reference voltage output circuit;

[0050] RF-1, RF-2, …, RF-n resistance elements;

[0051] F-1, F-2, ..., Fn electronic fuse (E fuse);

[0052] S-1, S-2, …, Sn switches;

[0053] VR1, VR2 variable resistors. DETAILED DESCRIPTION

[0054] Hereinafter, the embodiment of the control circuit of the present invention is described in detail based on the accompanying drawings. In addition, the present invention is not limited by this embodiment. Each embodiment is an example, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed. After the second embodiment, the description of the matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects based on the same structure are not mentioned one by one in each embodiment.

[0055] <First Embodiment and Comparative Example>

[0056] Hereinafter, the first embodiment will be described. However, in order to facilitate understanding of the first embodiment, a comparative example will be described first.

[0057] (Comparative Example)

[0058] Figure 1 1 is a diagram showing a structure of a Doherty amplifier according to a comparative example. The Doherty amplifier 100 includes an input power distribution circuit 111 , a carrier amplifier 112 , a peak amplifier 113 , and an output power combining circuit 114 .

[0059] The input power distribution circuit 111 distributes the high-frequency input signal RFin input from the RF (Radio Frequency) input terminal 121 to two paths and outputs the signals. The high-frequency signal RF11, which is one output signal of the input power distribution circuit 111, is supplied to the gate of the FET (Field Effect Transistor) constituting the carrier amplifier 112 via the DC cutoff capacitor 122. The high-frequency signal RF12, which is another output signal of the input power distribution circuit 111, is supplied to the gate of the FET constituting the peak amplifier 113 via the DC cutoff capacitor 123.

[0060] The carrier amplifier 112 is a power amplifier using, for example, FET, and always amplifies the high-frequency signal RF11 input from the input power distribution circuit 111. A bias voltage Vg1 is applied to the gate of the FET constituting the carrier amplifier 112 from a DC power supply 124 via a choke coil 125. The bias voltage Vg1 is set to bias the carrier amplifier 112 in class AB (or class A or class B). In addition, a DC voltage (for example, +28 V) is applied to the drain of the FET constituting the carrier amplifier 112 from a DC power supply 128 via a choke coil 129.

[0061] Furthermore, the bias voltage Vg1 output from the DC power supply 124 is also supplied to the voltage offset circuit 126. The voltage offset circuit 126 offsets the bias voltage Vg1 by a predetermined voltage Voffset to generate a bias voltage Vg2 for the peak amplifier 113.

[0062] The peak amplifier 113 is a power amplifier using, for example, FET, and amplifies the peak value of the high-frequency signal RF12 input from the input power distribution circuit 111. A bias voltage Vg2 is applied to the gate of the FET constituting the peak amplifier 113 from the voltage shift circuit 126 via the choke 127. The bias voltage Vg2 is set to perform a C-class bias on the peak amplifier 113. In addition, a DC voltage (for example, +28 V) is applied to the drain of the FET constituting the peak amplifier 113 from the DC power supply 128 via the choke 130.

[0063] Here, the carrier amplifier 112 and the peak amplifier 113 use amplifiers having common elements related to devices such as wafer batches and manufacturing periods.

[0064] The high-frequency signal RF13 as the output signal of the carrier amplifier 112 is supplied to the output power synthesis circuit 114 via the DC cut capacitor 131. In addition, the high-frequency signal RF14 as the output signal of the peak amplifier 113 is supplied to the output power synthesis circuit 114 via the DC cut capacitor 132. The output power synthesis circuit 114 outputs a high-frequency output signal RFout obtained by synthesizing the high-frequency signal RF13 and the high-frequency signal RF14 from the output terminal 133.

[0065] As described above, in the Doherty amplifier 100, the bias voltage Vg1 for the carrier amplifier 112 is supplied from the DC power supply 124. On the other hand, the bias voltage Vg2 for the peak amplifier 113 is generated by the voltage offset circuit 126 by offsetting the bias voltage Vg1 by the voltage Voffset, and is supplied from the voltage offset circuit 126 to the gate of the FET constituting the peak amplifier 113.

[0066] As a feature of Doherty amplifier 100 , carrier amplifier 112 operates in class AB (or class A or class B), and peak amplifier 113 operates in class C. To cope with this operation, bias voltage Vg2 is set to a voltage lower than bias voltage Vg1 of carrier amplifier 112 by voltage Voffset.

[0067] When the high-frequency input signal RFin is small, the Doherty amplifier 100 operates only with the carrier amplifier 112 operating with the AB class bias. When the high-frequency input signal RFin increases, the peak amplifier 113 operating with the C class bias starts to operate. As the peak amplifier 113 starts to operate, the load impedance of the carrier amplifier 112 decreases, and the Doherty amplifier 100 transitions to an operation of generating a larger output power.

[0068] In this way, the amplification operation of the Doherty amplifier 100 is switched in the middle according to the level of the high-frequency input signal RFin. Therefore, the output power-gain characteristic and the output power-phase characteristic of the Doherty amplifier 100 change at the timing when the peak amplifier 113 starts to operate. This change causes distortion to the high-frequency output signal RFout, resulting in an increase in adjacent channel leakage power (ACP), that is, a deterioration in the adjacent channel leakage power ratio (ACLR), and an increase (deterioration) in the error vector magnitude (EVM). When the Doherty amplifier 100 is used, in order to suppress (eliminate) the distortion of the high-frequency output signal RFout, the following digital pre-distortion (DPD) technology is used, that is, a data table is used in which the distortion of the inverse characteristic of the distortion of the Doherty amplifier 100 is numerically added to the high-frequency input signal RFin in advance.

[0069] However, the Doherty amplifier 100 of the comparative example does not take into account the deviations in the output power-gain characteristics and output power-phase characteristics of the transistors of the carrier amplifier 112 and the peak amplifier 113 caused by the deviations in the action thresholds due to the individual differences in the transistors of the carrier amplifier 112 and the peak amplifier 113 .

[0070] For example, if the operating thresholds of the transistors constituting the carrier amplifier 112 and the transistors constituting the peak amplifier 113 are relatively different, the relative bias conditions are different even if the voltage Voffset is constant. Therefore, the level of the high-frequency input signal RFin at which the peak amplifier 113 starts to operate is shifted, resulting in deviations in the output power-gain characteristics and the output power-phase characteristics of the peak amplifier 113.

[0071] Figure 2 is a graph showing the input-output characteristics of a class AB amplifier. Figure 2In FIG. 14 , the horizontal axis is the input power Pin, and the vertical axis is the output power Pout. Line 141 is a line showing an example of the input-output characteristics of the AB class amplifier. Until the input power Pin reaches a certain level, the relationship between the input power and the output power is linear. If the input power Pin becomes larger and the transistor is saturated, the output power Pout reaches the peak (saturation). The gain of the AB class amplifier varies according to individual differences in the bias current (bias voltage) level of the transistor, the characteristics of the transistor, the input-output matching circuit, etc., for example, as shown by lines 142 to 143. This deviation can be suppressed by adjusting the bias voltage or bias current.

[0072] Figure 3 The input and output characteristics of the Class C amplifier are shown in Figure 1. Figure 3 In the figure, the horizontal axis is the input power Pin and the vertical axis is the output power Pout. Line 151 is a line showing an example of the input-output characteristics of a class C amplifier. The class C amplifier does not operate until the input power Pin reaches a certain level. If the input power Pin reaches a certain level and the class C amplifier starts to operate, the gain of the class C amplifier also increases with the increase in the input power Pin. Finally, similar to the class AB amplifier, if the input power Pin increases and the transistor is saturated, the output power Pout reaches its peak (saturation). The gain of the class C amplifier deviates according to individual differences in the bias current (bias voltage) level of the transistor, the characteristics of the transistor, the input-output matching circuit, etc., for example, as shown by lines 152 to 153.

[0073] The level of the high-frequency input signal RFin at which the class C amplifier starts to operate depends on the bias current (bias voltage) level of the transistor and the high-frequency signal amplitude in the base (gate) of the transistor, and there are deviations due to individual differences in the bias current level and input matching circuits. The main causes of the deviations in the characteristics of the carrier amplifier 112 and the peak amplifier 113 are different, so they are not necessarily strongly correlated, and there are cases where they vary separately.

[0074] When the Doherty amplifier 100 is used in a mobile phone base station, for example, there is a timing dedicated to training the appropriate setting table in order to change the setting of the digital predistortion to reduce distortion, so the above-mentioned deviation does not become an essential problem.

[0075] However, when the Doherty amplifier 100 is used in a wireless communication terminal device such as a mobile phone device, there is no dedicated training timing, and it is difficult to suppress the deviation of characteristics caused by individual differences. Although it is also conceivable to create a digital predistortion table for each terminal before the factory shipment of the wireless communication terminal device to suppress the deviation of characteristics caused by individual differences, there is a problem of increased testing costs when shipping the wireless communication terminal device. Therefore, it is desired to suppress the deviation of the output power-gain characteristic and the output power-phase characteristic caused by individual differences.

[0076] Figure 4 It is a circuit diagram showing the concept of the present invention.

[0077] Relative to Figure 1 The Doherty amplifier of the comparative example shown in FIG. Figure 4 In the structure of FIG. 1 , in order to make the operation of the peak amplifier 13 reliable, the second bias circuit 18 is driven via the offset circuit 30 with a fuse adjustment function based on the voltage of the reference voltage output circuit Vref. By adjusting the voltage value or the current value by the offset circuit 30 with a fuse adjustment function, the peak amplifier 13 can be operated reliably.

[0078] (First embodiment)

[0079] Figure 5 It is a diagram showing a circuit configuration of a power amplifier module according to the first embodiment.

[0080] The power amplifier module 1 can be implemented by a hybrid IC (also referred to as a module) in which a plurality of components (semiconductor integrated circuits, etc.) are mounted on a substrate, but the present disclosure is not limited thereto. The power amplifier module 1 is used in wireless communication terminal devices such as mobile phones to transmit various signals such as voice and data to a base station.

[0081] The power amplifier module 1 includes a first integrated circuit (first IC chip) 2 and a second integrated circuit (second IC chip) 3. The first integrated circuit 2 is formed on a compound semiconductor substrate (e.g., GaAs substrate), but the present disclosure is not limited thereto. The second integrated circuit 3 is formed on a semiconductor substrate (e.g., Si substrate), but the present disclosure is not limited thereto.

[0082] The second integrated circuit 3 corresponds to an example of the “control circuit” in the present disclosure.

[0083] The first integrated circuit 2 includes a driver amplifier 11 at the initial stage (driver stage) and a carrier amplifier 12 and a peak amplifier 13 at the final stage (power stage). The carrier amplifier 12 and the peak amplifier 13 constitute a Doherty amplifier.

[0084] The carrier amplifier 12 includes a transistor Q1. The peak amplifier 13 includes a transistor Q2. The transistor Q1 is biased in class AB (or class A or class B) by a first bias circuit 17. The transistor Q2 is biased in class C by a second bias circuit 18.

[0085] Hereinafter, the first bias circuit 17 and the carrier amplifier 12 may be collectively referred to as a “carrier amplifier system.” Also, the second bias circuit 18 and the peak amplifier 13 may be collectively referred to as a “peak amplifier system.”

[0086] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited to this. The bipolar transistor is exemplified by a heterojunction bipolar transistor (HBT), but the present disclosure is not limited to this. The transistor may also be a field effect transistor (FET), for example. The transistor may also be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. The so-called unit transistor refers to the minimum structure that constitutes a transistor.

[0087] The high-frequency input signal RFin is input to the driver amplifier 11 via the terminal 1a. The driver amplifier 11 outputs a high-frequency signal RF1 obtained by amplifying the high-frequency input signal RFin.

[0088] One end of a DC cut capacitor C1 and one end of a phase shifter 14 are electrically connected to the output terminal of the driver amplifier 11. The other end of the DC cut capacitor C1 is electrically connected to the base of the transistor Q1. The high frequency signal RF1 is supplied to the base of the transistor Q1 via the DC cut capacitor C1.

[0089] The phase shifter 14 outputs a high-frequency signal RF2 whose phase is advanced or delayed by approximately 90 degrees from the phase of the high-frequency signal RF1. In the present disclosure, approximately 90 degrees is defined as 90 degrees ± 20 degrees.

[0090] The other end of the phase shifter 14 is electrically connected to the base of the transistor Q2 via the DC cut capacitor C2. The high-frequency signal RF2 is supplied to the base of the transistor Q2 via the DC cut capacitor C2.

[0091] The emitter of the transistor Q1 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto. The collector of the transistor Q1 is electrically connected to a power supply potential Vcc via a choke inductor L. The transistor Q1 outputs a high-frequency signal RF3 obtained by amplifying the high-frequency signal RF1 from the collector.

[0092] One end of the phase shifter 15 is electrically connected to the collector of the transistor Q1 , and the other end of the phase shifter 15 is electrically connected to the collector of the transistor Q2 .

[0093] The phase shifter 15 outputs a high-frequency signal RF4 in which the phase of the high-frequency signal RF3 is advanced or delayed by approximately 90 degrees.

[0094] When the phase shifter 14 advances the phase of the high frequency signal RF1 by approximately 90 degrees, the phase shifter 15 advances the phase of the high frequency signal RF3 by approximately 90 degrees. When the phase shifter 14 lags the phase of the high frequency signal RF1 by approximately 90 degrees, the phase shifter 15 lags the phase of the high frequency signal RF3 by 90 degrees.

[0095] The emitter of the transistor Q2 is electrically connected to a reference potential. The transistor Q2 outputs a high-frequency signal RF5 obtained by amplifying the high-frequency signal RF2 from its collector.

[0096] The other end of the phase shifter 15 and the collector of the transistor Q2 are electrically connected to the terminal 1b via the matching circuit 16. The high-frequency signal RF4 and the high-frequency signal RF5 are superimposed and outputted from the terminal 1b via the matching circuit 16 as a high-frequency output signal RFout.

[0097] When the high frequency input signal RFin is small, the carrier amplifier 12 (transistor Q1) operates, but the peak amplifier 13 (transistor Q2) does not operate. In this case, the load impedance of the carrier amplifier 12 becomes the impedance RL of the matching circuit 16. This is because the impedance of the phase shifter 15 does not change.

[0098] If the high-frequency input signal RFin increases, the carrier amplifier 12 (transistor Q1) approaches saturation, and the peak amplifier 13 (transistor Q2) starts to operate. In this case, the phase of the high-frequency signal RF5 applied from the peak amplifier 13 to the matching circuit 16 becomes the same as the phase of the high-frequency signal RF4 applied from the carrier amplifier 12 to the matching circuit 16 via the phase shifter 15. At this time, the signal amplitude in the collector of the transistor Q2 increases, so the load impedance (impedance of the matching circuit 16) increases equivalently from the perspective of the peak amplifier 13. This equivalent change in impedance is transmitted to the carrier amplifier 12 via the phase shifter 15. On the contrary, the load impedance decreases from the perspective of the carrier amplifier 12, so the saturation power (maximum power) of the carrier amplifier 12 increases.

[0099] Finally, in a state where the peak amplifier 13 is saturated, the load impedance (impedance of the matching circuit 16 ) seen from the peak amplifier 13 is 2RL, and the load impedance seen from the carrier amplifier 12 is RL / 2.

[0100] By this operation, once the carrier amplifier 12 approaches saturation, the load impedance appears to decrease, and a larger output can be delivered. Since the carrier amplifier 12 operates near saturation, it is possible to achieve high efficiency in a wide power range.

[0101] Figure 6 as well as Figure 7 is a diagram showing the characteristics of the Doherty amplifier. In detail, Figure 6 : is a graph showing the relationship between the output power and efficiency of the Doherty amplifier. Figure 7 : is a graph showing the relationship between the output power and the gain of the Doherty amplifier.

[0102] exist Figure 6 In FIG. 1 , the horizontal axis is the output power Pout and the vertical axis is the efficiency. Arrow 161 indicates the range of the output power Pout in which the carrier amplifier 12 operates. Arrow 162 indicates the range of the output power Pout in which the peak amplifier 13 operates. As shown by line 163, a high efficiency can be achieved from the level of the output power Pout in which the carrier amplifier 12 operates near saturation to the level in which the load impedance becomes half and saturates.

[0103] exist Figure 7 In FIG. 1 , the horizontal axis represents output power Pout and the vertical axis represents gain. As shown by line 171 , in region 172 where the peak amplifier 13 starts to operate, the nonlinearity of the Doherty amplifier is particularly significant.

[0104] In this way, the amplification operation of the Doherty amplifier is switched in the region 172, which is the timing at which the peak amplifier 13 starts to operate. Therefore, the output power-gain characteristic and the output power-phase characteristic of the Doherty amplifier change in the region 172. This change causes distortion to the high-frequency output signal RFout, resulting in an increase in adjacent channel leakage power (ACP), that is, a deterioration in the adjacent channel leakage power ratio (ACLR), and an increase (deterioration) in the error vector magnitude (EVM).

[0105] As previously mentioned, in the digital pre-distortion (DPD) technology, the digital signal processing unit of the transmitting circuit generates a distortion of the inverse characteristic of the distortion of the Doherty amplifier in region 172 and adds it to the high-frequency input signal RFin, thereby suppressing the deterioration of ACLR and EVM caused by the distortion of the high-frequency output signal RFout. The distortion of the Doherty amplifier is prone to change depending on the individual differences of the bipolar transistors included in the first integrated circuit 2. For example, if there are individual differences between transistor Q1 and transistor Q2, and the action thresholds are relatively different, then the relative bias conditions are different. Therefore, the timing at which the peak amplifier 13 (transistor Q2) starts to operate is one before and one after. That is, region 172 is Figure 7 Suppress the change of the distortion of the Doherty amplifier, that is, suppress the area 172 to Figure 7 The left-right movement in the Doherty amplifier is important for applying the Doherty amplifier to a wireless communication terminal device.

[0106] Refer again Figure 5 The bias of the carrier amplifier 12 and the peak amplifier 13 will be described. The second integrated circuit 3 outputs the current I1 to the first bias circuit 17 and outputs the voltage v2 to the second bias circuit 18 .

[0107] Generation of the current I1 will be described. The reference voltage output circuit Vref in the second integrated circuit 3 outputs the reference voltage V21 to the reference current output circuit Iref.

[0108] The reference current output circuit Iref outputs a reference current I21 corresponding to the reference voltage V21 to the variable constant current output circuit 31. The variable constant current output circuit 31 outputs a current I1 proportional to the reference current I21 to the terminal B1 of the first integrated circuit 2.

[0109] The first integrated circuit 2 includes a resistor Rp1 and a first bias circuit 17. The first bias circuit 17 includes diodes D11 and D12, a transistor Q11, and a resistor Rbias1. The diodes D11 and D12 are each exemplified as diodes in which the base and collector of the HBT are electrically connected, that is, diode-connected.

[0110] One end of the resistor Rp1 is electrically connected to the terminal B1. The other end of the resistor Rp1 is electrically connected to the anode of the diode D11. The cathode of the diode D11 is electrically connected to the anode of the diode D12. The cathode of the diode D12 is electrically connected to the reference potential. The series connection circuit of the diodes D11 and D12 generates a certain voltage. For example, if it is desired that the diodes D11 and D12 each generate a voltage of about 1.3V (volts), the series connection circuit of the diodes D11 and D12 should generate a voltage of about 2.6V.

[0111] The voltage of the series connection circuit of diodes D11 and D12 is applied to the base of transistor Q11. The collector of transistor Q11 is electrically connected to the power supply potential Vcbias via terminal CQ11 and terminal 1c. The emitter of transistor Q11 is electrically connected to the base of transistor Q1 via resistor Rbias1. In other words, transistor Q11 and resistor Rbias1 are emitter-follower connected. The base current of transistor Q1 is determined based on the voltage applied to the base of transistor Q11.

[0112] The generation of voltage V2 is described. The buffer amplifier AMP1 in the second integrated circuit 3 outputs a voltage V22 based on the reference voltage V21 to one end of the variable resistor VR1. The example voltage V22 is the same as the reference voltage V21, but the present disclosure is not limited to this. The series circuit of the variable resistor VR1 and the resistor array 32 divides the voltage V22 by resistance and outputs a voltage V23.

[0113] The resistor array 32 includes n (n is a natural number) resistor elements RF-1, RF-2, ..., RF-n and n electronic fuses (Efuse) F-1, F-2, ..., Fn. One ends of the resistor elements RF-1, RF-2, ..., RF-n are electrically connected to each other and to the other end of the variable resistor VR1. The other ends of the resistor elements RF-1, RF-2, ..., RF-n are electrically connected to each other via the electronic fuses F-1, F-2, ..., Fn, and to the reference potential. In other words, the resistor elements RF-1, RF-2, ..., RF-n are connected in parallel.

[0114] The resistance values ​​of the resistance elements RF-1, RF-2, ..., RF-n may be the same or different. Hereinafter, the resistance elements RF-1, RF-2, ..., RF-n may be collectively referred to as resistance element RF.

[0115] The electronic fuses F-1, F-2, ..., Fn are electrically connected to the n terminals 3a-1, 3a-2, ..., 3a-n, respectively. By selectively applying a voltage or current to the terminals 3a-1, 3a-2, ..., 3a-n, the electronic fuses F-1, F-2, ..., Fn can be selectively blown. The resistance value of the resistor array 32 can be changed by selectively blowing the electronic fuses F-1, F-2, ..., Fn. For example, if the electronic fuse F-1 is blown, the resistor element RF-1 becomes irrelevant to the resistance value of the resistor array 32, so the resistance value of the resistor array 32 becomes larger.

[0116] Hereinafter, the electronic fuses F- 1 , F- 2 , . . . , Fn may be collectively referred to as an electronic fuse F.

[0117] The electronic fuse F is an irreversible element that will not be restored if it is blown. The resistance value of the resistor array 32 is the smallest at the beginning (when none of the electronic fuses F is blown), and becomes irreversibly larger as the electronic fuses F are blown. In other words, the resistance value of the resistor array 32 can be irreversibly adjusted.

[0118] Figure 8 It is a diagram showing another example of a resistor array.

[0119] The resistor array 32A includes n resistor elements RF-1, RF-2, ..., RF-n and n switches S-1, S-2, ..., Sn. One ends of the resistor elements RF-1, RF-2, ..., RF-n are electrically connected to each other. The other ends of the resistor elements RF-1, RF-2, ..., RF-n are electrically connected to each other via switches S-1, S-2, ..., Sn, respectively.

[0120] The non-volatile memory 51 stores n-bit data and outputs a signal of n-bit width to switches S-1, S-2, ..., Sn. The switches S-1, S-2, ..., Sn are each turned on or off according to the supplied signal. The resistance value of the resistor array 32A can be changed by selectively turning on or off the switches S-1, S-2, ..., Sn. For example, if the switch S-1 is turned off, the resistor element RF-1 becomes irrelevant to the resistance value of the resistor array 32A, so the resistance value of the resistor array 32A increases. By writing data to the non-volatile memory 51, the on or off of the switches S-1, S-2, ..., Sn can be switched, and the resistance value of the resistor array 32A can be made variable.

[0121] The nonvolatile memory 51 is exemplified by a one-time ROM (Read Only Memory). A one-time ROM is an irreversible element that cannot be rewritten once data is written. That is, the resistance value of the resistor array 32A is irreversible.

[0122] The resistor arrays 32 and 32A correspond to an example of the “resistance” in the present disclosure.

[0123] In addition, the variable resistor VR1 is shown as Figure 8 The variable resistor VR1 can be realized by using EPROM (Erasable Programmable Read Only Memory), flash memory (registered trademark), etc. as the nonvolatile memory 51 so that the resistance value can be reversibly changed.

[0124] Refer again Figure 5 The voltage V23 can be adjusted by adjusting the resistance value of the resistor array 32 (and the resistance value of the variable resistor VR1).

[0125] When the resistance value of the variable resistor VR1 is maintained constant, the voltage V23 increases as the resistance value of the resistor array 32 increases. That is, the voltage V23 is a voltage obtained by adjusting the voltage V22 according to the resistance value of the resistor array 32.

[0126] The buffer amplifier AMP2 outputs the voltage V2 based on the voltage V23 to the terminal B2 of the first integrated circuit 2. The example voltage V2 is the same as the voltage V23, but the present disclosure is not limited to this. The voltage V23 can be adjusted by adjusting the resistance value of the resistor array 32 (and the resistance value of the variable resistor VR1). Therefore, the voltage V2 can be adjusted by adjusting the resistance value of the resistor array 32 (and the resistance value of the variable resistor VR1).

[0127] The first integrated circuit 2 includes a resistor Rp2 and a second bias circuit 18. The second bias circuit 18 includes diodes D21 and D22, a transistor Q21, and a resistor Rbias2. The diodes D21 and D22 are each an example of a diode-connected HBT.

[0128] One end of the resistor Rp2 is electrically connected to the terminal B2. The other end of the resistor Rp2 is electrically connected to the anode of the diode D21. The cathode of the diode D21 is electrically connected to the anode of the diode D22. The cathode of the diode D22 is electrically connected to the reference potential.

[0129] The anode of the diode D21 is electrically connected to the base of the transistor Q21. The collector of the transistor Q21 is electrically connected to the power supply potential Vcbias via the terminal CQ21 and the terminal 1c. The emitter of the transistor Q21 is electrically connected to the base of the transistor Q2 via the resistor Rbias2. That is, the transistor Q21 and the resistor Rbias2 are emitter-follower connected.

[0130] The voltage value of the voltage V2 is set to a voltage less than twice (for example, about 2.6 V) the turn-on voltage (for example, about 1.3 V) of each of the diode-connected HBTs, namely the diodes D21 and D22, and is exemplified as about 2.1 V to 2.2 V. Even if the voltage V2 is applied to the terminal B2, since the voltage V2 is less than the turn-on voltage of the series connection circuit of the diodes D21 and D22, no current flows through the diodes D21 and D22. Similarly, the transistors Q21 and Q2 do not operate.

[0131] If a high-frequency input signal RFin is input, the current flowing through the transistor increases as the input RF signal increases. At this time, under direct current, a self-bias effect that reduces the turn-on voltage of the base-emitter diode will occur. If the turn-on threshold voltage of the diode (pn junction between the base and the emitter) of transistor Q2 and transistor Q21 begins to decrease due to this self-bias effect, transistors Q2 and Q21 begin to operate. As a result, current begins to flow in the path of terminal B2 → resistor Rp2 → transistor Q21 → transistor Q2. The capacitor CB2 electrically connected between the emitter of transistor Q21 and the other end of the phase shifter 14 has the following function: the high-frequency signal RF2 is efficiently applied to the emitter of transistor Q21, promoting the decrease of the turn-on threshold voltage of transistor Q21. In addition, it is preferred to provide capacitor CB2, but it is not necessary and may not be provided.

[0132] The turn-on threshold voltage of the diode of each transistor varies according to the manufacturing process. Even transistors on different chips on the same wafer have different turn-on threshold voltages, and even transistors Q1 and Q2 on the same chip on the same wafer have deviations. The power amplifier module 1 suppresses this deviation by selectively blowing the electronic fuse F described above.

[0133] Fig. 9 It is a diagram showing a first adjustment process of the power amplifier module according to the first embodiment. Fig. 9 The illustrated process is performed by a semiconductor inspection apparatus (semiconductor tester) on a compound semiconductor wafer before the first integrated circuit 2 is diced.

[0134] A first integrated circuit 2 is selected from a plurality of first integrated circuits 2 on a wafer, and the coordinates on the wafer are recorded (step S100). The coordinates on the wafer are an example of identification information for identifying the selected first integrated circuit 2, and other information may be used as long as the selected first integrated circuit 2 can be identified.

[0135] A given potential (or a given current) is applied to terminals B1 and B2 (step S102). The given potential is exemplified as a predetermined potential above 2.6V, but the present disclosure is not limited to this. At this time, if the transistors and diodes included in the first integrated circuit 2 have no deviation (individual difference), then the collector current of transistor Q11 and the collector current of transistor Q21 become the same, and the collector current of transistor Q1 and the collector current of transistor Q2 become the same. However, in reality, the transistors and diodes included in the first integrated circuit 2 have deviations, so the collector current of transistor Q11 and the collector current of transistor Q21 will not become the same, and the collector current of transistor Q1 and the collector current of transistor Q2 will not become the same.

[0136] The collector current values ​​of transistors Q1 and Q2 (or transistors Q11 and Q21) are measured (step S104). Ultimately, the collector currents of transistors Q1 and Q2 directly affect the high-frequency output signal RFout, so it is preferred to measure the collector current values ​​of transistors Q1 and Q2. However, as long as the collector current values ​​of transistors Q1 and Q2 are greater than the maximum current value that can be measured by the semiconductor tester, the collector current values ​​of transistors Q11 and Q21 may also be measured.

[0137] When the collectors of transistors Q11 and Q21 are electrically connected to one pad in order to reduce the chip area, the collector current value of transistor Q11 and the collector current value of transistor Q21 can be measured in a time-division manner. In addition, if the collectors of transistors Q11 and Q21 are connected to other circuits such as a bias circuit for biasing the driver amplifier 11, the measurement accuracy will decrease. Therefore, if Figure 5 As shown, it is preferred that the collectors of the transistors Q11 and Q21 are not connected to other circuits.

[0138] The two measured collector current values ​​are recorded in association with the coordinates of the first integrated circuit 2 (step S106).

[0139] The voltage V2 at which the difference between the collector current value of transistor Q1 and the collector current value of transistor Q2 is minimized when transistor Q1 is biased at class AB (or class A or class B) and transistor Q2 is biased at class C is calculated based on the diode characteristics. The calculated voltage V2 is recorded in association with the coordinates of the first integrated circuit 2 (step S108).

[0140] Steps S100 to S108 are performed on all the first integrated circuits 2 on the compound semiconductor wafer.

[0141] A plurality of first integrated circuits 2 are cut out from a compound semiconductor wafer and mounted on a plurality of substrates, respectively, to assemble a plurality of power amplifier modules 1 (step S110 ).

[0142] One or more electronic fuses F are blown so that the buffer amplifier AMP2 outputs the voltage V2 calculated in step S108 for each of the plurality of power amplifier modules 1 (step S112). If the electronic fuse F is not adjusted, the variable resistor VR1 is adjusted.

[0143] The first adjustment process can suppress variations in the operating threshold of the diode (pn junction of the transistor) of the power amplifier module 1 .

[0144] Fig.10 It is a diagram showing a second adjustment process of the power amplifier module according to the first embodiment. Fig.10 The illustrated process exemplifies the process performed by the power amplifier module inspection apparatus on the assembled power amplifier module 1 .

[0145] The first integrated circuit 2 and the second integrated circuit 3 are mounted on a substrate to assemble the power amplifier module 1 (step S200 ).

[0146] The switch SW2 is turned off. Instead of turning off the switch SW2, the variable constant current output circuit 31 may be turned off. In addition, the switch SW1 is connected to the terminal B1 side (step S202). As a result, the transistors Q11 and Q1 are activated.

[0147] The collector current value of the transistor Q1 (or Q11) is measured (step S204).

[0148] The switch SW2 is turned off. Furthermore, the switch SW1 is connected to the terminal B2 side (step S206). As a result, the transistors Q21 and Q2 are activated.

[0149] The collector current value of the transistor Q2 (or Q21) is measured (step S208).

[0150] The difference Δicc between the collector current value of the transistor Q1 (or Q11) and the collector current value of the transistor Q2 (or Q21) is obtained (step S210).

[0151] It is determined whether the absolute value Abs(Δicc) of the difference Δicc is less than the predetermined tolerance ε (step S212). If it is determined that the absolute value Abs(Δicc) is not less than the tolerance ε (No in step S212), the process proceeds to step S214. If it is determined that the absolute value Abs(Δicc) is less than the tolerance ε (Yes in step S212), the process proceeds to step S216.

[0152] If it is determined that the absolute value Abs(Δicc) is not less than the tolerance ε (No in step S212 ), one or more electronic fuses F are blown (step S214 ), and the process proceeds to step S202 .

[0153] When it is determined that the absolute value Abs(Δicc) is smaller than the tolerance ε (Yes in step S212 ), the switch SW2 is turned on, the switch SW1 is connected to the terminal B2 side (step S216 ), and the process ends.

[0154] The second adjustment process, like the previous first adjustment process, can suppress the deviation of the action threshold of the diode (pn junction of the transistor) of the power amplifier module 1. Furthermore, compared with the previous first adjustment process, the second adjustment process does not need to manage the coordinates of the first integrated circuit 2, the history of wafer evaluation, etc., and can be executed at the same time as the good product test of the power amplifier module 1.

[0155] Fig.11 It is a diagram showing the third adjustment process of the power amplifier module according to the first embodiment. Fig.11 The illustrated process exemplifies the process performed by the power amplifier module inspection apparatus on the assembled power amplifier module 1 .

[0156] The first integrated circuit 2 and the second integrated circuit 3 are mounted on a substrate to assemble the power amplifier module 1 (step S300 ).

[0157] The switch SW2 is turned off. Instead of turning off the switch SW2, the variable constant current output circuit 31 may be turned off. In addition, the switch SW1 is connected to the terminal B2 side (step S302). Thus, the transistors Q11 and Q1 are stopped, and the transistors Q21 and Q2 can operate.

[0158] A predetermined first high frequency signal is input to the terminal 1a (step S304). The power of the first high frequency signal is set, for example, at a level at which the peak amplifier 13 starts a Class C operation (see Figure 3 ) is located near the

[0159] The collector current value of the transistor Q2 (or Q21) is measured (step S306).

[0160] A predetermined second high frequency signal is input to the terminal 1a (step S308). The power of the second high frequency signal is set, for example, so that the peak amplifier 13 starts the Class C operation (see Figure 3 ) is located near the

[0161] The collector current value of the transistor Q2 (or Q21) is measured (step S310).

[0162] In addition, steps S308 and S310 are used to improve the determination accuracy and may be omitted.

[0163] It is determined whether the collector current value measured in steps S306 and S310 is within a predetermined setting range (step S312). If it is determined that the collector current value is not within the setting range (No in step S312), the process proceeds to step S314. If it is determined that the collector current value is within the setting range (Yes in step S312), the process proceeds to step S316.

[0164] If it is determined that the collector current value is not within the set range (No in step S312), one or more electronic fuses F are blown (step S314), and the process proceeds to step S302.

[0165] When it is determined that the collector current value is within the set range (Yes in step S312 ), the switch SW2 is turned on, the switch SW1 is connected to the terminal B2 side (step S316 ), and the process ends.

[0166] The first and second adjustment processes above only suppress variations in the operating threshold of the diode (pn junction of the transistor), whereas the third adjustment process can suppress the influence of individual differences in the elements including the phase shifters 14 and 15 and the matching circuit 16 .

[0167] Figure 5 The circuit structure of the power amplifier module 1 shown can correspond to the first to third adjustment processes mentioned above.

[0168] As described above, the power amplifier module 1 can suppress the deviation of the characteristics of the peak amplifier system that performs the C-class operation, which is easily affected by the individual difference in the Doherty amplifier, by the electronic fuse F. The power amplifier module 1 can be shipped to the wireless communication terminal device manufacturer in a state where the deviation of the characteristics of the peak amplifier system is suppressed. Therefore, the power amplifier module 1 can suppress the test cost for the wireless communication terminal device manufacturer to apply digital pre-distortion to the wireless communication terminal device.

[0169] <Second Embodiment>

[0170] Fig.12 : is a diagram showing a circuit configuration of a power amplifier module according to the second embodiment.

[0171] Among the components of the power amplifier module 1A of the second embodiment, the components that are the same as those of the first embodiment are denoted by the same reference numerals and their description is omitted.

[0172] The power amplifier module 1A includes a first integrated circuit 2A and a second integrated circuit 3A.

[0173] The first integrated circuit 2A is similar to the first integrated circuit 2 of the first embodiment (see Figure 5 ), the capacitor CB2 is not included between the emitter of the transistor Q21 and the other end of the phase shifter 14. The capacitor CB2 has the function of efficiently applying the high-frequency signal RF2 to the emitter of the transistor Q21 and promoting the reduction of the on-threshold voltage of the transistor Q21, so it is preferably provided, but it is not essential and may not be provided.

[0174] The second integrated circuit 3A is similar to the second integrated circuit 3 of the first embodiment (see Figure 5 ) compared to the reference voltage output circuit Vref2.

[0175] The reference voltage output circuit Vref2 outputs a reference voltage V31 to the buffer amplifier AMP1. The buffer amplifier AMP1 outputs a voltage V22 based on the reference voltage V31 to one end of the variable resistor VR1.

[0176] The second integrated circuit 3 of the first embodiment generates the voltage V2 based on the reference voltage V21 output from the reference voltage output circuit Vref. On the other hand, the second integrated circuit 3A of the second embodiment generates the voltage V2 based on the reference voltage V31 output from the reference voltage output circuit Vref2. The reason is as follows.

[0177] The diode (pn junction) characteristics of the HBT are temperature dependent. For example, in a carrier amplifier system, the series connection of diodes D11 and D12 has a temperature characteristic that the voltage decreases when the temperature rises and increases when the temperature decreases. Diodes D11 and D12 can suppress the temperature characteristics of transistors Q11 and Q1 based on this temperature characteristic.

[0178] On the other hand, in the peak amplification system, no current flows until a high-frequency input signal RFin of a certain level is input. In particular, the diodes D21 and D22 are provided to set the conditions to be the same as those of the carrier amplification system during testing, and no current flows during the actual amplification operation. Therefore, the diodes D21 and D22 cannot suppress the temperature characteristics of the transistors Q21 and Q2.

[0179] Therefore, the reference voltage output circuit Vref2 is set to have a characteristic that cancels the temperature characteristics of the transistors Q21 and Q2. Specifically, the reference voltage output circuit Vref2 is set to have a negative temperature dependency such that the reference voltage V31 decreases when the temperature rises and increases when the temperature drops. Thus, the reference voltage output circuit Vref2 can suppress the temperature characteristics of the transistors Q21 and Q2.

[0180] As described above, the power amplifier module 1A, like the power amplifier module 1, can suppress the deviation of the characteristics of the peak amplifier system performing the C-class operation, which is easily affected by individual differences even in the Doherty amplifier, by the electronic fuse F. Furthermore, the power amplifier module 1A can also suppress the characteristic variation based on the temperature of the peak amplifier system.

[0181] <Third Embodiment>

[0182] Fig.13 It is a diagram showing a circuit configuration of a power amplifier module according to a third embodiment.

[0183] Among the components of the power amplifier module 1B of the third embodiment, the components that are the same as those of the first or second embodiment are denoted by the same reference numerals and their description is omitted.

[0184] The power amplifier module 1B includes a first integrated circuit 2B and a second integrated circuit 3B.

[0185] The first integrated circuit 2B is similar to the first integrated circuit 2 of the first embodiment (see Figure 5 ) and further include diodes DR1 and DR2. The diodes DR1 and DR2 are each exemplified as diodes in which the HBT is diode-connected. The cathode of the diode DR1 is electrically connected to the anode of the diode DR2.

[0186] The diodes DR1 and DR2 correspond to an example of the “plurality of diodes” in the present disclosure.

[0187] Furthermore, the first integrated circuit 2B does not include the capacitor CB2 as compared to the first integrated circuit 2. The capacitor CB2 is preferably provided to efficiently apply the high-frequency signal RF2 to the emitter of the transistor Q21 and promote the reduction of the on-threshold voltage of the transistor Q21, but is not necessarily provided and may be omitted.

[0188] In addition, the first integrated circuit 2B does not include the diodes D21 and D22 compared to the first integrated circuit 2. In the first embodiment, the diodes D21 and D22 are provided to set the conditions to be the same as those of the carrier amplification system during the test, and no current flows during the actual amplification operation. Therefore, the diodes D21 and D22 are omitted in the first integrated circuit 2B.

[0189] The second integrated circuit 3B is similar to the second integrated circuit 3 of the first embodiment (see Figure 5 ) also includes buffer amplifiers AMP3 and AMP4, a variable resistor VR2, a resistor Rcont, a switch SW3, a reference current output circuit Iref2 and a subtraction circuit 41.

[0190] The reference current output circuit Iref2 corresponds to an example of the “constant current output circuit” of the present disclosure.

[0191] The buffer amplifier AMP3 outputs a voltage V42 based on the reference voltage V21 to one end of the variable resistor VR2. The voltage V42 is illustrated to be the same as the reference voltage V21, but the present disclosure is not limited to this. The series circuit of the variable resistor VR2 and the resistor Rcont divides the voltage V42 by resistance and outputs a voltage V43. The buffer amplifier AMP4 outputs a voltage Voffset based on the voltage V43. The voltage Voffset is illustrated to be the same as the voltage V43, but the present disclosure is not limited to this. The voltage Voffset is equivalent to the difference voltage between the AB class (or, A class or B class) bias driving the carrier amplifier 12 and the C class bias driving the peak amplifier 13. The voltage Voffset is a voltage corresponding to the reference voltage V21.

[0192] The reference current output circuit Iref2 outputs a current I41 corresponding to the voltage V41 to the anode of the diode DR1. The series connection circuit of the diodes DR1 and DR2 generates a certain voltage V44. For example, if it is desired that the diodes DR1 and DR2 each generate a voltage of about 1.3V, the series connection circuit of the diodes DR1 and DR2 generates a voltage of about 2.6V.

[0193] The subtraction circuit 41 outputs a voltage V2 which is a difference between the voltage V44 and the voltage Voffset to the terminal B2 of the first integrated circuit 2B. The subtraction circuit 41 is exemplified by a differential amplifier using an operational amplifier 41a.

[0194] The voltage V44 is input to the non-inverting input terminal of the operational amplifier 41a via the resistor 41b. The non-inverting input terminal of the operational amplifier 41a is electrically connected to the reference potential via the resistor 41c. The voltage Voffset is input to the inverting input terminal of the operational amplifier 41a via the resistor 41d. The inverting input terminal of the operational amplifier 41a is electrically connected to the output terminal of the operational amplifier 41a via the resistor 41e.

[0195] The resistance value of resistor 41d is set to R 1 , set the resistance value of resistor 41e to R 2 , set the resistance value of resistor 41b to R 3 , set the resistance value of resistor 41c to R 4 If R 1 =R 3 And R 2 =R 4 , then the voltage V2 is expressed by the following formula (1).

[0196] V2=R 2 / R 1 (V44-Voffset)…(1)

[0197] That is, the gain of the subtraction circuit 41 becomes R 2 / R 1 The subtraction circuit 41 can adjust the resistance R 1 To R 4 The voltage V2 is thereby adjusted.

[0198] The power amplifier module 1A of the second embodiment has a reference voltage output circuit Vref2 having temperature characteristics, thereby suppressing the temperature characteristics of the transistors Q21 and Q2. On the other hand, the power amplifier module 1B of this embodiment has diodes DR1 and DR2 in the first integrated circuit 2B, and supplies a current I41 to the diodes DR1 and DR2 so that a voltage of the diode 2 is generated. The diodes DR1 and DR2 and the diodes D11 and D12 are formed in the first integrated circuit 2B. Therefore, it can be expected that the voltage of the diodes DR1 and DR2 is the same as the voltage of the diodes D11 and D12.

[0199] Just as the diodes D11 and D12 have temperature characteristics such that the voltage decreases when the temperature increases and increases when the temperature decreases, the diodes DR1 and DR2 also have temperature characteristics such that the voltage decreases when the temperature increases and increases when the temperature decreases.

[0200] The current value of the current I41 is a current value corresponding to the voltage adjusted by the reference voltage V21 using the variable resistor VR1 and the resistor voltage divider circuit of the resistor array 32. The voltage value of the voltage Voffset is a voltage value adjusted by the reference voltage V21 using the buffer amplifier AMP3, the resistor voltage divider circuit of the variable resistor VR2 and the resistor Rcont, and the buffer amplifier AMP4.

[0201] When the second and third adjustment processes described in the first embodiment are applied to the power amplifier module 1B, the voltage Voffset is terminated by closing (turning on) the switch SW3, and the subtraction circuit 41 operates as a buffer amplifier. In this case, the voltage V2 becomes the same as the voltage of the diodes DR1 and DR2, that is, the voltage of the diodes D11 and D12. As a result, the power amplifier module 1B can operate the peak amplification system in the same manner as the carrier amplification system, and thus the second and third adjustment processes can be applied.

[0202] As described above, the power amplifier module 1B, like the power amplifier module 1, can suppress the deviation of the characteristics of the peak amplification system performing the C-class operation, which is easily affected by individual differences even in the Doherty amplifier, by the electronic fuse F. Furthermore, the power amplifier module 1B can suppress the characteristic variation due to temperature more accurately than the power amplifier module 1A.

[0203] <Fourth Implementation Method>

[0204] Fig.14 It is a diagram showing a circuit configuration of a power amplifier module according to a fourth embodiment.

[0205] Among the components of the power amplifier module 1C of the fourth embodiment, the components that are the same as those of the first to third embodiments are denoted by the same reference numerals and their description is omitted.

[0206] The power amplifier module 1C includes a first integrated circuit 2C and a second integrated circuit 3C.

[0207] The first integrated circuit 2C is similar to the first integrated circuit 2B of the third embodiment (see Fig.13 ) does not include diodes DR1 and DR2.

[0208] The second integrated circuit 3C is similar to the second integrated circuit 3B of the third embodiment (see Fig.13 ) also includes diodes DR1 and DR2.

[0209] The diodes DR1 and DR2 correspond to an example of the “plurality of diodes” in the present disclosure.

[0210] That is, in the power amplifier module 1B of the third embodiment, the diodes DR1 and DR2 are formed in the first integrated circuit 2B (IC chip of a compound semiconductor substrate). In contrast, in the power amplifier module 1C of the fourth embodiment, the diodes DR1 and DR2 are formed in the second integrated circuit 3C (IC chip of a Si substrate).

[0211] The diodes DR1 and DR2 formed in the IC chip of the Si substrate have the same temperature characteristics as the diodes D11 and D12 formed in the IC chip of the compound semiconductor substrate, but the absolute values ​​of the on-threshold voltages are different. Therefore, the subtraction circuit 41 having the function of amplifying the voltage V44 generates the voltage V2.

[0212] As described above, the power amplifier module 1C, like the power amplifier module 1, can suppress the deviation of the characteristics of the peak amplification system that performs the C-class operation, which is easily affected by the individual differences even in the Doherty amplifier, by the electronic fuse F. Furthermore, the power amplifier module 1C does not increase the number of connection wirings between the first integrated circuit 2C and the second integrated circuit 3C, and can suppress the characteristic variation due to temperature more accurately than the power amplifier module 1A.

[0213] <Fifth Implementation Method>

[0214] Fig.15 It is a diagram showing a circuit configuration of a power amplifier module according to a fifth embodiment.

[0215] Among the components of the power amplifier module 1D according to the fifth embodiment, the components that are the same as those in the first to fourth embodiments are denoted by the same reference numerals and their description is omitted.

[0216] The power amplifier module 1D includes a first integrated circuit 2C and a second integrated circuit 3D.

[0217] The second integrated circuit 3D includes a reference voltage output circuit Vref, a reference current output circuit Iref, and a variable constant current output circuit 31. In addition, the second integrated circuit 3D includes a buffer amplifier AMP1, a variable resistor VR1, a resistor array 32, and a buffer amplifier AMP2. In addition, the second integrated circuit 3D includes a buffer amplifier AMP3, a variable resistor VR2, a resistor Rcont, a buffer amplifier AMP4, a switch SW3, and a subtraction circuit 41.

[0218] The variable constant current output circuit 31 corresponds to an example of the “constant current output circuit” of the present disclosure.

[0219] In the power amplifier module 1B of the third embodiment (see Fig.13 ), the second integrated circuit 3B outputs the voltage V2 based on the voltages of the diodes DR1 and DR2 provided in the first integrated circuit 2B. On the other hand, in the power amplifier module 1D of the present embodiment, the second integrated circuit 3D outputs the voltage V2 based on the voltages of the diodes D11 and D12 in the first bias circuit 17.

[0220] The input terminal of the buffer amplifier AMP1 is electrically connected to the terminal B1. That is, the voltage V51 applied to the buffer amplifier AMP1 is the voltage of the diodes D11 and D12.

[0221] The buffer amplifier AMP1 outputs a voltage V52 based on the voltage V51 to one end of the variable resistor VR1. The series circuit of the variable resistor VR1 and the resistor array 32 divides the voltage V52 by resistance and outputs a voltage V53. The buffer amplifier AMP2 outputs a voltage V54 based on the voltage V53 to the non-inverting input terminal of the operational amplifier 41a via the resistor 41b.

[0222] As described above, the power amplifier module 1D can suppress the variation of the characteristics of the peak amplifier system that performs the C-class operation, which is easily affected by the individual differences even in the Doherty amplifier, by the electronic fuse F, similarly to the power amplifier module 1. Furthermore, the power amplifier module 1D does not increase the number of connection wirings between the first integrated circuit 2C and the second integrated circuit 3D, and can suppress the characteristic variation due to temperature more accurately than the power amplifier module 1C.

[0223] <Sixth Implementation Method>

[0224] Fig.16 It is a diagram showing a circuit configuration of a power amplifier module according to a sixth embodiment.

[0225] Among the components of the power amplifier module 1E of the sixth embodiment, the components that are the same as those of the first to fifth embodiments are denoted by the same reference numerals and their description is omitted.

[0226] The power amplifier module 1E includes a first integrated circuit 2E and a second integrated circuit 3E. The first integrated circuit 2E includes a matching circuit 61, a DC cut capacitor CD1, a driver amplifier 11, a third bias circuit 62, and a matching circuit 63.

[0227] The high-frequency input signal RFin is inputted to the matching circuit 61 via the terminal 1a. The high-frequency signal RF1 is supplied to the base of the transistor QD1 in the driver amplifier 11 via the matching circuit 61 and the DC cut capacitor CD1.

[0228] The emitter of transistor QD1 is electrically connected to a reference potential. The collector of transistor QD1 is electrically connected to power supply potential Vcc via choke inductor L2. Transistor QD1 outputs high frequency signal RF6 obtained by amplifying high frequency input signal RFin to DC cut capacitor C1 and phase shifter 14 via matching circuit 63.

[0229] The third bias circuit 62 includes diodes DD1 and DD2, a transistor QDD, and a resistor RbiasD1. The diodes DD1 and DD2 are each exemplified as a diode-connected HBT.

[0230] A bias current (bias voltage) is input to the anode of the diode DD1 from the second integrated circuit 3E via the terminal B3. The cathode of the diode DD1 is electrically connected to the anode of the diode DD2. The cathode of the diode DD2 is electrically connected to a reference potential. A series connection circuit of the diodes DD1 and DD2 generates a constant voltage.

[0231] The voltage of the series connection circuit of diodes DD1 and DD2 is input to the base of transistor QDD. The collector of transistor QDD is electrically connected to the power supply potential Vcbias2 via terminal CQ31 and terminal 1d. The emitter of transistor QDD is electrically connected to the base of transistor QD1 via resistor RbiasD1. In other words, transistor QDD and resistor RbiasD1 are emitter-follower connected. The base current of transistor QD1 is determined based on the voltage applied to the base of transistor QDD.

[0232] As described above, the terminal 1d for supplying power to the third bias circuit 62 is different from the terminal 1c for supplying power to the first bias circuit 17 and the second bias circuit 18. Therefore, the third bias circuit 62 can be prevented from affecting the measurement of the collector current of the transistor Q11 in the first bias circuit 17 and the collector current of the transistor Q21 in the second bias circuit 18. As a result, the power amplifier module 1E can accurately set the bias of the carrier amplifier 12 and the peak amplifier 13.

[0233] In addition, the above-mentioned embodiment is for easy understanding of the present invention, and is not intended to limit the interpretation of the present invention. The present invention can be changed / improved without departing from the gist thereof, and its equivalents are also included in the present invention.

Claims

1. A control circuit for controlling a Doherty amplifier comprising a carrier amplifier and a peak amplifier, wherein: The control circuit comprises: a resistor whose value can be irreversibly adjusted, and based on which a bias of the peak amplifier is determined; and The constant current output circuit outputs a constant current corresponding to a voltage obtained by adjusting the reference voltage by the resistor to a plurality of diodes connected in series.

2. The control circuit according to claim 1, wherein: The resistor comprises: A plurality of resistance elements having one end electrically connected to each other; and A plurality of electronic fuses have one end electrically connected to the other ends of the plurality of resistance elements respectively and the other ends electrically connected to each other.

3. The control circuit according to claim 1, wherein: The resistor comprises: A plurality of resistance elements electrically connected to each other at one end; A plurality of switches having one end electrically connected to the other ends of the plurality of resistor elements respectively and the other ends electrically connected to each other; and The one-time ROM outputs a plurality of signals for controlling the plurality of switches to be turned on or off.

4. The control circuit according to any one of claims 1 to 3, wherein: The control circuit includes a voltage output circuit that outputs a voltage obtained by adjusting a reference voltage by the resistor to a bias circuit that biases the peak amplifier.

5. The control circuit according to any one of claims 1 to 3, wherein: The control circuit includes a voltage output circuit that outputs a voltage adjusted by the resistor to a bias circuit that biases the peak amplifier, the reference voltage that decreases when the temperature increases and increases when the temperature decreases.

6. The control circuit according to any one of claims 1 to 3, wherein: The control circuit comprises: The differential amplifier outputs a voltage which is a difference between the voltages of the plurality of diodes and a voltage corresponding to the reference voltage to a bias circuit which biases the peak amplifier.

7. The control circuit according to claim 6, wherein: The plurality of diodes are formed on a chip on which the Doherty amplifier is formed.

8. The control circuit according to claim 6, wherein: The plurality of diodes are formed on a chip on which the resistor, the constant current output circuit, and the differential amplifier are formed.

9. The control circuit according to claim 1, wherein: The resistor comprises an electronic fuse.

10. A control circuit for controlling a Doherty amplifier comprising a carrier amplifier and a peak amplifier, wherein: The control circuit comprises: a resistor whose value can be irreversibly adjusted, and based on which a bias of the peak amplifier is determined; a constant current output circuit that outputs a constant current corresponding to a reference voltage to a first bias circuit that biases the carrier amplifier; and The differential amplifier outputs a voltage representing a difference between a voltage at an input terminal of the first bias circuit adjusted by the resistor and a voltage corresponding to the reference voltage to a second bias circuit for biasing the peak amplifier.

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