Array substrate and display device

Abstract

The present application provides an array substrate and a display device. The array substrate includes: a base substrate; a plurality of gate lines, which are arranged on the base substrate and arranged along a first direction; a plurality of signal lines, which are arranged on the base substrate and arranged along a second direction, and the second direction is perpendicular to the first direction; the gate lines and the signal lines are insulated, overlapped and surrounded to form a plurality of sub-pixel units; a transistor, which is arranged in the sub-pixel unit, and the orthographic projection of the transistor on the base substrate partially overlaps with the orthographic projection of at least one of the gate lines and the signal lines on the base substrate; and a pixel electrode layer, which is arranged in the sub-pixel unit and connected to the transistor. The array substrate and the display device described in the present application can improve the pixel aperture ratio, improve the poor afterimage display, and do not require an additional Mask process.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Electronic paper (EPD) products use electronic paper molds to achieve display and are very popular in the market due to their low power consumption and reusability.

[0003] However, the inventor of the present application has found that when displaying, existing electronic paper products may have ghosting of displayed content, resulting in poor display. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an array substrate and a display device.

[0005] Based on the above purpose, the present application provides an array substrate, including:

[0006] substrate substrate;

[0007] A plurality of gate lines are disposed on the base substrate and arranged along a first direction;

[0008] A plurality of signal lines are arranged on the substrate and arranged along a second direction, wherein the second direction is perpendicular to the first direction; the gate lines and the signal lines are insulated, overlapped and surrounded to form a plurality of sub-pixel units;

[0009] A transistor is disposed in the sub-pixel unit, and an orthographic projection of the transistor on the substrate overlaps with an orthographic projection of at least one of the gate line and the signal line on the substrate; and

[0010] The pixel electrode layer is disposed in the sub-pixel unit and connected to the transistor.

[0011] Optionally, the transistor includes a dual-gate transistor; the dual-gate transistor includes a first gate, a second gate, a first electrode, a bridge electrode and a second electrode, a first active layer unit is arranged between the first gate and the first electrode and the bridge electrode, and a second active layer unit is arranged between the second gate and the bridge electrode and the second electrode;

[0012] The bridging electrode includes a first bridging sub-electrode and a second bridging sub-electrode connected to the first bridging sub-electrode, the first active layer unit forms a first channel between the first electrode and the first bridging sub-electrode, and the second active layer unit forms a second channel between the second bridging sub-electrode and the second electrode;

[0013] The first gate electrode and the second gate electrode are respectively arranged in the same layer as the gate lines, and part of the gate lines are multiplexed into part of the first gate electrode, and part of the gate lines are multiplexed into part of the second gate electrode.

[0014] Optionally, the first electrode, the bridging electrode and the second electrode are arranged in the same layer as the signal line, and part of the signal line is multiplexed into at least part of the first electrode, and the orthographic projection of the first gate on the base substrate partially overlaps with the orthographic projection of the signal line on the base substrate.

[0015] Optionally, the pixel electrode layer is connected to the second electrode, the orthographic projection of the pixel electrode layer on the base substrate at least partially overlaps with the orthographic projection of the second electrode on the base substrate, and the orthographic projections of the first channel and the second channel on the base substrate do not overlap with the orthographic projection of the pixel electrode layer on the base substrate.

[0016] Optionally, the gate line is disconnected in the sub-pixel unit to form a gate line first end and a gate line second end;

[0017] A section of the gate line at the first end of the gate line close to the data line is multiplexed as a first sub-gate of the first gate, and the first gate further includes a second sub-gate disposed on a side of the gate line close to the sub-pixel unit and connected to the first sub-gate;

[0018] A section of the gate line at the second end of the gate line away from the data line is multiplexed as a third sub-gate of the second gate, and the second gate further includes a fourth sub-gate disposed on a side of the gate line close to the sub-pixel unit and connected to the third sub-gate;

[0019] The second sub-gate is connected to the fourth sub-gate.

[0020] Optionally, the first electrode includes a first sub-electrode that reuses a section of the data line and a second sub-electrode that extends from one end of the first sub-electrode along the first direction;

[0021] The second electrode includes a third sub-electrode extending along the first direction and a fourth sub-electrode vertically connected to an end of the third sub-electrode away from the second sub-electrode, the third sub-electrode is arranged opposite to the second sub-electrode, and the first sub-electrode, the second sub-electrode, the third sub-electrode and the fourth sub-electrode are arranged to form a rectangular area;

[0022] The bridging electrode comprises a strip structure extending along the first direction and is disposed in the rectangular region, and the orthographic projection of the bridging electrode on the base substrate at least partially overlaps with the orthographic projection of the gate line on the base substrate. 7. The array substrate according to claim 6, characterized in that:

[0023] The first bridging sub-electrode comprises a first side parallel to and close to the data line and a second side adjacent to the first side and away from the gate line, the first side is arranged opposite to the first sub-electrode, and the second side is arranged opposite to the second sub-electrode;

[0024] The second bridging sub-electrode includes a third side parallel to and away from the data line and a fourth side adjacent to the third side and away from the gate line. The third side is disposed opposite to the fourth sub-electrode, and the fourth side is disposed opposite to the third sub-electrode.

[0025] Optionally, the sub-pixel unit includes a first sub-pixel unit and a second sub-pixel unit that are adjacent to each other, and the pixel electrode layer includes a first pixel electrode arranged in the first sub-pixel unit and a second pixel electrode arranged in the second sub-pixel unit; the orthographic projection of the bridging electrode in the first sub-pixel unit on the base substrate at least partially overlaps with the orthographic projection of the second pixel electrode on the base substrate.

[0026] Optionally, the first gate and the second gate include strip structures extending along the second direction, and are arranged parallel to each other on a side of the gate line facing the sub-pixel unit.

[0027] Optionally, the first gate includes a first sub-gate that reuses a section of the gate line and a second sub-gate that extends from one end of the first sub-gate along the second direction, and the orthographic projections of the first sub-gate and the second sub-gate on the base substrate at least partially overlap with the orthographic projection of the data line on the base substrate;

[0028] The second gate includes a third sub-gate that reuses a section of the gate line and a fourth sub-gate that extends from one end of the third sub-gate along the second direction, and the fourth sub-gate is arranged parallel to the second sub-gate.

[0029] Optionally, a section of the signal line is multiplexed as the first electrode, and the bridging electrode and the second electrode include a strip structure extending along the second direction and are arranged in parallel with the first electrode;

[0030] The orthographic projections of the first electrode, the bridge electrode, and the second electrode on the base substrate at least partially overlap with the orthographic projection of the gate line on the base substrate.

[0031] Optionally, the first gate includes a strip structure extending along the second direction;

[0032] The second gate includes a strip structure extending along a first direction, and the second gate is vertically connected to an end of the first gate close to the gate line.

[0033] Optionally, the first gate includes a first sub-gate that reuses a section of the gate line and a second sub-gate that extends from one end of the first sub-gate along the second direction, and the orthographic projections of the first sub-gate and the second sub-gate on the base substrate at least partially overlap with the orthographic projection of the data line on the base substrate;

[0034] The second gate includes a third sub-gate that reuses a section of the gate line and a fourth sub-gate that extends from one end of the third sub-gate along the second direction;

[0035] A distance between an end of the second sub-gate away from the gate line and the gate line is greater than a distance between an end of the fourth sub-gate away from the gate line and the gate line.

[0036] Optionally, the bridging electrode further comprises a bridging electrode extension portion connected to one end of the bridging electrode close to the gate line and extending along the first direction, and the bridging electrode extension portion forms a part of the second bridging sub-electrode;

[0037] The orthographic projection of the bridging electrode extension portion on the base substrate at least partially overlaps with the orthographic projection of the gate line on the base substrate.

[0038] The present application also provides a display device, comprising the array substrate as described in any one of the above items.

[0039] From the above description, it can be seen that the array substrate and display device provided by the present application, by redesigning the dual-gate transistor, make the orthographic projection of the dual-gate transistor on the substrate overlap with the orthographic projection of the gate line and / or the signal line on the substrate, thereby reducing the area ratio of the dual-gate transistor in the sub-pixel unit, and then increasing the area ratio of the pixel electrode layer in the sub-pixel unit, thereby increasing the pixel aperture ratio, improving the poor afterimage display, and enhancing the display effect; at the same time, there is no need to add an additional Mask process, change the process path, add an additional film layer, increase the cost, and affect the production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 It is a structural schematic diagram of an electronic paper display device in the related art;

[0042] Figure 2 A schematic diagram of the display principle of an electronic paper display device in the related art;

[0043] Figure 3 A top view of an array substrate in the related art;

[0044] Figure 4 is another top view of an array substrate in the related art;

[0045] Figure 5 is a structural schematic diagram of an array substrate in the related art;

[0046] Figure 6 This is a schematic diagram of the structure of the array substrate described in the embodiment of the present application;

[0047] Figure 7 A top view of the array substrate described in an embodiment of the present application;

[0048] Figure 8 for Figure 7 A schematic diagram of the structure of each film layer of the array substrate;

[0049] Fig. 9 for Figure 8 Schematic diagram of the local structure of the middle membrane layer;

[0050] Fig.10 is another top view of the array substrate described in the embodiment of the present application;

[0051] Fig.11 for Fig.10 A schematic diagram of the structure of each film layer of the array substrate;

[0052] Fig.12 for Fig.11 Schematic diagram of the local structure of the middle membrane layer;

[0053] Fig.13 is another top view of the array substrate described in the embodiment of the present application;

[0054] Fig.14 for Fig.13 A schematic diagram of the structure of each film layer of the array substrate;

[0055] Fig.15 for Fig.14 Schematic diagram of the local structure of the middle membrane layer. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0057] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0058] An electronic paper display device generally includes an upper substrate, a lower substrate, and an electronic ink layer disposed between the upper substrate and the lower substrate.

[0059] In some embodiments, Figure 1 As shown, the upper substrate includes a PET film (PolyEthylene Terephthalate). An electrode layer is arranged between the upper substrate and the electronic ink layer, and the electrode layer is generally an ITO (Indium Tin Oxides) transparent electrode layer. A protective film is arranged on the upper substrate. The electronic ink layer includes an adhesive and a microcapsule structure arranged in the adhesive, and white particles, black particles and a transparent electrophoretic liquid are arranged in the microcapsule structure. The material of the white particles is generally TiO2 and has a positive charge, and the material of the black particles is generally carbon black and has a negative charge. The lower substrate is connected to the electronic ink layer through a bonding adhesive layer. The lower substrate may include an array substrate (TFTGlass), and the array substrate is provided with a pixel electrode layer (Pixel ITO) corresponding to the electrode layer.

[0060] like Figure 2As shown, in the initial state, white particles, black particles and other reflective particles are suspended in the transparent electrophoretic liquid, arranged evenly and moving randomly. When an electric field is applied between the pixel electrode layer and the transparent electrode layer, the white particles and the black particles move under the action of the electric field; for example, when negative electricity is applied to the transparent electrode layer and positive electricity is applied to the pixel electrode layer, the white particles gather on one side of the transparent electrode layer, and the black particles gather on one side of the pixel electrode layer. At this time, under the reflection of natural light, the electronic paper display device displays a white screen; and when positive electricity is applied to the transparent electrode layer and negative electricity is applied to the pixel electrode layer, the white particles gather on one side of the pixel electrode layer and the black particles gather on one side of the transparent electrode layer. At this time, under the reflection of natural light, the electronic paper display device displays a black screen; the electronic paper display device uses this principle to achieve color conversion of text and images.

[0061] In some embodiments, the white particles and black particles in the microcapsule structure can also be replaced with colored reflective particles, such as reflective particles with half of the area being red (or green, blue, etc.) and the other half being black, wherein the red area is the charged area. In this way, when an electric field is applied between the pixel electrode layer and the transparent electrode layer, the red (or green, blue) surface of the reflective particles can be directed toward the display side according to the direction of the electric field, thereby realizing reflection of external light irradiated to the reflective particles, thereby forming a color display of the electronic paper display device.

[0062] The inventor of the present application has found that the above electronic paper display device may have ghosting display problems. After further research, the inventor of the present application has found that this is caused by a small pixel aperture ratio. The specific reasons for the small pixel aperture ratio are as follows:

[0063] Due to the special display principle, the signal driving method of the electronic paper display device has high requirements for Ion and is also sensitive to Ioff, where Ion represents the on-current of the TFT transistor in the pixel circuit, and Ioff represents the off-current of the TFT transistor in the pixel circuit. To ensure a low Ioff, the pixel circuit of the electronic paper display device generally adopts a dual-gate transistor 4 structure, such as Figure 3 In order to avoid crosstalk coupling between the pixel electrode layer 5, the dual-gate transistor 4 and the signal line 3 during charging and voltage maintenance, the dual-gate transistor 5 and the signal line 3 are not covered by the pixel electrode layer 4, which results in a small pixel aperture ratio. The uncovered area of ​​the pixel electrode layer 4 in a sub-pixel unit accounts for 24.99% of the sub-pixel unit, and the pixel aperture ratio is only 75.01%.

[0064] In this case, a large part of the area in a sub-pixel unit is not directly driven by the effective electric field. In this part of the area, the electric field driving force is insufficient, the voltage does not meet the rated requirements, the driving force on the reflective particles is weak, the reflective particles will not change at any time with the change of the electric field, the display color of the display screen is impure, and the display effect is poor. In particular, when the sub-pixel unit applies voltage in the same direction for multiple times in a row to display the same color, such as red, most of the reflective particles in this part of the area will also move to the red area facing upward. At this time, the voltage direction changes, and the reflective particles in the area covering the pixel electrode layer will make the black area of ​​the reflective particles face upward under the control of the electric field, while the red area of ​​the reflective particles in the area not covering the pixel electrode layer continues to face upward, so that the content that should be displayed in black in the display screen is mixed with red, resulting in poor afterimage (Ghosting) display.

[0065] Therefore, if the pixel aperture ratio can be increased, the problem of ghosting display defects can be effectively improved.

[0066] In some embodiments, since the metal position of the dual-gate bridge, i.e., the bridge electrode 44, has a small area and there are A-Si channels on both sides of the bridge electrode 44, it cannot cover the ITO continuously. Therefore, it is considered to add an ITO strip 501 at the bridge electrode 44 position, such as Figure 4 After the experiment, it was found that this method did not improve the ghosting display problem.

[0067] In other embodiments, Figure 5 As shown, the pixel electrode layer 5 is covered on the double-gate transistor 4 structure, and a thicker resin insulating layer (Resin) 103 is added between the pixel electrode layer 5 and the double-gate transistor 4. According to the capacitance calculation formula The resin insulating layer 103 can effectively reduce the coupling effect of the pixel electrode layer 5 on the signal of the dual-gate transistor 4, and avoid the abnormal increase of the leakage of the dual-gate transistor 4. As shown in the following table, when the resin insulating layer 103 is not set, Ioff increases, and the maximum increase can be 428879%, which is unacceptable; when the resin insulating layer 103 is set, the maximum Ioff only increases to 113.7%, which is acceptable. Therefore, when the pixel electrode layer 5 is covered on the dual-gate transistor 4 structure, the resin insulating layer 103 must be covered.

[0068]

[0069] However, compared with the original 4-Mask process flow, this method needs to add a Mask process for forming the resin insulation layer 103, so that the solution requires a 5-Mask process flow, which will increase the Mask cost once; at the same time, the production of the resin insulation layer 103 requires baking and curing, which is time-consuming, increases the overall process production time, and has a greater impact on production capacity.

[0070] Based on the above reasons, the present application embodiment provides an array substrate that can increase the pixel aperture ratio without adding an additional resin insulating layer 103, thereby improving the display effect of the electronic paper display device. Figure 6 , Figure 7 As shown, the array substrate includes a base substrate 1 and a plurality of gate lines 2 and a plurality of signal lines 3 arranged on the base substrate 1. The plurality of gate lines 2 are arranged along a first direction, the plurality of signal lines 3 are arranged along a second direction perpendicular to the first direction, and the plurality of gate lines 2 and the plurality of signal lines 3 are insulated, overlapped and surrounded on the base substrate to form a plurality of sub-pixel units.

[0071] The array substrate also includes a transistor and a pixel electrode layer 5. For example, Figure 6 , 7 As shown in Figures 9 and 11, the transistor may include a dual-gate transistor 4. The dual-gate transistor 4 is arranged in the sub-pixel unit and is connected to the gate line 2 and the signal line 3 respectively; the pixel electrode layer 5 is arranged in the sub-pixel unit and is connected to the dual-gate transistor 4. The signal input through the gate line 2 and the signal line 3 can control the operation of the dual-gate transistor 4, and the dual-gate transistor 4 can also transmit the electrical signal to the pixel electrode layer 5, and then the pixel electrode layer 5 cooperates with the transparent electrode layer to realize the control of the reflective particles in the electronic ink layer.

[0072] Optionally, the transistor described in the embodiment of the present application is not limited to the dual-gate transistor 4, but may also be other polycrystalline silicon thin film transistors, amorphous silicon thin film transistors, oxide thin film transistors and organic thin film transistors with single gate or multiple gates, and the embodiment of the present application does not impose any restrictions on this.

[0073] At the same time, the orthographic projection of the dual-gate transistor 4 on the substrate 1 partially overlaps with the orthographic projection of at least one of the gate line 2 and the signal line 3 on the substrate 1, thereby reducing the area ratio of the dual-gate transistor 4 in the sub-pixel unit, thereby increasing the area of ​​the pixel electrode layer 5 located in the sub-pixel unit, thereby increasing the area ratio of the pixel electrode layer 5, improving the pixel aperture ratio, improving the poor afterimage display, and enhancing the display effect.

[0074] The array substrate described in the embodiment of the present application redesigns the dual-gate transistor so that the orthographic projection of the dual-gate transistor on the substrate overlaps with the orthographic projection of the gate line and / or the signal line on the substrate, thereby reducing the area ratio of the dual-gate transistor in the sub-pixel unit, thereby increasing the area ratio of the pixel electrode layer in the sub-pixel unit, increasing the pixel aperture ratio, improving the poor afterimage display, and enhancing the display effect; at the same time, there is no need to add an additional Mask process, change the process path, add an additional film layer, increase the cost, and affect the production capacity.

[0075] Optionally, in this embodiment, the signal line 3 may be a data line (Date) for inputting a Date signal.

[0076] Optionally, the first direction is the horizontal axis direction, and the second direction is the vertical axis direction. It should be noted that the channel width-to-length ratio is an important parameter indicator of the transistor. Among them, the channel width-to-length ratio is the ratio of the channel width W to the channel length L, the channel length L is the distance between the source and the drain, and the channel width W is the width between the source and the drain perpendicular to the L direction. Based on the IV characteristic curve of the transistor, the larger the channel width-to-length ratio, the larger the saturation current (Idsat) of the transistor, and the better the performance. Therefore, it is not feasible to reduce the area ratio of the dual-gate transistor in the sub-pixel unit by directly reducing the area size of the gate and / or source and drain of the transistor.

[0077] In the embodiment of the present application, by making the orthographic projection of the dual-gate transistor on the substrate overlap partially with the orthographic projection of the gate line and / or the signal line on the substrate, the area ratio of the dual-gate transistor in the sub-pixel unit can be reduced, and the area ratio of the pixel electrode layer in the sub-pixel unit can be increased, thereby improving the pixel aperture ratio.

[0078] At the same time, in any embodiment of the present application, the channel width-to-length ratio of the dual-gate transistor is ensured to be the same as that of the prior art, while reducing the area ratio of the dual-gate transistor in the sub-pixel unit, thereby increasing the area ratio of the pixel electrode layer in the sub-pixel unit and improving the pixel aperture ratio.

[0079] In some embodiments, Figure 6 , Figure 7 As shown, the dual-gate transistor 4 includes a first gate 41, a second gate 42, a first electrode 43, a bridge electrode 44 and a second electrode 45, and a first active layer unit (Active) 461 is arranged between the first gate 41 and the first electrode 43 and the bridge electrode 44, and a second active layer unit 462 is arranged between the second gate 42 and the bridge electrode 44 and the second electrode 45. The first active layer unit 461 and the second active layer unit 462 can be made of materials such as polysilicon and metal oxide (such as IGZO).

[0080] The bridging electrode 44 includes a first bridging sub-electrode 441 and a second bridging sub-electrode 442 connected to the first bridging sub-electrode, for example, the first bridging sub-electrode 441 and the second bridging sub-electrode 442 can be connected through a bridging portion. The first active layer unit 461 forms a first channel between the first electrode 43 and the first bridging sub-electrode 441, and the second active layer unit 462 forms a second channel between the second bridging sub-electrode 442 and the second electrode 45. A transistor structure of the dual-gate transistor 4 is formed by the first gate 41, the first electrode 43, the first bridging sub-electrode 441 and the first active layer unit 461, and another transistor structure of the dual-gate transistor 4 is formed by the second gate 42, the second bridging sub-electrode 442, the second electrode 45 and the second active layer unit 462. The structure and function of the dual-gate transistor 4 are realized by the cooperation of the two transistor structures.

[0081] The first gate 41 and the second gate 42 are arranged in the same layer as the gate line 2 and are respectively connected to the gate line 2. The first gate 41, the second gate 42 and the gate line 2 can be made of metal materials such as copper, aluminum, titanium, cobalt or their alloy materials. For example, they can be formed into a single-layer structure or a multi-layer structure, such as a molybdenum / aluminum double-layer structure.

[0082] The first electrode 43, the bridge electrode 44, the second electrode 45 and the signal line 3 are arranged in the same layer, and the first electrode 43 is connected to the signal line 3. The first electrode 43, the bridge electrode 44, the second electrode 45 and the signal line 3 can be made of metal materials such as copper, aluminum, titanium, cobalt or their alloy materials, for example, they can be formed into a single-layer structure or a multi-layer structure, such as a MoTi / Cu / MoTi three-layer structure.

[0083] A gate insulating layer (GI) 101 is further disposed between the first gate 41, the second gate 42 and the first active layer unit 461, the second active layer unit 462. The gate insulating layer 101 may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0084] At the same time, the orthographic projection of the first electrode 43 on the substrate substrate 1 at least partially overlaps with the orthographic projection of the first gate 41 on the substrate substrate 1, the orthographic projection of the second electrode 45 on the substrate substrate 1 at least partially overlaps with the orthographic projection of the second gate 42 on the substrate substrate 1, the orthographic projection of the first bridging sub-electrode 441 on the substrate substrate 1 partially overlaps with the orthographic projection of the first gate 41 on the substrate substrate 1, and the orthographic projection of the second bridging sub-electrode 442 on the substrate substrate 1 partially overlaps with the orthographic projection of the second gate 42 on the substrate substrate 1, thereby forming the structure of a dual-gate transistor 4.

[0085] In this embodiment, if Figure 8 , Fig.11 , Fig.14 As shown, the first gate 41 and the second gate 42 are respectively arranged in the same layer as the gate line 2, and part of the gate line 2 is reused as part of the first gate 41, and part of the gate line is reused as part of the second gate 42, so that part of the gate line 2 can be used to form at least a part of the first gate 41 and the second gate 42, thereby reducing the area ratio of the first gate 41 and the second gate 42 in the sub-pixel unit, that is, reducing the area ratio of the dual-gate transistor 4 in the sub-pixel unit, reserving more space for the arrangement of the pixel electrode layer 5, and thus improving the pixel aperture ratio. At the same time, since the first gate 41 and the second gate 42 themselves are connected to the gate line 2, when at least a part of the first gate 41 and the second gate 42 are formed by part of the gate line 2, the performance of the first gate 41 and the second gate 42 will not be affected, that is, the performance of the dual-gate transistor 4 will not be affected by the structural arrangement of the first gate 41 and the second gate 42.

[0086] In the present embodiment, part of the gate lines are used to form at least part of the first gate and the second gate, thereby reducing the area ratio of the first gate and the second gate in the sub-pixel unit, so that more setting space can be reserved for the pixel electrode layer, and the area ratio of the pixel electrode layer in the sub-pixel unit is increased, thereby increasing the pixel aperture ratio, which can effectively improve the poor afterimage display and enhance the display effect.

[0087] In some embodiments, Figure 7-Figure 15 As shown, the first electrode 43, the bridge electrode 44 and the second electrode 45 are arranged in the same layer as the signal line 3, and part of the signal line 3 is reused as at least part of the first electrode 43, that is, at least part of the first electrode 43 is formed by using part of the signal line 3, thereby reducing the area ratio of the first electrode 43 in the sub-pixel unit, and then reducing the area ratio of the dual-gate transistor 4 in the sub-pixel unit, so that more setting space can be reserved for the pixel electrode layer, and the area ratio of the pixel electrode layer in the sub-pixel unit is increased. At the same time, since the first electrode 43 is originally connected to the signal line 3, the electrical signal of the first electrode 43 is also directly provided by the signal line 3, so the formation of at least part of the first electrode 43 by part of the signal line 3 will not affect the performance of the dual-gate transistor 4.

[0088] At the same time, the orthographic projection of the first gate 41 on the substrate 1 partially overlaps with the orthographic projection of the signal line 3 on the substrate 1, that is, at least part of the first gate 41 is arranged below the signal line 3, so that the first gate 41 and the first electrode 43 can form a first channel on the active layer 46 between the two, and at the same time, the area proportion of the first gate 41 in the sub-pixel unit can be further reduced, thereby reducing the area proportion of the dual-gate transistor 4 in the sub-pixel unit, so as to reserve more space for the pixel electrode layer 5, thereby increasing the pixel aperture ratio. Due to the existence of the gate insulating layer 101, the first gate 41 and the signal line 3 are still insulated, that is, the electrical signal between the first gate 41 and the signal line 3 will not be affected, and the performance of the dual-gate transistor 4 will not be affected. Optionally, in this embodiment, part of the signal line 3 can be used to form part of the first electrode 43, and part of the signal line 3 can also be used to form all of the first electrode 43, and this embodiment is not limited to this.

[0089] In some embodiments, Figure 7 As shown, the pixel electrode layer 5 is connected to the second electrode 45 through a via 49, and the orthographic projection of the pixel electrode layer 5 on the base substrate 1 overlaps at least partially with the orthographic projection of the second electrode 45 on the base substrate 1, that is, the pixel electrode layer 2 can be arranged above the second electrode 45 and cover part or all of the second electrode 45, thereby increasing the area proportion of the pixel electrode layer 5. At the same time, the orthographic projections of the first channel and the second channel on the base substrate 1 do not overlap with the orthographic projection of the pixel electrode layer 5 on the base substrate 1, thereby avoiding crosstalk coupling between the pixel electrode layer 5 and the dual-gate transistor 4.

[0090] In this embodiment, the pixel electrode layer 5 may cover part or all of the second electrode 45 , and not cover the first channel and the second channel, so that the performance of the dual-gate transistor 4 is not affected while increasing the proportion of the pixel electrode layer 5 .

[0091] In some embodiments, Figure 8 As shown, the first gate 41 and the second gate 42 both include L-shaped structures that are oppositely disposed and connected to each other, and are disposed in the sub-pixel unit.

[0092] like Fig. 9 As shown, the gate line 3 is disconnected in the sub-pixel unit to form a gate line first end 201 and a gate line second end 202 , and the gate line first end 201 is closer to the data line 3 than the gate line second end 202 .

[0093] A section of the gate line 2 at the first end 201 of the gate line close to the data line 3 is multiplexed as the first sub-gate 411 of the first gate 41, that is, a portion of the gate line extending from the first end 201 of the gate line close to the data line 3 is multiplexed as the first sub-gate 411; the first gate 41 also includes a second sub-gate 412 arranged on a side of the gate line 2 close to the sub-pixel unit and connected to the first sub-gate 411.

[0094] A section of the gate line 3 at the second end 202 of the gate line away from the data line 3 is multiplexed as the third sub-gate 421 of the second gate 42, that is, a portion of the gate line 42 extending from the second end 202 of the gate line away from the data line 3 is multiplexed as the third sub-gate 421; the second gate 42 also includes a fourth sub-gate 422 arranged on a side of the gate line 2 close to the sub-pixel unit and connected to the third sub-gate 421.

[0095] Meanwhile, the second sub-gate 412 is connected to the fourth sub-gate 422 ; for example, the second sub-gate 412 and the fourth sub-gate 422 may be connected via a gate bridge portion.

[0096] In this embodiment, part of the gate line 2 is used to form the first sub-gate 411 and the third sub-gate 421. In this way, the second sub-gate 412 and the fourth sub-gate 422 only need to be set in the area where the sub-pixel unit does not cover the gate line 2 and the data line 3, thereby reducing the area occupied by the first gate 41 and the second gate 42.

[0097] In some optional embodiments, such as Fig. 9 As shown, the first electrode 43 includes a first sub-electrode 431 that reuses a section of the data line 3 and a second sub-electrode 432 that extends from one end of the first sub-electrode 431 along the first direction; wherein the first sub-electrode 431 is connected to the second sub-electrode 432 .

[0098] The second electrode 45 includes a third sub-electrode 451 extending along the first direction and a fourth sub-electrode 452 vertically connected to an end of the third sub-electrode 451 away from the second sub-electrode 432, the fourth sub-electrode 452 is arranged in parallel with the first sub-electrode 431, and the fourth sub-electrode 452 is arranged on a side of the third sub-electrode 451 close to the gate line 2. The third sub-electrode 451 is arranged opposite to the second sub-electrode 432, and the first sub-electrode 431, the second sub-electrode 432, the third sub-electrode 451 and the fourth sub-electrode 452 are arranged to form a rectangular area.

[0099] In this embodiment, part of the signal line 3 is used to form the first sub-electrode 431, which can reduce the occupied area of ​​the double-gate transistor in the sub-pixel unit.

[0100] The bridge electrode 44 is arranged in the rectangular area formed by the first electrode layer 43 and the second electrode layer 45. The bridge electrode 44 is a strip structure and extends along the first direction, and the orthographic projection of the bridge electrode 44 on the substrate 1 overlaps at least partially with the orthographic projection of the gate line 2 on the substrate 1, thereby reducing the area proportion of the bridge electrode 1 in the sub-pixel unit, thereby reducing the area proportion of the dual-gate transistor 4 in the sub-pixel unit. At the same time, due to the existence of the gate insulating layer 101, the bridge electrode 44 and the gate line 2 are still insulated, that is, the electrical signal between the bridge electrode 44 and the gate line 2 will not be affected, and the performance of the dual-gate transistor 4 will not be affected.

[0101] Optional, such as Fig. 9 As shown, the first bridging sub-electrode 441 includes a first side parallel to and close to the data line 3 (i.e., the shorter side on the left side of the first bridging sub-electrode 441) and a second side adjacent to the first side and away from the gate line 2 (i.e., the upper side of the first bridging sub-electrode 441), the first side is arranged opposite to the first sub-electrode 431, and the second side is arranged opposite to the second sub-electrode 432. The second bridging sub-electrode 442 includes a third side parallel to and away from the data line 3 (i.e., the shorter side on the right side of the second bridging sub-electrode 442) and a fourth side adjacent to the third side and away from the gate line 2 (i.e., the upper side of the second bridging sub-electrode 442), the third side is arranged opposite to the fourth sub-electrode 452, and the fourth side is arranged opposite to the third sub-electrode 451.

[0102] In this embodiment, the first channel is formed by two parts, namely: the part between the first bridging sub-electrode 441 and the first sub-electrode 431 including the first side, and the part between the first bridging sub-electrode 441 and the second sub-electrode 432 including the second side. That is, in this embodiment, the channel width of the first channel is supplemented by the shorter side on the left side of the bridging electrode 44, and the area proportion of the dual-gate transistor 4 in the sub-pixel unit is reduced under the condition of ensuring the channel width-to-length ratio. Similarly, the channel width of the second channel is supplemented by the shorter side on the right side of the bridging electrode 44, and the area proportion of the dual-gate transistor 4 in the sub-pixel unit is reduced under the condition of ensuring the channel width-to-length ratio. Thereby, the area proportion of the dual-gate transistor 4 in the sub-pixel unit is reduced without affecting the performance of the dual-gate transistor 4, so as to reserve more space for the setting of the pixel electrode layer 5, thereby increasing the area proportion of the pixel electrode layer 5 in the sub-pixel unit and improving the pixel aperture ratio.

[0103] Optional, such as Figure 7As shown, the sub-pixel unit includes a first sub-pixel unit 61 and a second sub-pixel unit 62 that are adjacently arranged, and the pixel electrode layer 5 includes a first pixel electrode 51 arranged in the first sub-pixel unit 61 and a second pixel electrode 52 arranged in the second sub-pixel unit 62. The orthographic projection of the bridging electrode 44 in the first sub-pixel unit 61 on the base substrate 1 at least partially overlaps with the orthographic projection of the second pixel electrode 52 on the base substrate 1.

[0104] like Figure 8 As shown, the second pixel electrode 52 in the second sub-pixel unit 62 also includes a protrusion 521, the orthographic projection of the protrusion 521 on the base substrate 1 falls into the first sub-pixel unit 61, and at least partially overlaps with the orthographic projection of the bridge electrode 44 in the first sub-pixel unit 61 on the base substrate 1. That is, the pixel electrode layer 5 in the first sub-pixel unit 61 includes not only the first pixel electrode 51, but also part of the second pixel electrode 52 (that is, the part of the second pixel electrode 52 covering part or all of the bridge electrode 44), so that the area ratio of the pixel electrode layer 5 in the first sub-pixel unit 61 can be increased, and the pixel aperture ratio can be improved. At the same time, the part of the second pixel electrode 52 covering the bridge electrode 44 will not affect the performance of the dual-gate transistor 4.

[0105] In other embodiments, Fig.10 , Fig.11 As shown, the first gate 41 and the second gate 42 both include a strip structure extending along the second direction; at the same time, the first gate 41 and the second gate 42 are arranged in parallel with each other on the side of the gate line 2 facing the sub-pixel unit. In this embodiment, the double-gate transistor 4 formed by the first gate 41, the second gate 42, the first electrode 43, the bridge electrode 44, and the second electrode 45 overlaps with the gate line 2 and the signal line 3 respectively, thereby reducing the area ratio of the double-gate transistor 4 in the sub-pixel unit, so as to reserve more space for the setting of the pixel electrode layer 5, thereby increasing the area ratio of the pixel electrode layer 5 in the sub-pixel unit and improving the pixel aperture ratio.

[0106] like Fig.12As shown, the first gate 41 includes a first sub-gate 411 that reuses a section of the gate line 2 and a second sub-gate 412 that extends from one end of the first sub-gate 411 along the second direction, and the orthographic projections of the first sub-gate 411 and the second sub-gate 412 on the base substrate 1 at least partially overlap with the orthographic projection of the data line 3 on the base substrate 1. The second gate 42 includes a third sub-gate 421 that reuses a section of the gate line 2 and a fourth sub-gate 422 that extends from one end of the third sub-gate 421 along the second direction, and the fourth sub-gate 422 and the second sub-gate 412 are arranged in parallel with each other, and there is a preset distance between them.

[0107] Optional, such as Fig.11 , Fig.14 As shown, part of the signal lines 3 are multiplexed into all of the first electrodes 41. Fig.11 As shown, a section of the signal line is multiplexed into the first electrode 43, and the bridging electrode 44 and the second electrode 45 include a strip structure extending along the second direction and are arranged in parallel with the first electrode 44. At the same time, the orthographic projections of the first electrode 43, the bridging electrode 44 and the second electrode 45 on the base substrate 1 at least partially overlap with the orthographic projection of the gate line 2 on the base substrate 1.

[0108] like Fig.12 As shown, the portion of the bridging electrode 44 close to the first electrode 43 forms a first bridging sub-electrode 441, and the portion of the bridging electrode 44 close to the second electrode 45 forms a second bridging sub-electrode 442. The first bridging sub-electrode 441 and the second bridging sub-electrode 442 both extend along the second direction, that is, a transistor structure of the dual-gate transistor 4 is formed by the first gate 41, the first electrode 43, the first bridging sub-electrode 441 and the first active layer unit 461, and another transistor structure of the dual-gate transistor 4 is formed by the second gate 42, the second bridging sub-electrode 442, the second electrode 45 and the second active layer unit 462.

[0109] In this embodiment, part of the signal line 3 is used to form the entire first electrode 41 , thereby reducing the area occupied by the dual-gate transistor 4 in the sub-pixel unit.

[0110] In other embodiments, Fig.13 , Fig.14As shown, the first gate 41 includes a strip structure extending along the second direction, the second gate 42 includes a rectangular strip structure extending along the first direction, and the second gate 42 is vertically connected to an end of the first gate 41 close to the gate line 2. The first gate 41 and the second gate 42 are vertically connected to each other in an L-shaped structure, and are arranged on a side of the gate line 2 close to the sub-pixel unit. That is, the first gate 41 and the second gate 42 are vertically arranged at the intersection of the gate line 2 and the signal line 3.

[0111] Optional, such as Fig.15 As shown, the first gate 41 includes a first sub-gate 411 that reuses a section of the gate line 2 and a second sub-gate 412 that extends from one end of the first sub-gate 411 along the second direction, and the orthographic projections of the first sub-gate 411 and the second sub-gate 412 on the base substrate 1 at least partially overlap with the orthographic projection of the data line 3 on the base substrate 1. The second gate 42 includes a third sub-gate 421 that reuses a section of the gate line 2 and a fourth sub-gate 422 that extends from one end of the third sub-gate 421 along the second direction; and the distance between the end of the second sub-gate 412 away from the gate line 2 and the gate line 2 is greater than the distance between the end of the fourth sub-gate 422 away from the gate line 2 and the gate line 2.

[0112] Optional, such as Fig.14 As shown, the bridging electrode 44 includes a bridging electrode extension portion 443 connected to one end of the bridging electrode 44 close to the gate line 1 and extending along the first direction, wherein the bridging electrode 44 and the bridging electrode extension portion 443 are vertically connected to form an L-shaped structure. The orthographic projection of the bridging electrode extension portion 443 on the base substrate 1 at least partially overlaps with the orthographic projection of the gate line 2 on the base substrate 1, thereby reducing the area proportion of the dual-gate transistor 4 in the sub-pixel unit.

[0113] Optional, such as Fig.15 As shown, the bridge electrode extension 443 forms part of the second bridge sub-electrode, that is, part of the second electrode 45 is parallel to the bridge electrode extension 443. Fig.14 , 15 As shown, two adjacent sides of the second electrode 45 are parallel to the bridging electrode 44 and the bridging electrode extension 443, respectively, that is, the left side of the second electrode 45 is parallel to the bridging electrode 44, and the lower side of the second electrode 45 is parallel to the bridging electrode extension 443, so that a part of the second channel is formed between the left side of the second electrode 45 and the bridging electrode 44, and another part of the second channel is formed between the lower side of the second electrode 45 and the bridging electrode extension 443.

[0114] Optionally, in any of the above embodiments, the array substrate also includes a first electrode 21 of a storage capacitor arranged in the same layer as the gate line 2, and a second electrode 31 of a storage capacitor arranged in the same layer as the signal line 3, wherein the second electrode 31 of the storage capacitor is connected to the second electrode 45, and the orthographic projection of the first electrode 21 of the storage capacitor on the base substrate 1 at least partially overlaps with the orthographic projection of the second electrode 31 of the storage capacitor on the base substrate 1, thereby forming a storage capacitor corresponding to the sub-pixel unit.

[0115] It should be noted that the dual-gate transistors in the above embodiments are independently selected from one of polysilicon thin film transistors, amorphous silicon thin film transistors, oxide thin film transistors and organic thin film transistors. The "first electrode" involved in this embodiment may specifically refer to the source or drain of the transistor, and the corresponding "second electrode" may specifically refer to the drain or source of the transistor. Of course, those skilled in the art should know that the "first electrode" and the "second electrode" are interchangeable.

[0116] Optionally, in the above embodiment, when having Figure 3 When the related art shown has the same channel width-to-length ratio, compared with Figure 3 The pixel opening ratio of the related art shown is 75.91%, and the pixel opening ratio of the array substrate described in the embodiment of the present application can be increased to a pixel opening ratio of 82%-85%.

[0117] In a specific embodiment, Figure 7 As shown, in this embodiment, part of the gate line 2 is used to form at least a part of the first gate 41 and the second gate 42, and part of the signal line 3 is used to form part of the first electrode 43. The L-shaped first electrode 43, the second electrode 45 and the strip-shaped rectangular bridging electrode 44 are coordinated with the first gate 41 and the second gate 42 in the shape of a "X". At the same time, the pixel electrode layer 5 is covered on the bridging electrode 44 and the second electrode 45, so that the pixel aperture ratio can reach 84.5%.

[0118] In a specific embodiment, Fig.10 As shown, in this embodiment, part of the gate line 2 is used to form at least a part of the first gate 41 and the second gate 42, and part of the signal line 3 is used to form the entire first electrode 43, so that the pixel aperture ratio can reach 82.18%.

[0119] In a specific embodiment, Fig.13 As shown, in this embodiment, part of the gate line 2 is used to form at least a part of the first gate 41 and the second gate 42, and the first gate 41 and the second gate 42 form an L-shaped structure, part of the signal line 3 is used to form the entire first electrode 43, and the L-shaped bridging electrode 44 is matched with the adjacent two sides of the second electrode 45, so that the pixel aperture ratio can reach 82.98%.

[0120] Based on the same inventive concept, corresponding to the array substrate described in any of the above embodiments, the present application also provides a display device, which includes the array substrate described in any of the above embodiments. The display device includes the array substrate described in any of the above embodiments, and has the beneficial effects of the embodiments corresponding to the array substrate, which will not be repeated here.

[0121] It should be noted that the display device in this embodiment can be: electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, or any other product or component with a display function.

[0122] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0123] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0124] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0125] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0126] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. An array substrate, It is characterized in that include: substrate substrate; A plurality of gate lines are disposed on the base substrate and arranged along a first direction; A plurality of signal lines are arranged on the substrate and arranged along a second direction, wherein the second direction is perpendicular to the first direction; the gate lines and the signal lines are insulated, overlapped and surrounded to form a plurality of sub-pixel units; A transistor is disposed in the sub-pixel unit, and an orthographic projection of the transistor on the substrate overlaps with an orthographic projection of at least one of the gate line and the signal line on the substrate; as well as, A pixel electrode layer, disposed in the sub-pixel unit and connected to the transistor; The transistor comprises a dual-gate transistor; the dual-gate transistor comprises a first gate, a second gate, a first electrode, a bridge electrode and a second electrode, a first active layer unit is arranged between the first gate and the first electrode and the bridge electrode, and a second active layer unit is arranged between the second gate and the bridge electrode and the second electrode; The bridging electrode includes a first bridging sub-electrode and a second bridging sub-electrode connected to the first bridging sub-electrode, the first active layer unit forms a first channel between the first electrode and the first bridging sub-electrode, and the second active layer unit forms a second channel between the second bridging sub-electrode and the second electrode; The first gate and the second gate are respectively arranged in the same layer as the gate lines, and part of the gate lines are multiplexed into part of the first gate, and part of the gate lines are multiplexed into part of the second gate; The first electrode, the bridge electrode and the second electrode are arranged in the same layer as the signal line, and part of the signal line is multiplexed as at least part of the first electrode, and the orthographic projection of the first gate on the base substrate partially overlaps with the orthographic projection of the signal line on the base substrate; The pixel electrode layer is connected to the second electrode, an orthographic projection of the pixel electrode layer on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate, and an orthographic projection of the first channel and the second channel on the base substrate does not overlap with an orthographic projection of the pixel electrode layer on the base substrate; The gate line is disconnected in the sub-pixel unit to form a gate line first end and a gate line second end; A section of the gate line at the first end of the gate line close to the data line is multiplexed as a first sub-gate of the first gate, and the first gate further includes a second sub-gate disposed on a side of the gate line close to the sub-pixel unit and connected to the first sub-gate; A section of the gate line at the second end of the gate line away from the data line is multiplexed as a third sub-gate of the second gate, and the second gate further includes a fourth sub-gate disposed on a side of the gate line close to the sub-pixel unit and connected to the third sub-gate; The second sub-gate is connected to the fourth sub-gate; The first electrode includes a first sub-electrode that reuses a section of the data line and a second sub-electrode that extends from one end of the first sub-electrode along a first direction; The second electrode includes a third sub-electrode extending along the first direction and a fourth sub-electrode vertically connected to an end of the third sub-electrode away from the second sub-electrode, the third sub-electrode is arranged opposite to the second sub-electrode, and the first sub-electrode, the second sub-electrode, the third sub-electrode and the fourth sub-electrode are arranged to form a rectangular area; The bridging electrode includes a strip structure extending along the first direction and is disposed in the rectangular region. The orthographic projection of the bridging electrode on the base substrate at least partially overlaps with the orthographic projection of the gate line on the base substrate.

2. The array substrate according to claim 1, It is characterized in that The first bridging sub-electrode comprises a first side parallel to and close to the data line and a second side adjacent to the first side and away from the gate line, the first side is arranged opposite to the first sub-electrode, and the second side is arranged opposite to the second sub-electrode; The second bridging sub-electrode includes a third side parallel to and away from the data line and a fourth side adjacent to the third side and away from the gate line. The third side is disposed opposite to the fourth sub-electrode, and the fourth side is disposed opposite to the third sub-electrode.

3. The array substrate according to claim 1, It is characterized in that The sub-pixel unit includes a first sub-pixel unit and a second sub-pixel unit that are adjacent to each other, and the pixel electrode layer includes a first pixel electrode arranged in the first sub-pixel unit and a second pixel electrode arranged in the second sub-pixel unit; the orthographic projection of the bridging electrode in the first sub-pixel unit on the base substrate at least partially overlaps with the orthographic projection of the second pixel electrode on the base substrate.

4. The array substrate according to claim 1, It is characterized in that The first gate and the second gate include strip structures extending along the second direction, and are arranged parallel to each other on a side of the gate line facing the sub-pixel unit.

5. The array substrate according to claim 4, It is characterized in that The first gate includes a first sub-gate that reuses a section of the gate line and a second sub-gate that extends from one end of the first sub-gate along a second direction, and the orthographic projections of the first sub-gate and the second sub-gate on the base substrate at least partially overlap with the orthographic projection of the data line on the base substrate; The second gate includes a third sub-gate that reuses a section of the gate line and a fourth sub-gate that extends from one end of the third sub-gate along the second direction, and the fourth sub-gate is arranged parallel to the second sub-gate.

6. The array substrate according to claim 5, It is characterized in that A section of the signal line is multiplexed as the first electrode, and the bridging electrode and the second electrode include a strip structure extending along the second direction and are arranged in parallel with the first electrode; The orthographic projections of the first electrode, the bridge electrode, and the second electrode on the base substrate at least partially overlap with the orthographic projection of the gate line on the base substrate.

7. The array substrate according to claim 4, It is characterized in that The first gate comprises a strip structure extending along a second direction; The second gate includes a strip structure extending along a first direction, and the second gate is vertically connected to an end of the first gate close to the gate line.

8. The array substrate according to claim 4, It is characterized in that The first gate includes a first sub-gate that reuses a section of the gate line and a second sub-gate that extends from one end of the first sub-gate along a second direction, and the orthographic projections of the first sub-gate and the second sub-gate on the base substrate at least partially overlap with the orthographic projection of the data line on the base substrate; The second gate includes a third sub-gate that reuses a section of the gate line and a fourth sub-gate that extends from one end of the third sub-gate along the second direction; A distance between an end of the second sub-gate away from the gate line and the gate line is greater than a distance between an end of the fourth sub-gate away from the gate line and the gate line.

9. The array substrate according to claim 8, It is characterized in that The bridging electrode further comprises a bridging electrode extension portion connected to one end of the bridging electrode close to the gate line and extending along the first direction, wherein the bridging electrode extension portion forms a part of the second bridging sub-electrode; The orthographic projection of the bridging electrode extension portion on the base substrate at least partially overlaps with the orthographic projection of the gate line on the base substrate.

10. An array substrate, It is characterized in that include: substrate substrate; A plurality of gate lines are disposed on the base substrate and arranged along a first direction; A plurality of signal lines are arranged on the substrate and arranged along a second direction, wherein the second direction is perpendicular to the first direction; the gate lines and the signal lines are insulated, overlapped and surrounded to form a plurality of sub-pixel units; A transistor is disposed in the sub-pixel unit, and an orthographic projection of the transistor on the substrate overlaps with an orthographic projection of at least one of the gate line and the signal line on the substrate; as well as, A pixel electrode layer, disposed in the sub-pixel unit and connected to the transistor; The transistor comprises a dual-gate transistor; the dual-gate transistor comprises a first gate, a second gate, a first electrode, a bridge electrode and a second electrode, a first active layer unit is arranged between the first gate and the first electrode and the bridge electrode, and a second active layer unit is arranged between the second gate and the bridge electrode and the second electrode; The bridging electrode includes a first bridging sub-electrode and a second bridging sub-electrode connected to the first bridging sub-electrode, the first active layer unit forms a first channel between the first electrode and the first bridging sub-electrode, and the second active layer unit forms a second channel between the second bridging sub-electrode and the second electrode; The first gate and the second gate are respectively arranged in the same layer as the gate lines, and part of the gate lines are multiplexed into part of the first gate, and part of the gate lines are multiplexed into part of the second gate; The first electrode, the bridge electrode and the second electrode are arranged in the same layer as the signal line, and part of the signal line is multiplexed as at least part of the first electrode, and the orthographic projection of the first gate on the base substrate partially overlaps with the orthographic projection of the signal line on the base substrate; The pixel electrode layer is connected to the second electrode, an orthographic projection of the pixel electrode layer on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate, and an orthographic projection of the first channel and the second channel on the base substrate does not overlap with an orthographic projection of the pixel electrode layer on the base substrate; The first gate and the second gate include a strip structure extending along the second direction, and are arranged parallel to each other on a side of the gate line facing the sub-pixel unit; The first gate comprises a strip structure extending along a second direction; The second gate comprises a strip structure extending along a first direction, and the second gate is vertically connected to an end of the first gate close to the gate line; The first gate includes a first sub-gate that reuses a section of the gate line and a second sub-gate that extends from one end of the first sub-gate along a second direction, and the orthographic projections of the first sub-gate and the second sub-gate on the base substrate at least partially overlap with the orthographic projection of the data line on the base substrate; The second gate includes a third sub-gate that reuses a section of the gate line and a fourth sub-gate that extends from one end of the third sub-gate along the second direction; A distance between an end of the second sub-gate away from the gate line and the gate line is greater than a distance between an end of the fourth sub-gate away from the gate line and the gate line.

11. The array substrate according to claim 10, It is characterized in that The gate line is disconnected in the sub-pixel unit to form a gate line first end and a gate line second end; A section of the gate line at the first end of the gate line close to the data line is multiplexed as a first sub-gate of the first gate, and the first gate further includes a second sub-gate disposed on a side of the gate line close to the sub-pixel unit and connected to the first sub-gate; A section of the gate line at the second end of the gate line away from the data line is multiplexed as a third sub-gate of the second gate, and the second gate further includes a fourth sub-gate disposed on a side of the gate line close to the sub-pixel unit and connected to the third sub-gate; The second sub-gate is connected to the fourth sub-gate.

12. The array substrate according to claim 11, It is characterized in that The first electrode includes a first sub-electrode that reuses a section of the data line and a second sub-electrode that extends from one end of the first sub-electrode along a first direction; The second electrode includes a third sub-electrode extending along the first direction and a fourth sub-electrode vertically connected to an end of the third sub-electrode away from the second sub-electrode, the third sub-electrode is arranged opposite to the second sub-electrode, and the first sub-electrode, the second sub-electrode, the third sub-electrode and the fourth sub-electrode are arranged to form a rectangular area; The bridging electrode includes a strip structure extending along the first direction and is disposed in the rectangular region. The orthographic projection of the bridging electrode on the base substrate at least partially overlaps with the orthographic projection of the gate line on the base substrate.

13. The array substrate according to claim 12, It is characterized in that The first bridging sub-electrode comprises a first side parallel to and close to the data line and a second side adjacent to the first side and away from the gate line, the first side is arranged opposite to the first sub-electrode, and the second side is arranged opposite to the second sub-electrode; The second bridging sub-electrode includes a third side parallel to and away from the data line and a fourth side adjacent to the third side and away from the gate line. The third side is disposed opposite to the fourth sub-electrode, and the fourth side is disposed opposite to the third sub-electrode.

14. The array substrate according to claim 12, It is characterized in that The sub-pixel unit includes a first sub-pixel unit and a second sub-pixel unit that are adjacent to each other, and the pixel electrode layer includes a first pixel electrode arranged in the first sub-pixel unit and a second pixel electrode arranged in the second sub-pixel unit; the orthographic projection of the bridging electrode in the first sub-pixel unit on the base substrate at least partially overlaps with the orthographic projection of the second pixel electrode on the base substrate.

15. The array substrate according to claim 10, It is characterized in that The bridging electrode further comprises a bridging electrode extension portion connected to one end of the bridging electrode close to the gate line and extending along the first direction, wherein the bridging electrode extension portion forms a part of the second bridging sub-electrode; The orthographic projection of the bridging electrode extension portion on the base substrate at least partially overlaps with the orthographic projection of the gate line on the base substrate.

16. A display device, It is characterized in that Comprising the array substrate as described in any one of claims 1-9 or 10-15.

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