Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device preparation method, which comprises the following steps: forming a first sacrificial layer, a memory stack structure and a channel structure on a substrate, the channel structure extending through the memory stack structure and the first sacrificial layer and reaching the substrate, the channel structure having a side wall in contact with the first sacrificial layer, forming a gate line isolation groove through the memory stack structure and exposing the first sacrificial layer, introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line isolation groove to clean the surface of the first sacrificial layer, removing the first sacrificial layer and exposing the side wall, and then cleaning the side wall with the first active particles. The semiconductor device preparation method provided by the application can clean the surface of the first sacrificial layer and the side wall of the channel structure by using the first active particles, so that the problem that impurities existing on the surface of the first sacrificial layer and the side wall of the channel structure make the memory layer of the first sacrificial layer and the side wall of the channel structure difficult to be removed is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of semiconductor device. BACKGROUND

[0002] Before a side wall selective-epitaxial-growth (SWS) of a 3D NAND flash memory (3D NAND Flsah) memory channel structure is prepared, a sacrificial layer under a stack structure and a memory layer of a memory channel structure side wall in contact with the sacrificial layer need to be removed to expose a bottom silicon substrate surface and a channel of the memory channel structure side wall, and then the side wall selective-epitaxial-growth (SWS) of the memory channel structure can be grown.

[0003] However, impurities existing on the surface of the sacrificial layer and the memory channel structure side wall can make the sacrificial layer and the memory layer of the memory channel structure side wall not easy to be removed. SUMMARY

[0004] The present application provides a preparation method of semiconductor device, which effectively solves the problem that impurities existing on the surface of the sacrificial layer and the memory channel structure side wall can make the sacrificial layer and the memory layer of the memory channel structure side wall not easy to be removed.

[0005] In order to solve the above problems, the present application provides a preparation method of semiconductor device, which comprises:

[0006] forming a first sacrificial layer, a memory stack structure, and a channel structure passing through the memory stack structure and the first sacrificial layer and extending into the substrate, the channel structure having a side wall in contact with the first sacrificial layer on the substrate;

[0007] forming a gate line separation groove passing through the memory stack structure and exposing the first sacrificial layer;

[0008] introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line separation groove to clean the surface of the first sacrificial layer;

[0009] removing the first sacrificial layer and exposing the side wall; and,

[0010] cleaning the side wall with the first active particles.

[0011] Further preferably, the step of removing the first sacrificial layer specifically comprises:

[0012] introducing second active particles dissociated from carbon tetrafluoride and hydrogen into the gate line separation groove to remove the first sacrificial layer.

[0013] Further preferably, before the step of introducing the first active particles dissociated from the carbon tetrafluoride and the oxygen into the gate line trench, the method further comprises:

[0014] dissociating the carbon tetrafluoride and the oxygen in a preset environment at a first preset ratio;

[0015] wherein the preset environment is a nitrogen environment.

[0016] Further preferably, before the step of introducing the second active particles dissociated from the carbon tetrafluoride and the hydrogen into the gate line trench, the method further comprises:

[0017] dissociating the carbon tetrafluoride and the hydrogen in the same preset environment at a second preset ratio;

[0018] wherein the first preset ratio is greater than the second preset ratio.

[0019] Further preferably, the first active particles have a first etching selectivity of polysilicon to oxide and nitride, and the second active particles have a second etching selectivity of polysilicon to oxide and nitride, wherein the first etching selectivity is less than the second etching selectivity.

[0020] Further preferably, the channel structure comprises a channel layer and a storage layer arranged along a radial direction from inside to outside, and after the step of cleaning the sidewall with the first active particles, the method further comprises:

[0021] introducing an acidic liquid into the gate line trench to remove the storage layer on the radial projection of the sidewall, thereby forming a cavity below the storage stack structure;

[0022] growing a sidewall silicon epitaxial layer in the cavity.

[0023] Further preferably, a second sacrificial layer is arranged below the first sacrificial layer, and the step of cleaning the sidewall with the first active particles specifically comprises:

[0024] cleaning the surface of the sidewall and the second sacrificial layer with the first active particles.

[0025] Further preferably, the step of introducing the acidic liquid into the gate line trench to remove the storage layer on the radial projection of the sidewall specifically comprises:

[0026] introducing the acidic liquid into the gate line trench to remove the second sacrificial layer and the storage layer on the radial projection of the sidewall.

[0027] Further preferably, a protective layer is arranged on the inner wall of the gate line slot, the protective layer has a first thickness in the radial direction, and the storage layer has a second thickness in the radial direction, wherein the first thickness is greater than the second thickness.

[0028] Further preferably, the thickness of the second sacrificial layer is less than the thickness of the first sacrificial layer.

[0029] Further preferably, the first sacrificial layer and the second sacrificial layer are made of different materials, the first sacrificial layer is made of polysilicon, and the second sacrificial layer is made of oxide.

[0030] The present application has the following beneficial effects: the present application provides a semiconductor device preparation method, including: forming a first sacrificial layer, a storage stack structure, and a channel structure extending through the storage stack structure and the first sacrificial layer and into a substrate on a substrate, the channel structure having a sidewall in contact with the first sacrificial layer, forming a gate line slot through the storage stack structure and exposing the first sacrificial layer, introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line slot to clean the surface of the first sacrificial layer, removing the first sacrificial layer and exposing the sidewall, and then cleaning the sidewall with the first active particles. The semiconductor device preparation method provided by the present application cleans the surface of the first sacrificial layer and the sidewall of the channel structure using the first active particles, thereby avoiding the problem that impurities existing on the surface of the first sacrificial layer and the sidewall of the channel structure make the storage layer of the first sacrificial layer and the sidewall of the channel structure difficult to remove. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the description of each embodiment according to the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0032] Figure 1 is a flowchart of the semiconductor device preparation method provided by the first embodiment according to the present application.

[0033] Figures 2a to 2f is a process flowchart of the semiconductor device preparation method provided by the first embodiment according to the present application.

[0034] Figure 3 is a flowchart of the semiconductor device preparation method provided by the second embodiment according to the present application.

[0035] Figures 4a to 4fis a process flow diagram of a preparation method of a semiconductor device according to a second embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0037] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0038] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For a person of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0040] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0041] The present invention addresses the problem that impurities on the surface of the sacrificial layer and the sidewalls of the memory channel structure in existing semiconductor devices make it difficult to remove the sacrificial layer and the memory layer on the sidewalls of the memory channel structure. The embodiments of the present invention are used to solve this problem.

[0042] Please see Figure 1 , Figures 2a to 2f , Figure 1 A schematic flowchart of a method for fabricating a semiconductor device 100 according to a first embodiment of the present invention is shown. Figures 2a to 2f A schematic diagram of the process flow for fabricating a semiconductor device 100 according to a first embodiment of the present invention is shown.

[0043] like Figure 1 , Figures 2a to 2f As shown, the fabrication method of the semiconductor device 100 specifically includes the following process steps:

[0044] First formation step S101: A first sacrificial layer 120, a memory stack structure 130, and a channel structure 140 extending through the memory stack structure 130 and the first sacrificial layer 120 and into the substrate 110 are formed on the substrate 110. The channel structure 140 has a sidewall 140s in contact with the first sacrificial layer 120.

[0045] The second forming step S102 forms the gate line slot 150 through the memory stack structure 130, and exposes the first sacrificial layer 120.

[0046] The first cleaning step S103 introduces the first active particles, which are dissociated from carbon tetrafluoride and oxygen, into the gate line slot 150, to clean the surface 120s of the first sacrificial layer 120.

[0047] The first sacrificial layer removing step S104 removes the first sacrificial layer 120, and exposes the sidewall 140s.

[0048] The second cleaning step S105 cleans the sidewall 140s with the first active particles.

[0049] It should be noted that after the second forming step S102 is completed, the surface 120s of the first sacrificial layer 120 is usually covered with an oxide impurity, so that the first sacrificial layer 120 cannot be directly removed by etching process such as wet etching or dry etching. Therefore, before the first sacrificial layer removing step S104 is performed, the surface 120s of the first sacrificial layer 120 needs to be cleaned.

[0050] Further, in the first cleaning step S103, the fluorine particles in the first active particles mainly react with the oxide impurity to generate corresponding fluoride gas, so as to clean the surface 120s of the first sacrificial layer 120.

[0051] Specifically, the oxide impurity is mainly silicon dioxide SiO2, and the chemical reaction formula of the chemical reaction in this step is:

[0052] CF4+ SiO2+ O2= SiF4(g) + CO(g) + CO2(g)

[0053] It should be noted that the channel structure 140 includes the channel layer 141 and the memory layer 142 arranged along the radial direction from inside to outside. Before the sidewall epitaxial layer of the channel structure 140 is grown, the memory layer 142 located in the radial projection of the sidewall 140s needs to be removed, to expose the channel layer 141 and form a cavity below the memory stack structure 130, and then the sidewall epitaxial layer of the channel structure 140 is grown in the cavity. However, after the first sacrificial layer removing step S104 is completed, the sidewall 140s of the channel structure 140 is usually covered with a layer of polymer impurity, so that the memory layer 142 located in the radial projection of the sidewall 140s cannot be directly removed. Therefore, the sidewall 140s of the channel structure 140 needs to be cleaned.

[0054] Further, in the second cleaning step S105, the chemical bonds in the polymer impurities are broken and corresponding fluoride gas and oxide gas are generated by chemical reactions between the fluorine particles and oxygen particles in the first active particles and the polymer impurities, so as to clean the sidewall 140s of the channel structure 140.

[0055] Specifically, the polymer impurities are mainly polymers of C, F, Si and O (C-F-Si-O), and the chemical reaction formula of the chemical reaction in this step is as follows:

[0056] C-F-Si-O+F*+O2=SiF2(g)+SiF4(g)+CO(g)+CO2(g)

[0057] Further, before the first cleaning step S103 and the second cleaning step S105, carbon tetrafluoride CF4 and oxygen O2 are dissociated in a preset environment at a first preset ratio to generate the first active particles, for example:

[0058] The carbon tetrafluoride and the oxygen are dissociated in the preset environment at the first preset ratio;

[0059] Preferably, the preset environment is a nitrogen environment, in which the gas flow of nitrogen N2 can be about 50sccm, the pressure is about 300mT, and the temperature is about 100°C. Further, the first preset ratio is 0.2, and the first active particles have a first etching selectivity ratio of polysilicon Poly to oxide Ox and nitride SiN, and the first etching selectivity ratio is about 2:1:1.

[0060] Further, in the first sacrificial layer removing step S104, a wet etching process or a dry etching process can be used to remove the first sacrificial layer 120.

[0061] Further, after the second cleaning step S105, the following steps are further included:

[0062] An acidic liquid is introduced into the gate line slot 150 to remove the storage layer 142 located on the radial projection of the sidewall 140s, so as to form a cavity below the storage stack structure 130;

[0063] A sidewall silicon epitaxial layer is grown in the cavity.

[0064] Specifically, the acidic liquid can be hydrofluoric acid HF and phosphoric acid H3PO4.

[0065] Different from the prior art, the first embodiment according to the present application provides a preparation method of a semiconductor device 100, comprising: forming a first sacrificial layer 120, a memory stack structure 130, and a channel structure 140 extending through the memory stack structure 130 and the first sacrificial layer 120 and into a substrate 110 on the substrate 110, the channel structure 140 having a sidewall 140s in contact with the first sacrificial layer 120, forming a gate line isolation groove 150 through the memory stack structure 130 and exposing the first sacrificial layer 120, introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line isolation groove 150 to clean a surface 120s of the first sacrificial layer 120, removing the first sacrificial layer 120 and exposing the sidewall 140s, and then cleaning the sidewall 140s with the first active particles. The preparation method of the semiconductor device 100 provided by the first embodiment of the present application avoids the problem that impurities existing on the surface 120s of the first sacrificial layer 120 and the sidewall 140s of the channel structure 140 make the memory layer 142 of the first sacrificial layer 120 and the sidewall of the channel structure 120 not easy to be removed by cleaning the surface 120s of the first sacrificial layer 120 and the sidewall 140s of the channel structure 140 with the first active particles.

[0066] Please refer to Figure 3 、 Figures 4a to 4f , Figure 3 FIG. 2 shows a flowchart of a preparation method of a semiconductor device 200 according to the second embodiment of the present application, Figures 4a to 4f FIG. 3 shows a process flowchart of the preparation method of the semiconductor device 200 according to the second embodiment of the present application.

[0067] As shown in Figure 3 、 Figures 4a to 4f , the process steps of the second embodiment are substantially the same as those of the first embodiment, and specifically include:

[0068] A first forming step S201: forming a second sacrificial layer 260, a first sacrificial layer 220, a memory stack structure 230, and a channel structure 240 extending through the memory stack structure 230 and the first sacrificial layer 220 and into a substrate 210 on the substrate 210, the channel structure 240 having a sidewall 240s in contact with the first sacrificial layer 220;

[0069] A second forming step S202: forming a gate line isolation groove 250 through the memory stack structure 230 and exposing the first sacrificial layer 220;

[0070] A first cleaning step S203: introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line isolation groove 250 to clean a surface 220s of the first sacrificial layer 220;

[0071] A first removing step S204: the second active particles, which are dissociated from carbon tetrafluoride and hydrogen, are introduced into the gate line groove 250 to remove the first sacrifice layer 220 and expose the sidewall 240s;

[0072] A second cleaning step S205: the sidewall 240s and the surface of the second sacrifice layer 260 are cleaned by the first active particles;

[0073] A second removing step S206: the acid liquid is introduced into the gate line groove 250 to remove the second sacrifice layer 260 and the storage layer 242 located on the radial projection of the sidewall 240s, and form a cavity below the storage stack structure 230;

[0074] A sidewall silicon epitaxial layer growth step S207: the sidewall silicon epitaxial layer is grown in the cavity.

[0075] Different from the first embodiment described above, in the first removing step S204 of the present embodiment, the hydrogen particles in the second active particles chemically react with the first sacrifice layer 220 to generate silicon hydride particles on the surface 220s of the first sacrifice layer 220, and then the fluorine particles in the second active particles chemically react with the silicon hydride particles to generate silicon tetrafluoride gas and hydrogen, so as to achieve the purpose of removing the first sacrifice layer 220.

[0076] Specifically, the material of the first sacrifice layer 220 described above is polysilicon Poly, and the chemical reaction formula of the chemical reaction occurring in this step is:

[0077] Si + H* = Si-H* (surf)

[0078] Si-H* + F* = SiF4(g) + H2(g)

[0079] Further, before the first removing step S204 is performed, carbon tetrafluoride CF4 and hydrogen H2 need to be dissociated in a preset environment at a second preset ratio to generate the second active particles, for example:

[0080] Carbon tetrafluoride and hydrogen are dissociated in a preset environment at a second preset ratio;

[0081] The preset environment described above is the same as the preset environment in which the first active particles are obtained by dissociating carbon tetrafluoride CF4 and oxygen O2, and further, the second preset ratio is less than the first preset ratio described above, and the second preset ratio is 0.16, and the second active particles have a second etching selectivity for oxide Ox and nitride SiN, which is much greater than the first etching selectivity described above, and specifically, the second etching selectivity is about 700:1:1.

[0082] It is easy to understand that in the embodiment, the first cleaning step S203, the first removing step S204 and the second cleaning step S205 can be performed on the same process machine, simplifying the preparation process of the semiconductor device 200.

[0083] Further, in the embodiment, since the second etching selectivity is high, and the material of the first sacrificial layer 220 is the same as that of the substrate 210, a second sacrificial layer 260 is further arranged under the first sacrificial layer 220, so as to protect the substrate 210 in the first removing step S204 of removing the first sacrificial layer 220. Specifically, the material of the first sacrificial layer 220 is different from that of the second sacrificial layer 260, and the exemplary material of the second sacrificial layer 260 is oxide Ox, and the thickness of the second sacrificial layer 260 is less than that of the first sacrificial layer 220. It is easy to understand that in the second removing step S206, since the material of the second sacrificial layer 260 is different from that of the substrate 210, when the second sacrificial layer 260 is removed by the acidic liquid, the substrate 210 will not be damaged during the step.

[0084] Further, the polymer impurities described above can also be generated on the surface of the second sacrificial layer 260, so in the above-mentioned second cleaning step S205, the first active particles clean the sidewall 240s of the channel structure 240 and the surface of the second sacrificial layer 260.

[0085] Further, different from the first embodiment described above, in the second removing step S206 of the embodiment, the acidic liquid not only removes the storage layer 242 located on the radial projection of the sidewall 240s of the channel structure 240 to expose the channel layer 241, but also removes the second sacrificial layer 260.

[0086] Further, since the acidic liquid introduced in the second removing step S206 also damages the storage stack structure 230 in contact with the inner wall of the gate line isolation groove 250, the inner wall of the gate line isolation groove 250 is provided with a protective layer 251, and the protective layer 251 has a first thickness in the radial direction, and the storage layer 242 has a second thickness in the radial direction, wherein the first thickness is greater than the second thickness. Such thickness setting can make the protective layer 251 still have a certain thickness after the acidic liquid removes the storage layer 242 located on the radial projection of the sidewall 140s of the channel structure 240, thereby playing a role of protecting the storage stack structure 230 in contact with the inner wall of the gate line isolation groove 250. Specifically, the exemplary material of the protective layer 251 is oxide, nitride or a combination of the above-mentioned materials.

[0087] Different from the prior art, the second embodiment according to the present application provides a preparation method of a semiconductor device 200, comprising: forming a second sacrificial layer 260, a first sacrificial layer 220, a memory stack structure 230, and a channel structure 240 extending through the memory stack structure 230 and the first sacrificial layer 220 and into the substrate 210 on the substrate 210, the channel structure 240 having a sidewall 240s in contact with the first sacrificial layer 220, forming a gate line isolation groove 250 through the memory stack structure 230 and exposing the first sacrificial layer 220, introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line isolation groove 250 to clean the surface 220s of the first sacrificial layer 220, introducing second active particles dissociated from carbon tetrafluoride and hydrogen into the gate line isolation groove 250 to remove the first sacrificial layer 220 and expose the sidewall 240s, cleaning the sidewall 240s and the surface of the second sacrificial layer 260 with the first active particles, introducing an acidic liquid into the gate line isolation groove 250 to remove the second sacrificial layer 260 and the memory layer 242 located on the radial projection of the sidewall 240s, forming a cavity below the memory stack structure 230, and then growing a sidewall silicon epitaxial layer in the cavity. The preparation method of the semiconductor device 200 provided by the second embodiment of the present application avoids the problem that impurities existing on the surface 220s of the first sacrificial layer 220, the sidewall 240s of the channel structure 240, and the surface of the second sacrificial layer 260 make the first sacrificial layer 220, the memory layer 242 of the sidewall of the channel structure 220, and the second sacrificial layer 260 difficult to be removed, by using the first active particles to clean the surface 220s of the first sacrificial layer 220, the sidewall 240s of the channel structure 240, and the surface of the second sacrificial layer 260. Moreover, the use of the second active particles to remove the first sacrificial layer 220 not only improves the speed of the process step of removing the first sacrificial layer 220, but also simplifies the preparation process of the semiconductor device 200.

[0088] In addition to the above-mentioned embodiments, the present application can have other implementation manners. Any technical solution formed by equivalent replacement or equivalent substitution falls within the protection scope of the present application.

[0089] In summary, although the preferred embodiments of the present application have been disclosed as above, the above-mentioned preferred embodiments are not intended to limit the present application, and any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is defined by the scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: forming a first sacrificial layer, a memory stack structure, and a channel structure passing through the memory stack structure and the first sacrificial layer and extending into the substrate on the substrate, the channel structure having a sidewall in contact with the first sacrificial layer; forming a gate line slot passing through the memory stack structure and exposing the first sacrificial layer; introducing first active particles dissociated from carbon tetrafluoride and oxygen into the gate line slot to clean the surface of the first sacrificial layer; removing the first sacrificial layer and exposing the sidewall; and cleaning the sidewall with the first active particles.

2. The production method according to claim 1, characterized by, The step of removing the first sacrificial layer specifically comprises: introducing second active particles dissociated from carbon tetrafluoride and hydrogen into the gate line slot to remove the first sacrificial layer.

3. The preparation method according to claim 1, characterized in that, Before the step of introducing the first active particles dissociated from carbon tetrafluoride and oxygen into the gate line slot, the method further comprises: dissociating carbon tetrafluoride and oxygen in a preset environment at a first preset ratio; wherein the preset environment is a nitrogen environment.

4. The production method according to claim 3, characterized by, Before the step of introducing the second active particles dissociated from carbon tetrafluoride and hydrogen into the gate line slot, the method further comprises: dissociating carbon tetrafluoride and hydrogen in the same preset environment at a second preset ratio; wherein the first preset ratio is greater than the second preset ratio.

5. The preparation method according to claim 2, characterized in that, The first active particles have a first etching selectivity of polysilicon to oxide and nitride, and the second active particles have a second etching selectivity of polysilicon to oxide and nitride, wherein the first etching selectivity is less than the second etching selectivity.

6. The method of claim 1, wherein, The channel structure comprises a channel layer and a memory layer arranged radially from inside to outside, and after the step of cleaning the sidewall with the first active particles, the method further comprises: introducing an acidic liquid into the gate line slot to remove the memory layer located on the radial projection of the sidewall, forming a cavity below the memory stack structure; growing a sidewall silicon epitaxial layer in the cavity.

7. The production method according to claim 6, wherein A second sacrificial layer is further arranged below the first sacrificial layer, and the step of cleaning the sidewall with the first active particles specifically comprises: cleaning the surface of the sidewall and the second sacrificial layer with the first active particles.

8. The production method according to claim 7, characterized by, The step of introducing the acidic liquid into the gate line slot to remove the memory layer located on the radial projection of the sidewall specifically comprises: introducing the acidic liquid into the gate line slot to remove the second sacrificial layer and the memory layer located on the radial projection of the sidewall.

9. The preparation method according to claim 6, characterized in that, A protective layer is arranged on the inner wall of the gate line slot, the protective layer has a first thickness in the radial direction, and the memory layer has a second thickness in the radial direction, wherein the first thickness is greater than the second thickness.

10. The preparation method according to claim 7, characterized in that, The thickness of the second sacrificial layer is less than the thickness of the first sacrificial layer.

11. The preparation method according to claim 7, characterized in that, The materials of the first sacrificial layer and the second sacrificial layer are different, the material of the first sacrificial layer comprises polysilicon, and the material of the second sacrificial layer comprises oxide.

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