A method for manufacturing a shielded gate IGBT device

Abstract

The present invention belongs to the technical field of power semiconductor device design, and specifically relates to a method for manufacturing a shielded gate IGBT device, comprising: photolithography and etching to form a deep trench on a semiconductor substrate; forming a first source insulating layer at the bottom and sidewall of the deep trench, and filling the deep trench with a first source conductive material; isotropically etching the semiconductor substrate to form a top trench at the top of the deep trench; forming a gate dielectric layer in the top trench, and filling the gate conductive material; forming a second source conductive material, the second source conductive material is connected to the first source conductive material in the deep trench; forming a P-type body region, and forming an N-type source region in the P-type body region; forming an isolation dielectric layer, a contact hole and a front metal layer; forming a collector region and a back metal layer on the back. The method of the present invention is used to manufacture a shielded gate IGBT device, which solves the problem of contact hole misalignment, has a simple and controllable process, reduces manufacturing risks, and improves manufacturing yield.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to a method for manufacturing a shielded gate type IGBT device. Background Art

[0002] like Figures 1 to 9 FIG. 1 is a schematic diagram of the device structure in each step of the existing method; the existing shielded gate trench IGBT manufacturing method includes the following steps:

[0003] Step 1: Figure 1 As shown, a semiconductor substrate such as a silicon substrate 101 is provided, and a photolithography process is used to define a formation area of ​​a gate trench, and the gate trench includes a plurality of gate trenches. Before the photolithography process, a hard mask layer 201 is formed on the surface of the semiconductor substrate 101. After the photolithography process is used to define the formation area of ​​the gate trench, the hard mask layer 201 is etched to form a pattern structure of the hard mask layer 201 in which the formation area of ​​the gate trench is opened, and then the photoresist used in the photolithography process is removed.

[0004] Step 2: Figure 1 As shown, the semiconductor substrate 101 in the region where the gate trench is formed is first etched to form a top trench 202. The pattern structure of the hard mask layer 201 is directly used as a mask during the first etching.

[0005] Step 3: Figure 2 As shown, the top trench 202 is expanded by an isotropic etching process. After the isotropic etching process, the width of the top trench 202 is increased by the width formed by the isotropic etching on the basis of the definition of the photolithography process.

[0006] Step 4: Figure 3 As shown, a gate dielectric layer 102 is formed on the bottom surface and side of the top trench 202 and filled with a polysilicon gate 103. Preferably, the gate dielectric layer 102 is composed of an oxide layer and is formed by a thermal oxidation process. Figure 7 It is specially drawn and marked with a reference numeral 102.

[0007] Step 5: Figure 4 As shown, the polysilicon gate 103 and the gate dielectric layer 102 are etched, and the gate dielectric layer 102 and the polysilicon gate 103 after etching are located in the area formed by isotropic etching on both sides of the top groove 202; the width of the area enclosed by the polysilicon gate 103 on both sides of the top groove 202 is the same as the width defined by the photolithography process.

[0008] Step 6: Figure 4As shown, the semiconductor substrate 101 at the bottom of the top trench 202 is etched for the second time to form a bottom trench 203. The bottom trench 203, the area surrounded by the polysilicon gate 103 on both sides of the top trench 202, and the bottom trench 203 are vertically connected to form a through structure. The graphic structure of the hard mask layer 201 is directly used as a mask during the second etching.

[0009] Step 7: Figure 5 As shown, a source dielectric layer 104 is formed on the bottom surface and side surface of the through structure and filled with source polysilicon 105. Preferably, the source dielectric layer 104 is composed of an oxide layer.

[0010] Step 8: Figure 6 As shown, the source polysilicon 105 outside the gate trench region is removed; a gate structure is formed by the gate dielectric layer 102, the polysilicon gate 103, the source dielectric layer 104 and the source polysilicon 105 in each gate trench. At the same time, the source dielectric layer 104 outside the gate trench region and the hard mask layer 201 at the bottom are also removed.

[0011] Step 9: Figure 6 As shown, a channel region 106 doped with the second conductivity type is formed on the surface of the semiconductor substrate 101 between the gate structures; a source region 107 heavily doped with the first conductivity type is formed on the surface of the channel region 106; and the bottom of the channel region 106 is a drift region composed of the semiconductor substrate 101 doped with the first conductivity type.

[0012] Step 10: Figure 7 As shown, an interlayer film 108 and a contact hole 109 are formed; Figure 8 As shown, the front metal layer 110 is patterned to form a source and a gate. The contact hole 109 passes through the interlayer film 108. The polysilicon gate 103 is connected to the gate through the corresponding contact hole 109.

[0013] The source region 107 is connected to the source electrode through a corresponding contact hole 109. The top of the source polysilicon 105 is connected to the source electrode through a corresponding contact hole 9.

[0014] Step 11: forming a second conductivity type heavily doped drain region at the bottom of the drift region.

[0015] Step 12: Fig. 9 As shown, a back metal layer 111 is formed on the back side of the drain region and the back metal layer 111 constitutes a drain electrode.

[0016] In the actual processing, the formation of the gate contact hole may be misaligned due to the lithography misalignment accuracy and wafer warpage problems, such as Fig. 9 The existing shielded gate IGBT device shown, due to the particularity of its process steps, forms the gate through the difference in lateral length of two etches, so the gate width that can contact the upper gate contact hole is limited. In addition, since this type of IGBT substrate mostly uses a zone melting silicon substrate with soft characteristics, there will be serious contact hole misalignment problems. How to improve the gate contact hole misalignment problem and improve the mass production yield of this type of product has become a challenge in process and design. Summary of the invention

[0017] In order to solve the deficiencies of the prior art, the present invention provides a method for manufacturing a shielded gate IGBT device, which can solve the problem of gate contact hole misalignment caused by the prior art in manufacturing IGBT devices.

[0018] In order to solve the deficiencies of the prior art, the technical solution provided by the present invention is:

[0019] A method for manufacturing a shielded gate IGBT device, comprising:

[0020] Photolithographically etching a deep trench on a semiconductor substrate;

[0021] Forming a first source insulating layer at the bottom and sidewalls of the deep trench, and filling the deep trench with a first source conductive material;

[0022] isotropically etching the semiconductor substrate to form a top trench on the top of the deep trench;

[0023] forming a gate dielectric layer in the top trench and filling it with a gate conductive material;

[0024] forming a second source conductive material, wherein the second source conductive material is connected to the first source conductive material in the deep trench;

[0025] A P-type body region is formed, and an N-type source region is formed in the P-type body region;

[0026] An isolation dielectric layer and a contact hole are formed on the upper surface of the N-type source region, and a front metal layer is formed on the upper surface of the isolation dielectric layer;

[0027] A collector region is formed on the back side of the semiconductor substrate, and a back side metal layer is formed.

[0028] Furthermore, the photolithography and etching to form deep trenches on the semiconductor substrate comprises the following steps:

[0029] forming a first barrier layer on the semiconductor substrate, and etching the first barrier layer by photolithography to form an opening;

[0030] The semiconductor substrate is etched using the first barrier layer as a mask to form a deep trench.

[0031] Furthermore, the isotropic etching of the semiconductor substrate to form a top trench comprises the following steps:

[0032] forming a second barrier layer above the source conductive material in the deep trench;

[0033] The first source insulating layer is etched, and the top of the side wall of the retained first source insulating layer exceeds the top of the source conductive material.

[0034] The semiconductor substrate is isotropically etched using the first barrier layer, the second barrier layer and the retained first source insulating layer as masks to form a top trench.

[0035] Furthermore, the forming of the second source conductive material, wherein the second source conductive material is connected to the first source conductive material in the deep trench, comprises the following steps:

[0036] forming a third barrier layer on the semiconductor substrate, and etching the third barrier layer by photolithography to form an opening;

[0037] Using the third barrier layer as a mask, anisotropically etching the gate conductive material;

[0038] Depositing to form a second source insulating layer, and etching away the second source insulating layer above the source conductive material by anisotropic etching, leaving the second source insulating layer on the side wall;

[0039] Etching the second barrier layer until the first source conductive material is etched;

[0040] A second source conductive material is formed in the trench between the second source insulating layer and the first source conductive material on the sidewall, and the second source conductive material is connected to the second source insulating layer conductive material in the deep trench.

[0041] Furthermore, the first barrier layer (20), the second barrier layer (33), and the third barrier layer (50) are silicon nitride layers.

[0042] Furthermore, the first source insulating layer (31), the gate dielectric layer (41) and the second source insulating layer (53) are silicon oxide layers.

[0043] Beneficial effects of the present invention:

[0044] 1. The manufacturing method of the shielded gate IGBT device provided by the present invention fundamentally solves the problem of gate contact hole offset margin by filling the top trench with gate conductive material.

[0045] 2. The present invention forms a local source conductive material that penetrates the entire deep trench through the top trench by one-time photolithography, and the local area leaves enough offset margin for the source contact hole.

[0046] 3. The manufacturing method of the shielded gate IGBT device provided by the present invention has a simple and controllable process, which can reduce the manufacturing risk of the semiconductor shielded gate IGBT device and improve the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figures 1 to 9 It is a schematic cross-sectional structure diagram of the main structure in the manufacturing process of a semiconductor super junction device in the prior art;

[0048] Figures 10 to 22 It is a schematic cross-sectional structure diagram of the main structures in the manufacturing process of an embodiment of the manufacturing method of the shielded gate IGBT device provided by the present invention. DETAILED DESCRIPTION

[0049] The technical solution of the present invention will be fully described below in conjunction with the drawings in the embodiments of the present invention through specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present invention. At the same time, in order to clearly illustrate the specific implementation methods of the present invention, the schematic diagrams listed in the drawings of the specification magnify the thickness of the layers and regions described in the present invention, and the sizes of the listed graphics do not represent the actual sizes.

[0050] An embodiment of the present invention provides a method for manufacturing a shielded gate IGBT device, comprising the following steps:

[0051] First, if Fig.10 As shown, a first barrier layer 20 is formed on the provided N-type silicon substrate 10, and the first barrier layer 20 includes a silicon nitride layer. The position of the opening is defined by a photolithography process, and then the first barrier layer 20 is etched to form an opening 21 in the first barrier layer 20. The number of the openings 21 is determined by the specifications of the designed semiconductor shielded gate IGBT device. In the embodiment of the present invention, only two openings 21 are shown as an example.

[0052] Next, if Fig.11 As shown, the first barrier layer 20 is used as a mask, and a deep trench 30 is formed at the opening 21 of the silicon substrate 10 through an etching process.

[0053] Next, if Fig.12 As shown, a first source insulating layer 31 is formed in the deep trench 30 by a deposition oxide layer process. The first source insulating layer 31 is usually silicon oxide. Then, a source conductive material 32 is formed in the first source insulating layer 31 by a deposition and back etching process. The height of the source conductive material 32 does not exceed the surface of the silicon substrate. The source conductive material is usually polysilicon.

[0054] Next, if Fig.13 As shown, deposition and back etching are performed to form a second barrier layer 33 of a certain height, which is usually silicon nitride; a portion of the sidewall of the first source insulating layer 31 is etched away, and it is ensured that the top of the retained first source insulating layer 31 exceeds the top of the source conductive material 32.

[0055] Next, if Fig.14 As shown, the silicon substrate 10 is isotropically etched using the first barrier layer 20 , the second barrier layer 33 and the retained first source insulation layer 31 as masks to form a top trench 40 .

[0056] Next, if Fig.15 As shown, a gate dielectric layer 41 and a gate conductive material 42 are formed in the top trench 40. Usually, the gate dielectric layer 41 is silicon oxide grown by a thermal oxidation process, and the gate conductive material 42 is polysilicon.

[0057] Next, if Fig.16 As shown, a third barrier layer 50 is formed on the silicon substrate 10. The third barrier layer 50 may be a silicon nitride layer. The position of the opening is defined by a photolithography process, and then the third barrier layer 50 is etched to form an opening 51 in the third barrier layer 50. The shape of the opening 51 is determined by the specifications of the designed semiconductor shielded gate IGBT device, such as the plane Fig.17 As shown, in the embodiment of the present invention, only two opening shapes are exemplarily shown, and a platform 52 for subsequently opening a gate contact hole is left between the openings 51 .

[0058] Next, if Fig.18 As shown, the gate conductive material 42 is anisotropically etched using the third barrier layer 50 as a mask.

[0059] Next, if Fig.19 As shown, a second source insulating layer 53 is deposited, which is usually silicon oxide, and anisotropic etching is performed to etch away the second source insulating layer 53 at the bottom.

[0060] Next, if Fig. 20 As shown, the third barrier layer 50 and the second barrier layer 33 are etched away, usually by wet etching.

[0061] Next, if Fig.21 As shown, a second source conductive material 54 is deposited and etched back to connect with the first source conductive material 32 at the bottom of the deep trench 30 .

[0062] Next, if Fig. 22As shown, according to conventional processes, a P-type body region 60 is formed in an N-type silicon substrate, an N-type source region 61 is formed in the P-type body region 60, and then an isolation dielectric layer 62 and a contact hole 63 are formed on the upper surface of the N-type source region 61, and a front metal layer 64 is formed on the upper surface of the isolation dielectric layer. Then, conventional processes are performed on the back side of the IGBT to form a collector region on the back side of the semiconductor substrate 10, and a back metal layer 65 is formed to obtain the shielded gate IGBT device of the present invention.

[0063] The above specific implementation methods and examples are specific supports for the technical ideas of the present invention, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a shielded gate IGBT device, characterized in that: include: Photolithographically etching a deep trench (30) on a semiconductor substrate (10); Forming a first source insulating layer (31) at the bottom and sidewalls of the deep trench (30), and filling the deep trench (30) with a first source conductive material (32); isotropically etching the semiconductor substrate (10) to form a top trench (40) on the top of the deep trench (30); forming a gate dielectric layer (41) in the top trench (40) and filling it with a gate conductive material (42); forming a second source conductive material (54), wherein the second source conductive material (54) is connected to the first source conductive material (32) in the deep trench (30); forming a P-type body region (60), and forming an N-type source region (61) in the P-type body region; An isolation dielectric layer (62) and a contact hole (63) are formed on the upper surface of the N-type source region, and a front metal layer (64) is formed on the upper surface of the isolation dielectric layer (62); forming a collector region on the back side of the semiconductor substrate (10) and forming a back side metal layer (65); The gate contact hole is located between the source contact holes along the extension direction of the deep trench (30).

2. The method for manufacturing a shielded gate IGBT device according to claim 1, characterized in that: The process of photolithographically etching a deep trench (30) on a semiconductor substrate (10) comprises the following steps: forming a first barrier layer (20) on a semiconductor substrate (10), and etching the first barrier layer (20) by photolithography to form an opening (21); The semiconductor substrate (10) is etched using the first barrier layer (20) as a mask to form a deep trench (30).

3. The method for manufacturing a shielded gate IGBT device according to claim 2, characterized in that: The isotropic etching of the semiconductor substrate (10) to form a top trench (40) comprises the following steps: forming a second blocking layer (33) above the source conductive material (32) in the deep trench (30); Etching the first source insulating layer (31) so that the top of the side wall of the retained first source insulating layer (31) exceeds the top of the source conductive material (32); The semiconductor substrate (10) is isotropically etched using the first barrier layer (20), the second barrier layer (33) and the retained first source insulating layer (31) as masks to form a top trench (40).

4. The method for manufacturing a shielded gate IGBT device according to claim 3, characterized in that: The forming of the second source conductive material (54), wherein the second source conductive material (54) is connected to the first source conductive material (32) in the deep trench (30), comprises the following steps: forming a third barrier layer (50) on a semiconductor substrate (10), and etching the third barrier layer (50) by photolithography to form an opening (51); Using the third barrier layer (50) as a mask, anisotropically etching the gate conductive material (42); Depositing to form a second source insulating layer (53), and etching away the second source insulating layer (53) above the source conductive material (32) by anisotropic etching, leaving the second source insulating layer (53) on the side wall; Etching the second barrier layer (33) until the first source conductive material (32) is etched; A second source conductive material (54) is formed in the groove between the second source insulating layer (53) and the first source conductive material (32) on the side wall, and the second source conductive material (54) is connected to the second source insulating layer (53) and the conductive material (54) in the deep groove (30).

5. The method for manufacturing a shielded gate IGBT device according to claim 4, characterized in that: The first barrier layer (20), the second barrier layer (33) and the third barrier layer (50) are silicon nitride layers.

6. The method for manufacturing a shielded gate IGBT device according to claim 4, characterized in that: The first source insulating layer (31), the gate dielectric layer (41) and the second source insulating layer (53) are silicon oxide layers.

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