Display panel and display device

Abstract

The embodiment of the present invention discloses a display panel and a display device, wherein the display panel comprises: a single crystal silicon substrate, the single crystal silicon substrate comprises a first region and a second region; the first region comprises a single crystal silicon transistor circuit fabricated on the single crystal silicon substrate, the single crystal silicon transistor circuit is located in a signal circuit and a control circuit of the display panel, and the second region comprises a pixel circuit array of the display panel fabricated on the single crystal silicon substrate. The technical solution of the embodiment of the present invention, by preparing different types of circuits in the first region and the second region, its hybrid circuit can ensure that the voltage driving the LED light-emitting layer will not produce parasitic effects such as latch-up effects in the single crystal silicon substrate, and at the same time has the advantages of high speed and low power consumption of single crystal silicon integrated circuits, so that it is more suitable for manufacturing more miniature and high-performance LED display screens.

Description

Technical Field

[0001] Embodiments of the present invention relate to display technology, and more particularly to a display panel and a display device. Background Art

[0002] With the development and market promotion of OLED displays for wearable display devices for augmented reality and virtual reality, the technical requirements for display panels in OLED microdisplays used for these two purposes are becoming increasingly higher. In particular, the resolution of display panels has been expanded to an ultra-high resolution of 5000ppi, and the size of a single pixel is close to 5 microns. It is foreseeable that the size of a single pixel may approach 1 micron in the near future, so all transistors in the internal circuits of all pixels must be sub-micron level.

[0003] Figure 1 This is a schematic diagram of the structure of an OLED display made on a silicon wafer, also known as a silicon-based OLED. Inside and on the surface of the silicon substrate 010, similar to ordinary CMOS devices, heavily doped diffusion regions 021 of the source and drain of the transistor are made, and the source metal or drain metal 022 made later makes ohmic contact with the source or drain diffusion layer through the via hole in the gate oxide layer 031. A polysilicon gate 023 is made on the gate oxide layer 031 to control the conduction state of the transistor. At the same time, other components in the pixel are also made on the silicon wafer, such as the switching transistor for reset, the transistor for compensating voltage deviation, and the storage capacitor. In addition, the scanning line, data line and power line that control the pixel are also made on the silicon substrate through the usual semiconductor integrated circuit process. These pixel matrices made on the silicon wafer, including transistors, capacitors and wiring for various purposes, are usually called the display's driving backplane.

[0004] The manufactured driving backplane needs to be covered with a passivation layer 032, and then a thicker interlayer insulating film is covered thereon by evaporation or coating. Then the source of the transistor driving the OLED is connected to the upper OLED anode metal layer 041 through a via and a conductive connection column 024. The anodes of each pixel are isolated by a pixel definition layer (PDL) 033. PDL033 can also avoid large leakage current or electrical breakdown short circuit between the cathode 042 on the top of the OLED caused by the strong fringe electric field of the anode metal 041.

[0005] On top of the anode array and PDL033 grid, the various functional layers of the OLED and the final cathode metal layer 042 are continuously evaporated in a vacuum film forming device. For simplicity without losing generality, Figure 1Only the simplest three-layer OLED structure is drawn here, which includes a hole injection and transport layer 043 in contact with the anode metal. In contact with the top cathode metal is the electron injection and transport layer 044. Sandwiched in the middle is the OLED light-emitting layer 045. Above the cathode is usually a planarization layer 034, the purpose of which is to eliminate the surface unevenness caused by the different thicknesses of the anode metal and PDL, so that the color filter film produced later can be evenly coated on the flat surface. Above the planarization layer 034 are color filters of different colors, such as the red filter 051, and the black film between them that absorbs light to reduce color mixing, which is usually called the black matrix BM.

[0006] As mentioned above, in order to make a more miniaturized OLED display, the transistors in each pixel are close to the sub-micron level. All CMOS semiconductor integrated circuits manufactured in IC foundries must comply with the rule of scale reduction, that is, as the size of the transistor on the chip plane is reduced, its depth direction size must also be reduced accordingly, such as the ion implantation depth and diffusion depth of the doping region, the thickness of the gate insulation film must also be reduced, and the driving voltage of the transistor must also be reduced accordingly. However, when driving the OLED film, it is necessary to apply a sufficiently high voltage to inject enough current into the organic film with a very low carrier mobility to stimulate a large number of photons. In order to obtain sufficient image brightness difference, that is, the number of gray levels of the image or the dynamic range of the image, the amplitude of the voltage driving the OLED needs to be at least 5V. In order to increase the output luminous flux of the OLED, one technology is to stack two OLED films together, so as to expect to emit nearly twice the luminous flux on the same luminous area. However, the increase in the overall thickness of the OLED film will inevitably require a larger driving voltage at both ends, and even a bias voltage close to 10V will be required.

[0007] However, such high voltages will inevitably lead to various problems for submicron-sized transistors. In particular, they include leakage current between the source and drain of the transistor in the threshold or subthreshold working state, leakage current between the source and drain diffusion layer 021 and the silicon substrate caused by the reverse bias of the PN junction, gate leakage current through the gate oxide layer, transistor turn-off barrier reduction (DIBL) caused by the drain voltage, and various parasitic effects caused by lateral leakage current and electric field inside the silicon chip. Among these parasitic effects, the most likely and most harmful is the latch-up effect. This is a low-impedance parasitic leakage current path generated by the mutual coupling of parasitic PNP and NPN bipolar BJTs between the power supply and the ground potential of the silicon chip substrate, thereby generating additional large currents between the power supply and the silicon chip substrate. The higher the integration of the IC, the higher the probability of latch-up effect in the silicon chip body. This large current not only increases power consumption, but in extreme cases may also cause the chip to burn.

[0008] In order to solve this problem in high-resolution silicon-based OLEDs, eMagin (US20210183314A1) proposed a structure and method to fabricate high-voltage driven transistors and low-voltage driven transistors on two different chips, of course, their manufacturing processes and reduction scales are different, and then stack the two chips together, and use connecting metal columns to connect the relevant electrode arrays. However, the biggest challenge of this method is how to accurately and perfectly connect the tens of millions of electrode points on the upper and lower chips. Considering that the two chips are made in different process flows, the dimensional deviation caused by the thermal expansion and contraction of the chips during the manufacturing process, the accumulation of deviations in multiple photolithography processes, and the warping of the silicon wafer surface due to tension will all cause this attempt at alignment and conductive connection to fail.

[0009] Another way is to consider that since the above effects all occur in the body of the silicon chip, the transistors that are easily affected by leakage current are made of thin film transistors (TFTs), which can avoid the above leakage current and other parasitic effects in the diffusion area between the silicon substrate. In particular, when people found that the leakage current between the source and drain of oxide semiconductors, such as IGZO TFTs, is much smaller than that of polysilicon or amorphous silicon TFTs, it was proposed to use high-mobility polysilicon TFTs as transistors to drive OLEDs in large-area display driver backplanes, and use oxide semiconductor TFTs as switch transistors to control data writing, such as CN103715196A and CN105931988B. Unfortunately, however, polysilicon TFTs are not suitable for making highly integrated CMOS data signal processors and drivers for driving OLED panels. On the one hand, due to the defect states between and on the surface of polysilicon grains, when the size of the transistor and the grain size are at the same order of magnitude, the characteristics of the transistor will have greater non-uniformity. On the other hand, there are shortcomings from TFT itself, such as self-heating effect and floating body effect. The current transmission channel of TFT is enclosed by two layers of insulating film, and its thermal conductivity is almost one percent of that of the internal transistor. The heat generated by the internal current is difficult to conduct away. When the device works at an extremely high frequency and has a large current density, the rapid temperature rise of the device leads to a decrease in performance such as carrier mobility and accelerated aging of OLED materials. For example, the operating frequency of the transistors in the driver module of a 2K×2K display panel is at least 2,000 times higher than that of the transistors in the display area. The floating substrate effect will reduce the antistatic ability of TFT devices by about half, making them more susceptible to ESD damage. These adverse effects will become more harmful as the integration of semiconductor devices increases. However, we know that the silicon-based OLED backplane not only has an array of OLED pixels, but also a driver module of the driver circuit and signal processing circuit located around the OLED display area. Due to space limitations and power consumption, the driver module requires a higher integration than the pixel array, such as transistors of about tens of nanometers densely gathered on a small chip. Only in this way can a high-speed chip module with rich signal processing functions be manufactured within an extremely small display area frame, thereby achieving an extremely small frame or even borderless micro-display.

[0010] Therefore, how to overcome the above technical difficulties and design and manufacture a high-resolution and extremely small frame OLED micro display with a higher yield rate is the goal that the present invention strives to achieve. Summary of the invention

[0011] The present invention provides a display panel made on a single crystal silicon substrate through an embodiment, and a first area and a second area are set on the single crystal silicon substrate. An integrated circuit of a single crystal silicon transistor is prepared on the single crystal silicon substrate in the first area for signal generation, such as a digital-to-analog conversion circuit and a related timing control circuit. The second area includes a pixel circuit array of a display panel made on the single crystal silicon substrate, and the pixel circuit array includes a plurality of compound semiconductor thin film transistors. A lower driving voltage is used in the highly integrated single crystal silicon CMOS circuit in the first area, thereby having the advantages of high speed and low power consumption, and also avoiding the problem of heat conduction of the insulating substrate when the compound semiconductor thin film transistor circuit is running at high speed. In the pixel circuit of the compound semiconductor thin film transistor, a higher voltage can be used according to the threshold voltage and IV characteristics of the OLED light-emitting layer, thereby having the advantages of a large dynamic range and high brightness, and also avoiding the problems such as the latch effect and the dark current in the body caused by the high voltage driving the OLED light-emitting layer in the single crystal silicon body.

[0012] In another embodiment, a pixel circuit array of a mixed material including a compound semiconductor thin film transistor and a single crystal silicon transistor is prepared in the second region, and an organic light emitting diode thin film and an inorganic light emitting diode microchip are superimposed on the pixel circuit array, and the compound semiconductor thin film transistor drives the organic light emitting diode thin film, and the single crystal silicon transistor drives the inorganic light emitting diode microchip. This structure of mixing two driving circuits and two light emitting devices has the characteristics of driving different light emitting materials or components with low voltage and high voltage respectively, thereby having the performance freedom of optimizing the color and life of different light emitting materials and the freedom of the driving voltage range.

[0013] In the process of manufacturing the above-mentioned single-crystal silicon integrated circuits and compound semiconductor thin-film transistor pixel circuits, the same process can be applied to two areas at the same time. For example, the polysilicon gates of transistors in the two areas can be made at the same time, and ion implantation and diffusion can also be carried out simultaneously, thereby simplifying the manufacturing process of hybrid integrated circuits.

[0014] The embodiment of the present invention can also ensure that the voltage driving the light-emitting layer does not produce adverse effects such as latch-up effect in the body of the single-crystal silicon substrate by changing the position of the scanning circuit. The scanning circuit can be located in the first area or the second area. When the scanning circuit is located in the first area, it includes a plurality of single-crystal silicon transistors; when the scanning circuit is located in the second area, it includes a plurality of thin-film transistors. At the same time, it is located on one side or both sides of the pixel circuit.

[0015] In another embodiment, the present invention further provides a display device, including the above-mentioned display panel.

[0016] The display panel provided by the embodiment of the present invention includes a single crystal silicon substrate, and the single crystal silicon substrate includes a first area and a second area; the first area includes a single crystal silicon transistor circuit made on the single crystal silicon substrate, and the single crystal silicon transistor can form a signal circuit and a control circuit of the display panel, and the second area includes a thin film transistor of a compound semiconductor made on the single crystal silicon substrate, and the thin film transistor is located in the pixel circuit array of the display panel. While the single crystal silicon transistor on the single crystal silicon substrate is retained in the display panel, a thin film transistor of a compound semiconductor is prepared in another area, so that the signal circuit and the control circuit of the display panel and the pixel circuit of the display panel are two different circuits, and the hybrid circuit can ensure that the voltage driving the LED light-emitting layer will not produce parasitic effects such as latch-up effect in the single crystal silicon substrate, and at the same time, it has the advantages of high speed and low power consumption of single crystal silicon integrated circuits, thereby improving the quality of displayed images. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0018] Figure 2 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 3 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of an OLED pixel equivalent circuit provided by an embodiment of the present invention;

[0021] Figure 5 A schematic diagram of another OLED pixel equivalent circuit provided by an embodiment of the present invention;

[0022] Figure 6 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0023] Figure 7 A schematic diagram of an OLED pixel equivalent circuit provided by an embodiment of the present invention;

[0024] Figure 8 A schematic diagram of a local equivalent circuit of an OLED pixel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0026] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second" and the like are only used for descriptive purposes and do not indicate any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0027] In order to solve the problems mentioned in the background technology, an embodiment of the present invention provides a display panel, which can be applied to a wearable display device of AR or VR. Figure 2 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, referring to Figure 2 As shown, a display panel 1 provided by an embodiment of the present invention includes: a single crystal silicon substrate 10, and the single crystal silicon substrate 10 includes a first area 101 and a second area 102. The first area 101 includes a single crystal silicon transistor 110 made on the single crystal silicon substrate 10, and the second area 102 includes a plurality of compound semiconductor thin film transistors 120 made on the single crystal silicon substrate 10. The signal circuit and the control circuit located in the display panel 1 include the single crystal silicon transistor 110, and the pixel circuit array located in the display panel 1 includes the thin film transistor 120. The pixel circuit of the display panel 1 provides a sufficient voltage to the light-emitting layer 20 to meet its light-emitting state, while avoiding the generation of parasitic effects and self-heating effects that may damage the display panel.

[0028] The single crystal silicon substrate 10 includes a first region 101 and a second region 102. The first region 101 is used to make a single crystal silicon transistor 110 on the single crystal silicon substrate 10 through a doping process. In the second region 102, a high-quality silicon oxide layer 121 is formed on the surface of the single crystal silicon substrate 10 by high-temperature oxidation of the single crystal silicon substrate 10, or silicon oxide is deposited on the surface of the single crystal silicon substrate 10 by chemical vapor deposition, or low-energy ion implantation is used, and high-temperature annealing is performed after oxygen atoms are implanted to form a high-quality silicon oxide layer 121 on the surface of the single crystal silicon substrate 10. A compound semiconductor thin film transistor 120 is prepared on the silicon oxide layer 121.

[0029] Among them, Figure 2As shown, the single crystal silicon transistor 110 manufactured by the doping process on the first region 101 is a part of the signal circuit and the control circuit. The specific structure of the signal circuit and the control circuit and other unspecified specific structures are the same as those of the control circuit. Figure 1 The same as in the above, no further details are given here. The thin film transistor 120 made in the second area 102 is part of the pixel circuit. The display panel 1 includes a pixel circuit array for providing voltage to the light-emitting layer 20. The thin film transistor 120 made in the second area 102 provides sufficient voltage to the light-emitting layer 20, which can increase the high luminous flux emitted from the light-emitting layer 20 and enhance the display effect of the display panel 1. The signal circuit and the control circuit are made in the first area 101, and the pixel circuit array is made in the second area 102. The display panel 1 of the hybrid circuit can ensure the required voltage of the light-emitting layer 20, while avoiding the parasitic effect and latch effect in the single crystal silicon substrate 10 when only the single crystal silicon transistor 110 is made, and avoiding the non-uniformity and self-heating effect of the thin film transistor 120 made of only compound semiconductors, etc., so as to facilitate the manufacture of a more miniature display screen and ensure the display effect.

[0030] In summary, the display panel provided by the embodiment of the present invention, by retaining the single crystal silicon transistors on the single crystal silicon substrate in the display panel, prepares the compound semiconductor thin film transistors in another area, so that the signal circuit and control circuit of the display panel and the pixel circuit of the display panel are two different circuits. The hybrid circuit can ensure that the voltage driving the LED light-emitting layer will not produce parasitic effects such as latch-up effect in the single crystal silicon substrate, and at the same time has the advantages of high speed and low power consumption of single crystal silicon integrated circuits, so it is more suitable for manufacturing more miniaturized and high-performance LED display screens.

[0031] refer to Figure 2 As shown, the display panel 1 provided in the embodiment of the present invention includes a light-emitting layer 20 superimposed on a pixel circuit array, and its light-emitting state is controlled by the pixel circuit array. The light-emitting layer 20 can be a light-emitting layer of an organic light-emitting diode OLED, including: an OLED anode metal 21, an OLED hole injection layer 22, an OLED light-emitting layer 23, an OLED electron injection layer 24 and an OLED cathode metal 25. In a specific implementation, the light-emitting layer can include at least one of an organic light-emitting diode film, an inorganic light-emitting diode chip, nano-shaped light-emitting particles, and an inorganic electroluminescent film.

[0032] Taking OLED as an example, the light-emitting layer 20 includes: OLED anode metal 21, OLED hole injection layer 22, OLED light-emitting layer 23, OLED electron injection layer 24 and OLED cathode metal 25. The OLED hole injection layer 22 and the OLED electron injection layer 24 inject the provided electrons and holes into the OLED light-emitting layer, and the OLED light-emitting layer emits light after the holes and electrons are recombined. The driving voltage is provided by the pixel circuit to control the light-emitting state of the light-emitting layer 23. Ensuring the light-emitting state of the light-emitting layer 20 can improve the display effect of the display panel 1.

[0033] In another embodiment of the invention, as shown in FIG. Figure 3 As shown, a pixel circuit array of a mixed material including a compound semiconductor thin film transistor and a single crystal silicon transistor is prepared in the second area on the single crystal silicon substrate, and an organic light emitting diode thin film and an inorganic light emitting diode microchip are superimposed on the pixel array, and the compound semiconductor thin film transistor drives the organic light emitting diode thin film, and the single crystal silicon transistor drives the inorganic light emitting diode microchip. This structure of mixing two driving circuits and two light emitting devices has the characteristics of driving different light emitting materials or components with low voltage and high voltage respectively, thereby having the performance freedom and driving voltage range freedom of optimizing the color and life of different light emitting materials. Since the threshold voltages of organic and inorganic LEDs for starting to emit light are different, the rising curves of the current and voltage of the LEDs are also different. Mixing the two provides more freedom in designing and changing performance, such as expanding the dynamic range of brightness. Another embodiment of expanding the application according to the idea of ​​the present invention is to connect OLED and inorganic LED in series and use the same pixel circuit to drive the combination and driving method.

[0034] The inorganic light-emitting diode microchip can be a so-called Micro-LED chip transferred from a GaN epitaxial wafer by a mass transfer method. For the Micro-LED transferred to the monocrystalline silicon driving transistor and electrically connected to its source, it can be connected to the anode or cathode of the Micro-LED according to the actual circuit and application requirements of the monocrystalline silicon.

[0035] exist Figure 3 On the display panel of the hybrid light-emitting components driven by the hybrid circuit backplane shown, different color filters can be superimposed as needed, or the color filters can be omitted according to the luminous colors of the organic and inorganic light-emitting LEDs themselves, thereby greatly improving the luminous efficiency.

[0036] In the following embodiments, the display panel is an OLED display panel as an example for description. Figure 4 A schematic diagram of an OLED pixel equivalent circuit provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the pixel circuit array includes a plurality of pixel circuits ( Figure 4 Only one pixel circuit is schematically shown in the figure, and multiple pixel circuits are distributed in the display area of ​​the display panel in an orthogonal arrangement of rows and columns (not shown in the figure). Each pixel circuit includes at least one storage capacitor Cst, a thin film transistor T1 for inputting a signal voltage, and a thin film transistor T2 for OLED.

[0037] The pixel circuit includes a storage capacitor Cst, a thin film transistor T1 and a thin film transistor T2. The thin film transistor T1 is used for inputting a signal voltage, the storage capacitor Cst is used for storing the input signal voltage, and the thin film transistor T2 is used for driving the OLED pixel circuit array. The pixel circuits include a plurality of pixel circuits arranged in rows and columns orthogonally, all including the above structure, thereby improving the display effect of the display panel.

[0038] Specifically, the voltage provided to the thin film transistor T2 is relatively high, such as 5V or 7.5V, and the thin film transistor T2 is manufactured in the second region 102 . Figure 5 Another schematic diagram of an OLED pixel equivalent circuit provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, each pixel circuit may include and a single crystal silicon transistor T1'. The driving voltage of the single crystal silicon transistor T1' is relatively small, so it may be manufactured in the first area 101. In other embodiments, the pixel circuit may be a 7T1C circuit including 7 transistors and 1 capacitor, and may include both thin film transistors and single crystal silicon transistors, which is not limited in the embodiment of the present invention. The storage capacitor Cst is manufactured in the second area 102 in the embodiment provided in the present invention, but in other embodiments, it may also be placed in the first area 101, and the embodiment of the present invention does not specifically limit the distribution position of the storage capacitor Cst. Combined with Figure 2 As shown, the OLED anode metal 21 is directly made above the first area 101 and the second area 102, and the OLED cathode metal 25 is connected to the external constant voltage power supply VCA. According to the OLED material and structure used, VCA can vary between 0V and -10V. The difference between the voltage of VCA and the voltage of the thin film transistor T2 is the voltage clamped at both ends of the light-emitting layer 20. When the light-emitting layer 20 is not allowed to emit light, the gate of the thin film transistor T2 is written with a signal voltage less than the threshold voltage, so that the thin film transistor T2 is in a cut-off state, and the source potential of the thin film transistor T2 will be close to the potential of the cathode metal 25 of the OLED, and the drain of the thin film transistor T2 is always at a potential of about +5V of VDD. Therefore, the operating voltage of the thin film transistor T2 is far beyond what a deep submicron-level in vivo single-crystal silicon transistor can withstand, but it is no problem at all for the compound semiconductor thin film transistor made on the silicon oxide layer.

[0039] For large-area display screens, current manufacturing technology and cost requirements make it impossible to use single-crystal silicon wafers as substrates. Only thin-film transistor switch transistors and transistors driving OLEDs can be manufactured on insulators such as glass, that is, single-crystal silicon T1' and thin-film transistor T2 mentioned in this embodiment. Considering that the current between the source and drain of polycrystalline silicon thin-film transistors is relatively large, thin-film transistors are used as switch transistors in the prior art, and polycrystalline silicon with higher mobility is used as drive transistors. However, in the embodiments of the present invention, single-crystal silicon is used to make switch transistors and other transistors that do not directly drive OLEDs. Its perfect single-crystal silicon crystal structure and high-temperature oxidized gate silicon oxide make the defect state density in the body and interface of the semiconductor extremely low, so the leakage current generated is also much smaller than that of polycrystalline silicon thin-film transistors manufactured at low temperatures. This is one of the reasons why the present invention can use single-crystal silicon transistors as switches within pixels.

[0040] Specifically, not only can a pixel circuit be divided into a first region 101 and a second region 102 in the body, and different transistors and circuits can be manufactured thereon respectively, but also the same can be done on an entire silicon-based display screen. Figure 6 Another schematic diagram of an OLED pixel equivalent circuit provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, it is divided into two areas. The second area 102 completely covers the display area of ​​the pixel array, the first area 101A is the area for inputting signals and processing signals, and the first area 101B is the row scanning circuit of the pixel array. The transistors, capacitors, metal wirings, etc. in all pixels in the second area 102 are made on the compound semiconductor of the thin film transistor. It can achieve the maximum local use of the advantages of the highly integrated single-crystal silicon CMOS circuit at the level of more than ten nanometers in the first area 101A and the first area 101B, and at the same time, the advantages of low leakage current, low parasitic capacitance, and low power consumption of the thin film transistor are also brought into play in the second area 102. The disadvantage of only making thin film transistor devices is that they are easily damaged by static electricity, especially for large-size thin film transistor arrays made on glass substrates and other insulating substrates. In the manufacturing process, the transistors and various wirings are basically in an electrically suspended state, and before the driver IC is bonded to the display panel, they are very susceptible to ESD damage. In various embodiments of the present invention, all scan lines, data lines and power lines are connected to the single crystal silicon substrate circuit of the first area 101A or the first area 101B during the process, so that various ESD protection measures of the single crystal silicon integrated circuit can be easily utilized in the manufacturing process engineering to protect the entire silicon-based OLED microdisplay.

[0041] At the same time, the shift register for generating row scan pulses in the first area 101B can also be made of thin film transistors. The row scan circuit can handle the generation and output of higher voltage amplitudes. In addition, the row scan area can also be placed on both sides of the display array, not just one side.

[0042] The scan data lines inside the OLED pixel can be distributed in the first area 101 or the second area 102. Figure 4 As shown, the row scanning circuit VA for scanning the pixel circuit array in the first area 101 is located on one side or both sides of the pixel circuit layer, and the row scanning circuit VA includes a plurality of single crystal silicon transistors. Figure 5 As shown, the row scanning circuit VA in the second area 102 for scanning the pixel circuit array is located on one side or both sides of the pixel circuit layer, and the row scanning circuit VA includes a plurality of thin film transistors.

[0043] Among them, the scanning circuit VA includes a control pulse voltage A i The scan line VAi and the adjacent control pulse voltage are A i-1 The scanning line VAi-1 and the transistor driving the scanning line VA (not shown in the figure), and so on. The scanning pulse voltage VA i Controls the opening and closing states of the thin film transistor T1, the thin film transistor T2 and the single crystal silicon transistor T1. Specifically, Figure 4 As shown, the scanning circuit VA is arranged in the first area 101, and the scanning circuit VA includes a plurality of single crystal silicon transistors. The scanning circuit VA is located on one side of the pixel circuit layer. Through the scanning operation, the scanning circuit VA is located on both sides of the pixel circuit layer. Figure 5 As shown, the scanning circuit VA is arranged in the second area 102. The scanning circuit VA includes a plurality of thin film transistors. The scanning circuit VA is located at one side of the pixel circuit layer. Through the scanning operation, the scanning circuit VA is located at both sides of the pixel circuit layer.

[0044] Figure 7 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention, such as Figure 7 As shown, the compound semiconductor 123 in the thin film transistor 120 includes one of the following materials: metal oxide semiconductor material, II-IV compound semiconductor material and III-V compound semiconductor material. Among them, the metal oxide semiconductor material includes ZnO, CdO, MgO or IGZO, the II-IV compound semiconductor material includes ZnSe, ZnS, ZnTe, CdSe, CdTe or CdS, and the III-V compound semiconductor material includes GaAs, GaP, InAs or InP.

[0045] Among them, Figure 7As shown, the compound semiconductor 123 in the thin film transistor 120 provided in this embodiment is a thin film lacking oxygen atoms produced by hydrogen plasma treatment of an oxide semiconductor in a self-calibration manner using a top gate 127 as a mask. The compound semiconductor 123 can be made of metal oxide semiconductor materials, II-IV compound semiconductor materials, and III-V compound semiconductor materials. The compound semiconductor 123 can be prepared using a variety of materials, and the compound semiconductor 123 has a high conductivity, so that it can form a good ohmic contact with the source and drain metal 128, and can also provide or receive current to the channel region 124.

[0046] refer to Figure 2 As shown, the signal circuit and the control circuit include a single-crystal silicon transistor 110 with a polysilicon gate, the pixel circuit array includes a thin-film transistor 120 with a polysilicon gate, and the polysilicon gates of the single-crystal silicon transistor 110 and the thin-film transistor 120 are both manufactured synchronously.

[0047] Among them, the signal circuit and the control circuit include a single crystal silicon transistor 110 with a polysilicon gate, and the pixel circuit layer includes a thin film transistor 120 with a polysilicon gate. The gate of the hybrid transistor included in the display panel 1 can be manufactured simultaneously using the same process. At the same time, it can also be made separately or with different conductive materials, such as polysilicon or metal copper alloy. The advantage of using polysilicon is that it can be protected by insulating coverage through oxidation, while if metal is used, an additional process of evaporating an insulating film is required. The contact metal of the source and drain of the single crystal silicon transistor 110 and the thin film transistor 120 can be deposited synchronously or separately by plasma sputtering.

[0048] Figure 8 A schematic diagram of a local equivalent circuit of an OLED pixel provided by an embodiment of the present invention. Figure 7 and Figure 8 As shown, the display panel 1 provided by the embodiment of the present invention includes a dual-gate thin film transistor 120, and the dual-gate thin film transistor 120 includes a silicon oxide layer 121, a bottom gate 126, a top gate 127, a bottom gate insulating layer 122, a top gate insulating layer 125, a compound semiconductor 123, a channel region 124, and a source-drain metal 128. At the same time, the thickness of the insulating layer 122 of the bottom gate is less than the thickness of the insulating layer 125 of the top gate.

[0049] Specifically, in an embodiment of the present invention, the bottom gate 126 will serve as the main control gate of the driving thin film transistor. The top gate 127 can be connected inside the pixel circuit through a via hole, thereby forming a dual-gate thin film transistor 120. The top gate 127 is in an isolated and electrically floating state after manufacturing. That is, during the manufacturing process, the top gate 127 is an important plasma treatment mask, which can block light from entering the oxide semiconductor film when the display panel is working, thereby reducing or avoiding light-induced leakage current. Figure 8 As shown, the pixel equivalent circuit diagram of the present invention may still use the symbol or graphic of a single gate transistor, but it can be understood that the thin film transistors in the display area can be used as needed. Figure 8 The dual-gate thin film transistor 120 shown, or the top gate metal is placed in an electrically floating state. The bottom gate 126 of the dual-gate thin film transistor 120 is made of polysilicon, and can be deposited on the substrate at the same time as the polysilicon gate of the transistor. The top gate 127 is made of an opaque metal material, which can block light and also block the deterioration of the performance of the metal oxide film below by water vapor and hydrogen ions. The bottom gate insulating layer 122 is a denser and less defect-dense insulating film formed by high-temperature oxidation or nitridation of the imaged polysilicon, and is most suitable as an insulating film for driving the main control gate of the dual-gate thin film transistor 120. The top gate insulating layer 125 is deposited by magnetron sputtering or other methods at room temperature or a relatively low film forming temperature (less than 350 degrees Celsius), in order to ensure the stability of the metal oxide film that is not resistant to high temperatures. Therefore, its density and defect state density are not as good as the bottom gate insulating layer 122 oxidized at high temperature. In order to ensure a low gate leakage current, the thickness of the top gate insulating layer 125 is greater than the thickness of the bottom gate insulating layer 122, for example, the thickness of the top gate insulating layer 125 is greater than 500nm. At the same time, the thickness of the silicon oxide layer 121 is at least 50nm thick. The thicker silicon oxide layer 121 can significantly reduce the parasitic capacitance and leakage current between the bottom gate 126 of the dual-gate thin film transistor 120 and the monocrystalline silicon substrate 10 in the body, both of which directly or indirectly increase the driving power consumption of the OLED display panel.

[0050] In this embodiment, the channel length of the thin film transistor 120 is less than 0.5 micrometers.

[0051] Among them, the channel length can be N-type or P-type doped as needed above the original doping concentration of the silicon substrate, so as to obtain NMOS FET or PMOS FET, or a symmetrical complementary MOS FET with both, that is, a CMOS circuit. Using CMOS circuits in signal circuits and control circuits around the display area can greatly reduce power consumption and increase operating speed. The purpose of light doping in the channel area is to make appropriate adjustments to the threshold voltage. The channel length of the thin film transistor provided in an embodiment of the present invention is less than 0.5 microns.

[0052] Specifically, when the pixel size is 1μm×1μm, half of the area is used to make the second area of ​​the thin film transistor circuit. In an area of ​​0.5μm×1μm, it is relatively easy to manufacture a thin film transistor with a channel length of 0.4μm, a channel width of 0.8μm, and a width-to-length ratio W / L=2. To be conservative, it is assumed that the electron mobility of the metal oxide thin film transistor is only 10cm 2 / cm.s, the gate insulating film thickness is 50nm, the gate saturation voltage relative to the source is 3V, the threshold voltage is 0.5V, and the source voltage is 1V, then the saturation current of the thin film transistor can reach 240nA. As for the current of OLED, even at 1000mA / cm 2 According to the current density of the OLED film with an area of ​​1μm×1μm, the current of the OLED film is at most 10nA, which is far less than the current that the metal oxide thin film transistor can provide. However, it is worth mentioning that when the pixel area exceeds 10μm×10μm, a higher mobility and a larger aspect ratio of the oxide semiconductor thin film transistor are required, otherwise it is difficult to provide enough current to the high-brightness OLED light-emitting layer, which is why most small-sized OLED displays such as mobile phone screens use low-temperature polycrystalline silicon thin film transistors with higher mobility. Metal oxide thin film transistors are usually single-carrier conductive, such as IGZO, whose hole mobility is almost zero, but the electron mobility can reach tens, and it cannot be made into a driving and scanning module for CMOS circuits. Therefore, a single-crystal silicon chip and a metal oxide film superimposed thereon are used. In addition, from the perspective of display integration and packaging technology, the method of bonding the driver IC to the glass substrate commonly used in mobile phone displays has reached the limit of reducing the border. To this end, single-crystal silicon is directly used as the substrate, the driving module is made around it, and the pixel array of the display area is directly superimposed on the single-crystal silicon substrate in the middle, opening up a way to achieve an extremely narrow border.

[0053] An embodiment of the present invention further provides a display device, comprising any one of the display panels provided in the above embodiments, wherein the display device may be a wearable device for AR or VR.

[0054] Since the display device provided by the embodiment of the present invention includes any one of the display panels provided by the above embodiments, it has the same or corresponding technical effects as the display panel.

[0055] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A single crystal silicon substrate, the single crystal silicon substrate comprising a first region and a second region; The first region includes a single crystal silicon transistor circuit manufactured on the single crystal silicon substrate, the single crystal silicon transistor circuit is located in the signal circuit and the control circuit of the display panel, and the second region includes a pixel circuit array of the display panel manufactured on the single crystal silicon substrate, the pixel circuit array includes a plurality of compound semiconductor thin film transistors; A light-emitting layer superimposed on the pixel circuit array, whose light-emitting state is controlled by the pixel circuit array; Also included: a plurality of single crystal silicon transistors within the pixel circuit array; A mixed light-emitting layer of an organic light-emitting diode film and an inorganic light-emitting diode chip in the light-emitting layer; The compound semiconductor thin film transistor in the pixel circuit array drives the organic light emitting diode thin film, and the single crystal silicon transistor in the pixel circuit array drives the inorganic light emitting diode chip.

2. The display panel according to claim 1, characterized in that: The light-emitting layer includes at least one of an organic light-emitting diode film, an inorganic light-emitting diode chip, nano-shaped light-emitting particles, and an inorganic electroluminescent film.

3. The display panel according to claim 1, characterized in that: Also includes: The row scanning circuit in the first area for scanning the pixel circuit array is located on one side or both sides of the pixel circuit array, and the row scanning circuit includes a plurality of the single crystal silicon transistors.

4. The display panel according to claim 1, characterized in that: Also includes: The row scanning circuit in the second area for scanning the pixel circuit array is located on one side or both sides of the pixel circuit array, and the row scanning circuit includes a plurality of the thin film transistors.

5. The display panel according to claim 1, characterized in that: The compound semiconductor in the thin film transistor includes one of the following materials: A metal oxide semiconductor material, wherein the metal oxide semiconductor material includes ZnO, CdO, MgO or IGZO; II-IV compound semiconductor materials, wherein the II-IV compound semiconductor materials include ZnSe, ZnS, ZnTe, CdSe, CdTe or CdS; The III-V compound semiconductor material includes GaAs, GaP, InAs or InP.

6. The display panel according to claim 1, characterized in that: The signal circuit and the control circuit include single-crystal silicon transistors with polysilicon gates, the pixel circuit array includes thin-film transistors with polysilicon gates, and the single-crystal silicon transistors and the polysilicon gates of the thin-film transistors are both manufactured synchronously.

7. The display panel according to claim 6, characterized in that: include: A double-gate thin film transistor has a bottom gate and a top gate connected together.

8. The display panel according to claim 7, characterized in that: The thickness of the insulating layer of the bottom gate is smaller than the thickness of the insulating layer of the top gate.

9. The display panel according to claim 1, characterized in that: The channel length of the thin film transistor is less than 0.5 micrometers.

10. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 9.

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