Dual-color wide-spectrum detector, dual-color wide-spectrum detector array and manufacturing method

Abstract

The embodiments of the present application provide a dual-color wide-band short-wave infrared detector and a manufacturing method thereof, a dual-color wide-band short-wave infrared detector array and a manufacturing method thereof. The dual-color wide-band short-wave infrared detector uses an lnP substrate, an lnP lower contact layer, a first absorption layer, an N-type common contact layer, and a first P electrode and an N electrode to form an n‑i‑p type InGaAs detector, and uses a P-type doping region, a diffusion control layer, a second absorption layer, a buffer layer, an N-type common contact layer, and a second P electrode and an N electrode to form a p‑i‑n type multi-quantum well structure detector. The two detectors are combined to achieve short-wave infrared detection in a wavelength range of 0.9μm to 2.6μm, and each component structure in the dual-color wide-band short-wave infrared detector is designed with an InP-based III‑V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector has a wider response spectrum, higher sensitivity, and better manufacturability.

Description

Technical Field

[0001] The present application relates to the technical field of short-wave infrared detection, and in particular to a dual-color wide-spectrum short-wave infrared detector and a manufacturing method thereof, and a dual-color wide-spectrum short-wave infrared detector array and a manufacturing method thereof. Background Art

[0002] As the third atmospheric infrared window, short-wave infrared light has gradually shown its application potential in industrial detection, spectral sensing, security and defense in recent years. The spectral range of short-wave infrared light covers 1.0μm to 2.7μm. In terms of spectral signal characteristics, there are differences between the 0.9μm to 1.7μm spectral range and the 1.7μm to 2.7μm spectral range of short-wave infrared light. These two spectral ranges are complementary in application characteristics. Therefore, it is necessary to develop two-color short-wave infrared detection technology. However, existing research on two-color detection is mainly concentrated in the mid- and long-wave thermal infrared spectral range. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a dual-color wide-band short-wave infrared detector and a manufacturing method thereof, as well as a dual-color wide-band short-wave infrared detector array and a manufacturing method thereof, so as to realize dual-color wide-band short-wave infrared detection.

[0004] To achieve the above objectives, this application provides the following technical solutions:

[0005] A dual-color wide-band short-wave infrared detector, comprising:

[0006] P-type doped lnP substrate;

[0007] A P-type doped InP lower contact layer located on the first side surface of the substrate;

[0008] A first absorption layer is located on the side of the lower contact layer away from the substrate, wherein the first absorption layer exposes a portion of the lower contact layer and is an intrinsic ln 0.53 Ga 0.47 As layer;

[0009] A first stacking structure located on a surface of the first absorption layer facing away from the lower contact layer, the first stacking structure comprising: a stacked common contact layer and a second stacking structure, the second stacking structure exposing a portion of the common contact layer, comprising: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, and a P-type doping region extending from the top layer to the diffusion control layer along the first direction;

[0010] A first P electrode located in the exposed area of ​​the lower contact layer and electrically connected to the lower contact layer;

[0011] An N electrode located in an exposed area of ​​the common contact layer and electrically connected to the common contact layer;

[0012] a second P electrode located at a side of the second stacked structure away from the first absorption layer and electrically connected to the P-type doping region;

[0013] Wherein, the common contact layer comprises N-type doped ln x Ga 1-x As layer, the buffer layer is an intrinsic InGaAs layer, the second absorption layer includes a multi-quantum well structure, the diffusion control layer is an intrinsic InGaAs layer, and the top layer is an N-type doped InP layer or InAlAs layer.

[0014] Optionally, the multi-quantum well structure comprises quantum well layers and quantum barrier layers that are alternately stacked, and the number of the quantum well layers is one more than the number of the quantum barrier layers;

[0015] The quantum well layer is a InGaAs layer, and the quantum barrier layer is a GaAsSb layer.

[0016] Optionally, also include:

[0017] a lower limiting layer located between the lower contact layer and the first absorbing layer, the lower limiting layer exposing a portion of the lower contact layer, and the first absorbing layer being located on a surface of the lower limiting layer facing away from the lower contact layer;

[0018] The lower confinement layer is a P-type doped InAlAs layer.

[0019] Optionally, the thickness of the lower limiting layer ranges from 0.2 μm to 1.0 μm, including endpoint values.

[0020] Optionally, the first stacking structure further includes:

[0021] a first confinement layer between the first absorbing layer and the common contact layer;

[0022] a second restriction layer located between the common contact layer and the buffer layer, the second restriction layer exposing a portion of the common contact layer, and the buffer layer being located on a surface of the second restriction layer facing away from the common contact layer;

[0023] The first confinement layer and the second confinement layer are N-type doped InP layers or N-type doped InAlAs layers.

[0024] Optionally, the thickness of the first restriction layer and the second restriction layer ranges from 0.2 μm to 1.5 μm, including endpoint values.

[0025] Optionally, also include:

[0026] A first insulating layer covering the first stacked structure and a partial area of ​​the lower contact layer, wherein the first insulating layer has a first through hole, a second through hole and a third through hole;

[0027] Among them, the first through hole exposes a partial area of ​​the lower contact layer, and the first P electrode is located in the first through hole and electrically connected to the lower contact layer; the second through hole exposes at least a partial area of ​​the P-type doped region, and the second P electrode is located in the second through hole and electrically connected to the P-type doped region; the third through hole exposes a partial area of ​​the common contact layer, and the N electrode is located in the third through hole and electrically connected to the common contact layer.

[0028] Optionally, the N electrode further extends to cover a portion of the surface of the second stacked structure.

[0029] A method for manufacturing a dual-color wide-band short-wave infrared detector, comprising:

[0030] Forming a P-type doped InP lower contact layer on the first side surface of the P-type doped InP substrate;

[0031] A first absorption layer is formed on the side of the lower contact layer away from the substrate, the first absorption layer exposes a portion of the lower contact layer, and a first stacking structure is formed on the surface of the first absorption layer away from the lower contact layer, the first stacking structure includes: a stacked common contact layer and a second stacking structure, the second stacking structure exposes a portion of the common contact layer, and includes: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, and a P-type doping region extending into the diffusion control layer through the top layer along the first direction, the first absorption layer is an intrinsic ln 0.53 Ga 0.47 As layer;

[0032] forming a first P electrode electrically connected to the lower contact layer in the exposed area of ​​the lower contact layer;

[0033] forming an N electrode electrically connected to the common contact layer in an exposed area of ​​the common contact layer;

[0034] forming a second P electrode electrically connected to the P-type doping region on a side of the second stacked structure away from the common contact layer;

[0035] Wherein, the common contact layer comprises N-type doped ln x Ga 1-x As layer, the buffer layer is an intrinsic InGaAs layer, the second absorption layer includes a multi-quantum well structure, the diffusion control layer is an intrinsic InGaAs layer, and the top layer is an N-type doped InP layer or InAlAs layer.

[0036] Optionally, also include:

[0037] A lower limiting layer is formed between the lower contact layer and the first absorbing layer, wherein the lower limiting layer exposes a portion of the lower contact layer, and the first absorbing layer is located on a surface of the lower limiting layer facing away from the lower contact layer;

[0038] The lower confinement layer is a P-type doped InAlAs layer.

[0039] Optionally, the first stacking structure further includes:

[0040] a first confinement layer between the first absorbing layer and the common contact layer;

[0041] a second restriction layer located between the common contact layer and the buffer layer, the second restriction layer exposing a portion of the common contact layer, and the buffer layer being located on a surface of the second restriction layer facing away from the common contact layer;

[0042] The first confinement layer and the second confinement layer are N-type doped InP layers or N-type doped InAlAs layers.

[0043] A dual-color wide-band short-wave infrared detector array, comprising:

[0044] P-type doped lnP substrate;

[0045] A P-type doped InP lower contact layer located on the first side surface of the substrate;

[0046] A first absorption layer is located on the side of the lower contact layer away from the substrate, wherein the first absorption layer exposes a portion of the lower contact layer and is an intrinsic ln 0.53 Ga 0.47 As layer;

[0047] At least two first stacked structures are located on the surface of the first absorption layer on a side away from the lower contact layer, the first stacked structure includes: a stacked common contact layer and a second stacked structure, the second stacked structure exposes a portion of the common contact layer, includes: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, penetrates the top layer along the first direction, and extends to a P-type doped region in the diffusion control layer;

[0048] A first P electrode located in the exposed area of ​​the lower contact layer and electrically connected to the lower contact layer;

[0049] An N-electrode located in an exposed area of ​​the common contact layer and electrically connected to the common contact layer, wherein the N-electrode corresponds to the first stacked structure in a one-to-one manner;

[0050] a second P electrode located at a side of the second stacked structure away from the first absorption layer and electrically connected to the P-type doping region, the second P electrode corresponding to the P-type doping region in a one-to-one manner;

[0051] Wherein, the common contact layer comprises N-type doped ln x Ga 1-x As layer, the buffer layer is an intrinsic InGaAs layer, the second absorption layer includes a multi-quantum well structure, the diffusion control layer is an intrinsic InGaAs layer, and the top layer is an N-type doped InP layer or InAlAs layer.

[0052] Optionally, also include:

[0053] a lower limiting layer located between the lower contact layer and the first absorbing layer, the lower limiting layer exposing a portion of the lower contact layer, and the first absorbing layer being located on a surface of the lower limiting layer facing away from the lower contact layer;

[0054] The lower confinement layer is a P-type doped InAlAs layer.

[0055] Optionally, the first stacking structure further includes:

[0056] a first confinement layer between the first absorbing layer and the common contact layer;

[0057] a second restriction layer located between the common contact layer and the buffer layer, the second restriction layer exposing a portion of the common contact layer, and the buffer layer being located on a surface of the second restriction layer facing away from the common contact layer;

[0058] The first confinement layer and the second confinement layer are N-type doped InP layers or N-type doped InAlAs layers.

[0059] A method for manufacturing a dual-color, wide-spectrum, short-wave infrared detector array, used to manufacture any of the dual-color, wide-spectrum, short-wave infrared detector arrays described above, the manufacturing method comprising:

[0060] Forming a stacking structure on the first side surface of the P-type doped InP substrate, the stacking structure comprising a stacked lower contact layer, a first absorption layer, a common contact layer, a buffer layer, a second absorption layer, a diffusion control layer and a top layer;

[0061] forming a P-type doped region in a plurality of first regions of the top layer, wherein the P-type doped region extends into the diffusion control layer;

[0062] Etching the stack structure to the lower contact layer to expose a second region of the lower contact layer;

[0063] Etching the stacked structure to the first absorption layer to form at least two first stacked structures, wherein the first stacked structures correspond to the P-type doped regions one by one;

[0064] Etching the at least two first stacked structures to the common contact layer to form at least two second stacked structures, wherein the second stacked structures correspond to the first stacked structures one by one;

[0065] forming a first P electrode electrically connected to the lower contact layer in the exposed area of ​​the lower contact layer;

[0066] forming an N electrode electrically connected to the common contact layer in an exposed area of ​​the common contact layer;

[0067] A second P electrode electrically connected to the P-type doping region is formed on a side of the second stacked structure away from the common contact layer.

[0068] Optionally, forming a P-type doping region in the plurality of first regions of the top layer, wherein the P-type doping region extends into the diffusion control layer, comprises:

[0069] A diffusion process is used to form P-type doping regions in a plurality of first regions of the top layer, and the P-type doping regions extend into the diffusion control layer.

[0070] Compared with the prior art, the above technical solution has the following advantages:

[0071] The dual-color wide-band short-wave infrared detector provided in the embodiment of the present application utilizes an lnP substrate, an lnP lower contact layer, a first absorption layer, an N-type common contact layer, and a first P electrode and an N electrode to form a nip-type InGaAs detector to achieve short-wave infrared detection in the standard wavelength 0.9μm to 1.7μm spectrum band, and simultaneously utilizes a P-type doped region, a diffusion control layer, a second absorption layer, a buffer layer, an N-type common contact layer, and a second P electrode and an N electrode to form a pin-type multi-quantum well structure detector to achieve short-wave infrared detection in the extended wavelength 1.7μm to 2.6μm spectrum band, thereby enabling the dual-color wide-band short-wave infrared detector to achieve dual-color wide-band short-wave infrared detection.

[0072] Moreover, in the dual-color wide-band short-wave infrared detector provided in the embodiment of the present application, each component structure is designed using an InP-based III-V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector has a wider response spectrum, higher sensitivity, and better manufacturability. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0074] Figure 1 A schematic diagram of the structure of a dual-color, wide-band, short-wave infrared detector provided by one embodiment of the present application;

[0075] Figure 2 A curve diagram showing the variation of the response quantum efficiency of a dual-color, wide-band, short-wave infrared detector as a function of its spectral response wavelength provided by an embodiment of the present application;

[0076] Figure 3 A schematic diagram of the energy band structure of the n+_InP / n+_InGaAs / n+_InP heterogeneous nBi hole barrier in a dual-color wide-band short-wave infrared detector provided in one embodiment of the present application;

[0077] Figure 4 A flowchart of a method for manufacturing a dual-color, wide-band, short-wave infrared detector provided by one embodiment of the present application;

[0078] Figure 5-Figure 18 A schematic diagram of the structure after each process step is completed in a method for manufacturing a dual-color, wide-spectrum, short-wave infrared detector provided in an embodiment of the present application;

[0079] Fig.19 A schematic diagram of the structure of a dual-color, wide-band, short-wave infrared detector array provided by one embodiment of the present application;

[0080] Fig. 20 A top view of a dual-color, wide-band, short-wave infrared detector array provided by one embodiment of the present application;

[0081] Fig.21 A flow chart of a method for manufacturing a dual-color wide-band short-wave infrared detector array provided in one embodiment of the present application;

[0082] Figure 22-Figure 31 A schematic structural diagram of a method for manufacturing a dual-color, wide-band, short-wave infrared detector array after each process step is completed according to an embodiment of the present application. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0084] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0085] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0086] Currently, due to the maturity of technology, most applications of short-wave infrared light mainly choose In 0.53 Ga 0.47 The As / InP detector has a spectral range of 0.9μm to 1.7μm. From an application perspective, the molecular functional groups are enriched in the spectral range of 1.7μm to 2.7μm of short-wave infrared light, which has important application value.

[0087] It should be noted that the response cutoff wavelength of InGaAs detectors in the prior art can be extended to 2.7 μm, but when the cutoff wavelength is greater than 1.7 μm, due to the material lattice mismatch between the substrate and the absorption layer, a complex buffer zone design is required for the epitaxial layer.

[0088] For the back-incident structure suitable for the manufacture of focal plane detectors, the absorption effect of the narrow-bandgap lattice mismatch buffer will cause the quantum efficiency of the InGaAs detector in the short wavelength direction to drop sharply, limiting the spectral response range of the InGaAs detector; and, the material defects introduced by the lattice mismatch in the InGaAs detector will significantly increase the dark current of the detector, resulting in limited detection sensitivity of the InGaAs detector and greatly reduced manufacturability.

[0089] Therefore, most of the current applications in wide spectral bands such as 0.8μm~2.5μm and 1.0μm~2.5μm use HgCdTe technology. However, considering factors such as volume power consumption, cost price, and two-color detection, HgCdTe detectors are not an ideal choice.

[0090] In view of this, the embodiment of the present application provides a dual-color wide-spectrum short-wave infrared detector and a manufacturing method thereof, and a dual-color wide-spectrum short-wave infrared detector array and a manufacturing method thereof, so as to realize dual-color wide-spectrum short-wave infrared detection. The dual-color wide-spectrum short-wave infrared detector and a manufacturing method thereof, and a dual-color wide-spectrum short-wave infrared detector array and a manufacturing method thereof provided in the embodiment of the present application are described below in conjunction with the accompanying drawings.

[0091] like Figure 1 As shown, the dual-color wide-spectrum short-wave infrared detector provided in the embodiment of the present application includes:

[0092] A P-type doped InP substrate 10, optionally, the substrate is a single crystal substrate, and the substrate is a Zn-doped InP substrate;

[0093] A P-type doped InP lower contact layer 20 located on the first side surface of the substrate 10;

[0094] The first absorption layer 30 is located on the side of the lower contact layer 20 away from the substrate 10. The first absorption layer 30 exposes a portion of the lower contact layer 20 and is an intrinsic ln 0.53 Ga 0.47 As layer;

[0095] a first stacking structure located on a surface of the first absorption layer 30 on a side away from the lower contact layer 20, the first stacking structure comprising: a stacked common contact layer 40 and a second stacking structure 50, the common contact layer 40 being located on a side away from the first absorption layer 30 and away from the substrate 10, the second stacking structure 50 exposing a portion of the common contact layer 40, and comprising: a stacked buffer layer 51, a second absorption layer 52, a diffusion control layer 53 and a top layer 54, and a P-type doping region 55 extending along the first direction X through the top layer 54 and into the diffusion control layer 53;

[0096] A first P electrode 60 located in an exposed area of ​​the lower contact layer 20 and electrically connected to the lower contact layer 20;

[0097] An N electrode 70 located in an exposed area of ​​the common contact layer 40 and electrically connected to the common contact layer 40;

[0098] A second P electrode 80 is located at a side of the second stacked structure 50 away from the first absorption layer 30 and is electrically connected to the P-type doping region 55 .

[0099] The common contact layer 40 includes N-type doped ln x Ga 1-xAs layer, the buffer layer 51 is an intrinsic InGaAs layer, the second absorption layer 52 includes a multi-quantum well structure, the diffusion control layer 53 is an intrinsic InGaAs layer, and the top layer 54 is an N-type doped InP layer or InAlAs layer.

[0100] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the lower contact layer ranges from 0.2 μm to 1.0 μm, including the end value. Optionally, the lower contact layer is a Zn-doped lnP layer, and the P-type doping concentration of the lower contact layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0101] Based on the above embodiments, in one embodiment of the present application, the thickness of the first absorption layer ranges from 2.0 μm to 3.5 μm, including the end value, and optionally, the background carrier concentration in the first absorption layer is not greater than 5E+15 cm -3 .

[0102] Specifically, in one embodiment of the present application, the first stacking structure includes:

[0103] The common contact layer 40 is located on the side away from the first absorption layer 30 and away from the substrate 10. Optionally, the common contact layer thickness ranges from 0.1 μm to 1.0 μm, including the end value, and the N-type doping concentration of the common contact layer ranges from 2E+18 cm -3 ~8E+18cm -3 , including endpoint values;

[0104] a buffer layer 51 located on a side of the common contact layer 40 away from the first absorption layer 30;

[0105] A second absorption layer 52 located on a side of the buffer layer 51 away from the common contact layer 40;

[0106] a diffusion control layer 53 located on a side of the second absorption layer 52 away from the buffer layer 51;

[0107] a top layer 54 located on a side of the diffusion control layer 53 away from the second absorption layer 52;

[0108] The first direction X penetrates the top layer 54 and extends to the P-type doping region 55 in the diffusion control layer 53 .

[0109] It should be noted that, in the embodiment of the present application, the buffer layer located between the common contact layer and the second absorption layer is conducive to better growth of the second absorption layer.

[0110] Based on the above embodiments, in one embodiment of the present application, the multi-quantum well structure includes:

[0111] A quantum well layer 521 located on the side of the buffer layer 51 away from the common contact layer 40, and a quantum barrier layer 522 located on the side of the quantum well layer 521 away from the buffer layer 51; wherein a plurality of the quantum well layers 521 and the quantum barrier layers 522 are arranged alternately, and the number of the quantum well layers 521 is one more than the number of the quantum barrier layers 522, so that a layer of the multi-quantum well structure in contact with the buffer layer is a quantum well layer, and a layer of the multi-quantum well structure in contact with the diffusion control layer is also a quantum well layer. Optionally, in an embodiment of the present application, the quantum well layer 521 is a lnGaAs layer, and the quantum barrier layer 522 is a GaAsSb layer.

[0112] It should be noted that, in an embodiment of the present application, the response cutoff wavelength of the second absorption layer is related to the thickness of the second absorption layer. Optionally, in an embodiment of the present application, the multi-quantum well structure includes quantum well layers and quantum barrier layers arranged in an alternating manner for 200 to 300 periods, that is, the number of quantum well layers and quantum barrier layers in the multi-quantum well structure ranges from 200 to 300, including endpoint values, but the present application does not limit this and it depends on the specific circumstances.

[0113] Specifically, in one embodiment of the present application, the quantum well layer is ln 0.53 Ga 0.47 As layer, the thickness of the quantum well layer is 6.4nm; the quantum barrier layer is GaAs 0.51 Sb 1-0.51 The thickness of the quantum barrier layer is 5.0 nm, but this application does not limit this and it depends on the specific situation.

[0114] Based on any of the above embodiments, in one embodiment of the present application, the diffusion control layer is an intrinsic ln 0.53 Ga 0.47 As layer, the intrinsic ln 0.53 Ga 0.47 The background carrier concentration in the As layer is no more than 5E+15cm -3 , so as to control the spatial distribution of Zn diffusion concentration in the diffusion control layer. Optionally, the thickness of the diffusion control layer ranges from 0.5 μm to 1.5 μm, including the endpoint values.

[0115] On the basis of any of the above embodiments, in one embodiment of the present application, the thickness of the top layer ranges from 0.3 μm to 1.5 μm, including the endpoint value, the N-type doping ion in the top layer is Si, and the doping concentration ranges from 1E+16 cm -3 ~5E+16cm-3 , including endpoint values. However, this application does not limit this, and it depends on the specific circumstances.

[0116] Based on any of the above embodiments, in one embodiment of the present application, the P-type doping region is formed by diffusion of Zn ions, and the diffusion concentration ranges from 1E+18cm -3 ~5E+18cm -3 , including endpoint values. However, this application does not limit this, and it depends on the specific circumstances.

[0117] like Figure 2 As shown, Figure 2 A curve diagram showing the change in the response quantum efficiency of the dual-color wide-band short-wave infrared detector provided in an embodiment of the present application as a function of its spectral response wavelength is shown, wherein curve a is the response spectrum of a nip-type InGaAs detector formed by an lnP substrate, an lnP lower contact layer, a first absorption layer, an N-type common contact layer, a first P electrode and an N electrode, and curve b is the response spectrum of a pin-type multi-quantum well structure detector formed by a P-type doped region, a diffusion control layer, a second absorption layer, a buffer layer, an N-type common contact layer, a second P electrode and an N electrode.

[0118] from Figure 2 It can be seen that the dual-color wide-band short-wave infrared detector provided in the embodiment of the present application can utilize an lnP substrate, an lnP lower contact layer, a first absorption layer, an N-type common contact layer, a first P electrode and an N electrode to form a nip-type InGaAs detector to achieve short-wave infrared detection in the standard wavelength 0.9μm to 1.7μm spectrum band, and at the same time utilize a P-type doped region, a diffusion control layer, a second absorption layer, a buffer layer, an N-type common contact layer, and a second P electrode and an N electrode to form a pin-type multi-quantum well structure detector to achieve short-wave infrared detection in the extended wavelength 1.7μm to 2.6μm spectrum band, so that the dual-color wide-band short-wave infrared detector can achieve dual-color wide-band short-wave infrared detection.

[0119] It should be noted that, based on the above embodiments, n represents N-type doping, i represents undoped, p represents P-type doping, and in the nip-type InGaAs detector, nip represents that the N-type doped structural layer is located above the P-type doped structural layer, that is, in the embodiment of the present application, the nip-type InGaAs detector is composed of a P-type doped structural layer, an undoped intrinsic layer located above the P-type doped structural layer, and an N-type doped structural layer located above the undoped intrinsic layer; the pin-type multi-quantum well structure detector is composed of an N-type doped structural layer, an undoped intrinsic layer located above the N-type doped structural layer, and a P-type doped structural layer located above the undoped intrinsic layer.

[0120] On the basis of any of the above embodiments, in one embodiment of the present application, the dual-color wide-spectrum short-wave infrared detector further includes:

[0121] A lower restriction layer 21 is located between the lower contact layer 20 and the first absorption layer 30, wherein the lower restriction layer 21 exposes a portion of the lower contact layer 20, and the first absorption layer 30 is located on the surface of the lower restriction layer 21 away from the lower contact layer 20; optionally, the lower restriction layer is a P-type doped InAlAs layer.

[0122] Specifically, based on the above embodiments, in one embodiment of the present application, the thickness of the lower limiting layer ranges from 0.2 μm to 1.0 μm, including the end value, and the P-type doping concentration of the lower limiting layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0123] It should be noted that in the embodiment of the present application, since the band gap of the lower confinement layer is relatively wide, the lower confinement layer inserted between the lower contact layer and the first absorption layer can inhibit the diffusion of impurities in the substrate and the lower contact layer toward the first absorption layer, which is beneficial to improving the quality of the subsequent epitaxial structure.

[0124] On the basis of any of the above embodiments, in one embodiment of the present application, the first stacking structure further includes:

[0125] a first restriction layer 41 located between the first absorption layer 30 and the common contact layer 40;

[0126] a second restriction layer 42 located between the common contact layer 40 and the buffer layer 51, wherein the second restriction layer 42 exposes a portion of the common contact layer 40, and the buffer layer 51 is located on a surface of the second restriction layer 42 facing away from the common contact layer 40;

[0127] The first confinement layer 41 and the second confinement layer 42 are N-type doped InP layers or N-type doped InAlAs layers.

[0128] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the first restriction layer and the second restriction layer ranges from 0.2 μm to 1.5 μm, including the end value, and the doping ions of the first restriction layer and the second restriction layer are Si, and the doping concentration ranges from 1E+18 cm -3 ~8E+18cm -3 , including the endpoint values.

[0129] like Figure 3 As shown, Figure 3The schematic diagram of the n+_InP / n+_InGaAs / n+_InP heterogeneous nBi hole barrier band structure is shown. Figure 3 It can be seen that in the above embodiment, the first confinement layer, the common contact layer and the second confinement layer can form a double heterojunction and form an nBi heterostructure with the second absorption layer, so that the nBi heterostructure can be used to form a hole unipolar barrier at the heterointerface, effectively improving the dark current problem caused by surface recombination.

[0130] From the materials of each component structure in the dual-color wide-band short-wave infrared detector in the above-mentioned embodiments, it can be seen that each component structure in the dual-color wide-band short-wave infrared detector provided in the embodiments of the present application is designed with an InP-based III-V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector has a wider response spectrum, higher sensitivity and better manufacturability.

[0131] On the basis of any of the above embodiments, in one embodiment of the present application, the dual-color wide-spectrum short-wave infrared detector also includes: a first insulating layer 90 covering the first stacking structure and a partial area of ​​the lower contact layer 20, the first insulating layer 90 having a first through hole, a second through hole and a third through hole; wherein the first through hole exposes a partial area of ​​the lower contact layer 20, the first P electrode 60 is located in the first through hole, and is electrically connected to the lower contact layer 20; the second through hole exposes at least a partial area of ​​the P-type doped region 55, the second P electrode 80 is located in the second through hole, and is electrically connected to the P-type doped region 55; the third through hole exposes a partial area of ​​the common contact layer 40, the N electrode 70 is located in the third through hole, and is electrically connected to the common contact layer 40.

[0132] Based on the above embodiments, in one embodiment of the present application, the first insulating layer 90 also covers the side of the N electrode 70 to insulate and protect the side wall of the N electrode, thereby reducing the probability of the N electrode short-circuiting with other structures or the probability of the N electrode being disconnected due to wear.

[0133] Optionally, based on the above embodiments, in one embodiment of the present application, the first P electrode (i.e., the P lower electrode) is a stacked structure of a Cr electrode and an Au electrode, or a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a metal-semiconductor ohmic contact process; the second P electrode and N electrode are a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a UBM (under bumping metallization) process, but the present application does not limit this and it depends on the specific circumstances.

[0134] Based on the above embodiments, in one embodiment of the present application, the N electrode 70 also extends to cover a portion of the surface of the second stacked structure 50, so that the electrical connection point between the N electrode 70 and the outside world and the electrical connection point between the second P electrode 80 and the outside world are flush, so as to facilitate the electrical connection between the N electrode and the second P electrode and the external structure.

[0135] On the basis of the above embodiments, in one embodiment of the present application, the dual-color wide-band short-wave infrared detector further includes:

[0136] A first electrical connection ball 71 located at a side of the N electrode 70 away from the top layer 54 and electrically connected to the N electrode. Optionally, the first electrical connection ball is an In ball for flip-chip interconnection with a readout circuit;

[0137] A second electrical connection ball 81 is located on the side of the second P electrode 80 away from the top layer 54 and is electrically connected to the second P electrode. Optionally, the second electrical connection ball is an In ball for flip-chip interconnection with a readout circuit.

[0138] On the basis of the above embodiments, in one embodiment of the present application, the dual-color wide-band short-wave infrared detector further includes:

[0139] The first antireflection film 11 is located on the side of the substrate 10 away from the first absorption layer 30. Optionally, the first antireflection film is an AR antireflection coating.

[0140] In summary, the dual-color wide-band short-wave infrared detector provided in the embodiment of the present application utilizes an lnP substrate, an lnP lower contact layer, a first absorption layer, an N-type common contact layer, and a first P electrode and an N electrode to form a nip-type InGaAs detector to achieve short-wave infrared detection in the standard wavelength range of 0.9μm to 1.7μm. At the same time, a pin-type multi-quantum well structure detector is formed using a P-type doped region, a diffusion control layer, a second absorption layer, a buffer layer, an N-type common contact layer, and a second P electrode and an N electrode to achieve short-wave infrared detection in the extended wavelength range of 1.7μm to 2.6μm. Based on the InP substrate and using a III-V group lattice-matched material system, the nip-type InGaAs detector structure is combined with a pin-type InGaAs / GaAsSb two-type MQWs detector structure to achieve a dual-color wide-band short-wave infrared pinip-type detector structure design that responds to standard wavelengths of 0.9μm to 1.7μm and extended wavelengths of 1.7μm to 2.6μm.

[0141] Moreover, in the dual-color wide-band short-wave infrared detector provided in the embodiment of the present application, each component structure is designed using an InP-based III-V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector has a wider response spectrum, higher sensitivity, and better manufacturability.

[0142] Correspondingly, an embodiment of the present application also provides a method for manufacturing a dual-color, wide-spectrum, short-wave infrared detector, which is used to manufacture the dual-color, wide-spectrum, short-wave infrared detector provided by any of the above embodiments.

[0143] It should be noted that in one embodiment of the present application, MOCVD epitaxial technology is used to produce the dual-color wide-spectrum short-wave infrared detector provided in any of the above embodiments, but the present application is not limited to this. MBE epitaxial technology can also be used to produce the dual-color wide-spectrum short-wave infrared detector provided in any of the above embodiments, depending on the specific circumstances.

[0144] Specifically, Figure 4 As shown, the manufacturing method of the dual-color wide-band short-wave infrared detector provided in the embodiment of the present application includes:

[0145] S401: Figure 5 As shown, a P-type doped InP lower contact layer 20 is formed on a first side surface of a P-type doped InP substrate 10 .

[0146] In one embodiment of the present application, the substrate is a single crystal substrate, and the substrate is a Zn-doped InP substrate, which is not limited in the present application and depends on the specific circumstances.

[0147] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the lower contact layer ranges from 0.2 μm to 1.0 μm, including the end value. Optionally, the lower contact layer is a Zn-doped lnP layer, and the P-type doping concentration of the lower contact layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0148] S402: forming a first absorption layer on the side of the lower contact layer away from the substrate, the first absorption layer exposing a portion of the lower contact layer, and forming a first stacking structure on the surface of the first absorption layer away from the lower contact layer, the first stacking structure comprising: a stacked common contact layer and a second stacking structure, the second stacking structure exposing a portion of the common contact layer, comprising: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, and a P-type doping region extending from the top layer to the diffusion control layer along the first direction, the first absorption layer is an intrinsic ln 0.53 Ga 0.47 As layer.

[0149] Specifically, in one embodiment of the present application, a first absorption layer is formed on the side of the lower contact layer away from the substrate, the first absorption layer exposes a portion of the lower contact layer, and a first stacking structure is formed on the surface of the first absorption layer away from the lower contact layer, the first stacking structure includes: a stacked common contact layer and a second stacking structure, the second stacking structure exposes a portion of the common contact layer, including: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, and a P-type doped region extending into the diffusion control layer along the first direction through the top layer includes:

[0150] like Figure 6 As shown, a first absorption layer 30 is formed on the side of the lower contact layer 20 away from the substrate 10;

[0151] like Figure 7 As shown, a first stacking structure is formed on the surface of the first absorption layer 30 on the side away from the lower contact layer 20, the first stacking structure includes: a stacked common contact layer 40 and a second stacking structure 50, the second stacking structure 50 includes: a stacked buffer layer 51, a second absorption layer 52, a diffusion control layer 53 and a top layer 54, and a P-type doping region 55 extending into the diffusion control layer 53 and penetrating the top layer 54 along the first direction;

[0152] like Figure 8 As shown, the first stacked structure and the second region of the first absorption layer 30 are etched to expose a portion of the lower contact layer 20, and the second region is used for subsequently forming a first P electrode 60;

[0153] Continue as Figure 8 As shown, the third region of the first stacked structure is etched to expose a portion of the common contact layer 40 , and the third region is used for subsequently forming an N-electrode 70 .

[0154] It should be noted that, in the embodiment of the present application, the etching depth of the second region can be the sum of the thicknesses of the first stacking structure and the first absorption layer, or can be greater than the sum of the thicknesses of the first stacking structure and the first absorption layer, and less than the sum of the thicknesses of the first stacking structure, the first absorption layer and the lower contact layer. The present application does not impose any limitation on this, as long as a portion of the second region of the lower contact layer is exposed to facilitate the subsequent formation of a first P electrode electrically connected to the lower contact layer.

[0155] Optionally, in one embodiment of the present application, etching the first absorption layer and the second region of the first stacking structure includes: etching the first absorption layer and the second region of the first stacking structure by a dry etching process; in another embodiment of the present application, etching the first absorption layer and the second region of the first stacking structure includes: etching the first absorption layer and the second region of the first stacking structure by a wet etching process; in other embodiments of the present application, other processes may also be used to etch the first absorption layer and the first stacking structure, and the present application does not limit this, depending on the specific circumstances.

[0156] Based on any of the above embodiments, in one embodiment of the present application, the thickness of the first absorption layer ranges from 2.0 μm to 3.5 μm, including the end value, and optionally, the background carrier concentration in the first absorption layer is not greater than 5E+15 cm -3 .

[0157] Specifically, based on any of the above embodiments, in one embodiment of the present application, forming a first stacking structure on a surface of the first absorption layer facing away from the lower contact layer includes:

[0158] A common contact layer 40 is formed on the side of the first absorption layer 30 away from the substrate 10. The common contact layer includes an N-type doped ln x Ga 1-x As layer;

[0159] A second stacking structure is formed on the side of the common contact layer 40 away from the first absorption layer 30 .

[0160] Optionally, in one embodiment of the present application, forming a second stacking structure on a side of the common contact layer 40 away from the first absorption layer 30 includes:

[0161] A buffer layer 51 is formed on the side of the common contact layer 40 away from the first absorption layer 30, wherein the buffer layer is an intrinsic InGaAs layer;

[0162] A second absorption layer 52 is formed on a side of the buffer layer 51 away from the common contact layer 40, wherein the second absorption layer includes a multi-quantum well structure;

[0163] A diffusion control layer 53 is formed on the side of the second absorption layer 52 away from the buffer layer 51, and the diffusion control layer is an intrinsic InGaAs layer;

[0164] A top layer 54 is formed on the side of the diffusion control layer 53 away from the second absorption layer 52, and the top layer is an N-type doped InP layer or InAlAs layer;

[0165] A P-type doping region 55 is formed in the roof layer 54 , penetrating the roof layer 54 along the first direction and extending into the diffusion control layer 53 .

[0166] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the common contact layer ranges from 0.1 μm to 1.0 μm, including the endpoint value, and the N-type doping concentration of the common contact layer ranges from 2E+18 cm -3 ~8E+18cm -3 , including the endpoint values.

[0167] It should be noted that, based on the above embodiments, in one embodiment of the present application, the buffer layer located between the common contact layer and the second absorption layer is conducive to better growth of the second absorption layer.

[0168] Based on the above embodiments, in one embodiment of the present application, continue to refer to Figure 8 , forming a second absorption layer 52 on the side of the buffer layer 51 away from the common contact layer 40 includes:

[0169] A quantum well layer 521 and a quantum barrier layer 522 are alternately formed on the side of the buffer layer 51 away from the common contact layer 40; wherein a plurality of the quantum well layers 521 and the quantum barrier layers 522 are alternately arranged, and the number of the quantum well layers 521 is one more than the number of the quantum barrier layers 522, so that a layer of the multi-quantum well structure in contact with the buffer layer is a quantum well layer, and a layer of the multi-quantum well structure in contact with the diffusion control layer is also a quantum well layer. Optionally, the quantum well layer 521 is a lnGaAs layer, and the quantum barrier layer 522 is a GaAsSb layer.

[0170] It should be noted that, in the above embodiments, the response cutoff wavelength of the second absorption layer is related to the thickness of the second absorption layer. Optionally, in one embodiment of the present application, the multi-quantum well structure includes quantum well layers and quantum barrier layers that are staggered in 200 to 300 cycles, that is, the number of quantum well layers and quantum barrier layers in the multi-quantum well structure ranges from 200 to 300, including endpoint values, but the present application does not limit this and it depends on the specific circumstances.

[0171] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the quantum well layer is 6.4 nm. Optionally, the thickness of the quantum well layer is ln 0.53 Ga 0.47 As layer; the thickness of the quantum barrier layer is 5.0nm, optionally, the quantum barrier layer is GaAs 0.51 Sb 0.49 This application does not limit this, and it depends on the specific circumstances.

[0172] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the diffusion control layer ranges from 0.5 μm to 1.5 μm, including the end value, and optionally, the diffusion control layer is an intrinsic ln 0.53 Ga 0.47 As layer, the intrinsic ln 0.53 Ga 0.47 The background carrier concentration in the As layer is no more than 5E+15cm -3 , so as to control the spatial distribution of Zn diffusion concentration in the diffusion control layer.

[0173] On the basis of any of the above embodiments, in one embodiment of the present application, the thickness of the top layer ranges from 0.3 μm to 1.5 μm, including the endpoint value, the N-type doping ion of the top layer is Si, and the doping concentration ranges from 1E+16 cm -3 ~5E+16cm -3 , including endpoint values. However, this application does not limit this, and it depends on the specific circumstances.

[0174] Based on any of the above embodiments, in one embodiment of the present application, the P-type doping region is Zn ion diffused, and the diffusion concentration range is 1E+18cm -3 ~5E+18cm -3 , including the endpoint values.

[0175] On the basis of the above embodiments, in one embodiment of the present application, forming a P-type doping region in the top layer that penetrates the top layer along the first direction and extends into the diffusion control layer includes:

[0176] like Fig. 9 As shown, a first dielectric film layer 56 is deposited on the side of the top layer 54 away from the diffusion control layer 53. Optionally, the first dielectric film layer is SiN X The dielectric film layer may be SiO 2 Dielectric film layer;

[0177] like Fig.10 As shown, the first dielectric film layer 56 is photolithographically processed so that the first dielectric film layer forms a first dielectric pattern 57 including a first region;

[0178] like Fig.11 As shown, the first dielectric pattern 57 is used as a mask, and ion diffusion is performed on the first region of the top layer 54 by using a diffusion process to form a P-type doping region 55 in the first region of the top layer, and the P-type doping region 55 extends to the diffusion control layer 53;

[0179] The first medium pattern is removed.

[0180] Based on the above embodiment, in one embodiment of the present application, etching the first stacked structure until a partial area of ​​the common contact layer 40 is exposed includes:

[0181] like Fig.12 As shown, a second dielectric film layer 58 is deposited on the side of the top layer 54 away from the substrate 10, and the second dielectric film layer 58 is passivated so that the second dielectric film layer plays a role in protecting the surface of the dual-color wide-spectrum short-wave infrared detector. Optionally, the second dielectric film layer is SiN X Dielectric film, SiO 2 Dielectric film or Al 2 O 3 Dielectric film layer;

[0182] like Fig.13 As shown, the third region of the first stacked structure is etched using the second dielectric film layer 58 as a mask to expose the common contact layer 40, wherein the third region is used for subsequent formation of an N electrode;

[0183] The second dielectric film layer is removed.

[0184] Based on any of the above embodiments, in one embodiment of the present application, Fig.14 As shown, the first stacking structure also includes: a first restriction layer 41 located between the first absorption layer 30 and the common contact layer 40; a second restriction layer 42 located between the common contact layer 40 and the buffer layer 51, the second restriction layer 42 exposes a portion of the common contact layer 40, and the buffer layer 51 is located on the surface of the second restriction layer 42 on the side away from the common contact layer 40; accordingly, the method also includes: forming the first restriction layer 41 between the first absorption layer 30 and the common contact layer 40; forming the second restriction layer 42 between the common contact layer 40 and the buffer layer 51, the second restriction layer 42 exposes a portion of the common contact layer 40, and the buffer layer 51 is located on the surface of the second restriction layer 42 on the side away from the common contact layer 40.

[0185] It should be noted that, when the first stacked structure further includes a first restriction layer and a second restriction layer, etching the second stacked structure further includes etching the second restriction layer to expose a portion of the surface of the third region of the common contact layer.

[0186] It should also be noted that, in the embodiment of the present application, the etching depth of the third region can be the sum of the thicknesses of the second restriction layer and the second stacking structure, or can be greater than the sum of the thicknesses of the second restriction layer and the second stacking structure, and less than the sum of the thicknesses of the second restriction layer, the second stacking structure and the common contact layer. The present application does not limit this, as long as a portion of the third region of the common contact layer is exposed to facilitate the subsequent formation of an N electrode electrically connected to the common contact layer.

[0187] Optionally, in one embodiment of the present application, etching the second confinement layer and the third region of the second stacking structure includes: etching the second confinement layer and the third region of the second stacking structure by a dry etching process; in another embodiment of the present application, etching the second confinement layer and the third region of the second stacking structure includes: etching the second confinement layer and the third region of the second stacking structure by a wet etching process; in other embodiments of the present application, other processes may also be used to etch the second confinement layer and the second stacking structure, and the present application does not limit this, depending on the specific circumstances.

[0188] Specifically, in one embodiment of the present application, the first confinement layer 41 and the second confinement layer 42 are N-type doped InP layers or N-type doped InAlAs layers.

[0189] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the first limiting layer and the second limiting layer ranges from 0.2 μm to 1.5 μm, including the end value, the doping ion is Si, and the doping concentration ranges from 1E+18 cm -3 ~8E+18cm -3 , including the endpoint values.

[0190] It should be noted that, in the above embodiment, the first confinement layer, the common contact layer and the second confinement layer form a double heterojunction, and then form an nBi heterostructure with the second absorption layer, so that the nBi heterostructure can be used to form a hole unipolar barrier at the heterointerface, effectively improving the dark current problem caused by surface recombination.

[0191] Based on the above embodiments, in one embodiment of the present application, continue to refer to Fig.14 , the method further comprises:

[0192] A lower confinement layer 21 is formed between the lower contact layer 20 and the first absorption layer 30, the lower confinement layer 21 exposes a portion of the lower contact layer 20, and the first absorption layer 30 is located on the surface of the lower confinement layer 21 on a side away from the lower contact layer 20; optionally, the lower confinement layer is a P-type doped lnAlAs layer. It should be noted that, in the embodiment of the present application, when the first absorption layer and the first stacked structure are etched to expose a portion of the lower contact layer, the lower confinement layer is also etched to expose a portion of the lower contact layer.

[0193] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the lower limiting layer ranges from 0.2 μm to 1.0 μm, including the end value, and the P-type doping concentration of the lower limiting layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0194] It should be noted that in the embodiment of the present application, the band gap of the lower confinement layer is relatively wide. The lower confinement layer inserted between the lower contact layer and the first absorption layer can inhibit the diffusion of impurities in the substrate and the lower contact layer toward the first absorption layer, which is beneficial to improving the quality of the subsequent epitaxial structure.

[0195] Based on the above embodiments, in one embodiment of the present application, Fig.15 As shown, the method also includes:

[0196] A first insulating layer 90 is formed on the first stacking structure and partial areas of the lower contact layer 20 and the common contact layer 40, and the first insulating layer 90 has a first through hole, a second through hole and a third through hole; wherein the first through hole exposes a partial area of ​​the lower contact layer 20 to facilitate the subsequent formation of a first P electrode electrically connected to the lower contact layer in the first through hole, the second through hole exposes at least a partial area of ​​the P-type doping region to facilitate the subsequent formation of a second P electrode electrically connected to the P-type doping region in the second through hole, and the third through hole exposes a partial area of ​​the common contact layer 40 to facilitate the subsequent formation of an N electrode electrically connected to the common contact layer in the third through hole.

[0197] S403: Fig.16 As shown, a first P electrode 60 electrically connected to the lower contact layer 20 is formed in the exposed area of ​​the lower contact layer 20 , and is electrically connected to the lower contact layer 20 .

[0198] Optionally, based on the above embodiments, in one embodiment of the present application, the first P electrode (i.e., the P lower electrode) is a stacked structure of a Cr electrode and an Au electrode, or a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a metal-semiconductor ohmic contact process.

[0199] S404: Continue to refer Fig.16 An N electrode 70 electrically connected to the common contact layer 40 is formed in the exposed area of ​​the common contact layer 40, the third through hole exposes a portion of the common contact layer 40, and the N electrode 70 is located in the third through hole and electrically connected to the common contact layer.

[0200] Optionally, the N electrode is a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and is formed by a UBM (underbumping metallization) process, but the present application does not limit this and it depends on the specific circumstances.

[0201] S405: Continue to refer Fig.16 A second P electrode 80 electrically connected to the P-type doped region 55 is formed on the side of the second stacked structure 50 away from the common contact layer 40, the second through hole exposes at least a portion of the P-type doped region, and the second P electrode is located in the second through hole and electrically connected to the P-type doped region.

[0202] Optionally, the second P electrode is a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and is formed by a UBM (under bumping metallization) process, but the present application does not limit this and it depends on the specific circumstances.

[0203] Based on the above embodiments, in one embodiment of the present application, the N electrode 70 also extends to cover a portion of the surface of the second stacked structure 50, so that the electrical connection point between the N electrode 70 and the outside world and the electrical connection point between the second P electrode 80 and the outside world are flush, so as to facilitate the electrical connection between the N electrode and the second P electrode and the external structure.

[0204] Based on the above embodiments, in one embodiment of the present application, Fig.17 As shown, the first insulating layer 90 is continuously deposited on the side of the N-electrode 70 away from the P-type doping region 55, so that the first insulating layer 90 covers the side of the N-electrode 70 to insulate and protect the side wall of the N-electrode, thereby reducing the probability of the N-electrode short-circuiting with other structures or the probability of the N-electrode being disconnected due to wear.

[0205] It should be noted that in one embodiment of the present application, the first P electrode, the second P electrode and the N electrode can be formed at the same time. In other embodiments of the present application, the first P electrode, the second P electrode and the N electrode can also be formed sequentially. The present application does not limit this and it depends on the specific circumstances.

[0206] Based on the above embodiments, in one embodiment of the present application, Fig.18 As shown, the method also includes:

[0207] A first electrical connection ball 71 electrically connected to the N electrode is formed on the side of the N electrode 70 away from the top layer 54. Optionally, the first electrical connection ball is an In ball for flip-chip interconnection with a readout circuit.

[0208] A second electrical connection ball 81 electrically connected to the second P electrode is formed on the side of the second P electrode 80 away from the top layer 54. Optionally, the second electrical connection ball is an In ball for flip-chip interconnection with a readout circuit.

[0209] Based on the above embodiments, in one embodiment of the present application, continue to refer to Fig.18 , the method further comprises:

[0210] The side of the substrate 10 away from the first absorption layer 30 is roughly ground and thinned, and then polished, and then a first anti-reflection film 11 is formed on the side of the substrate 10 away from the first absorption layer 30. Optionally, the first anti-reflection film is an AR anti-reflection coating.

[0211] In summary, in the method for manufacturing a dual-color wide-band short-wave infrared detector provided in the embodiment of the present application, an lnP lower contact layer, a first absorption layer, a first stacked structure, a second P electrode and an N electrode are deposited on an lnP substrate, and an nip-type InGaAs detector is formed by using the lnP substrate, the lnP lower contact layer, the first absorption layer, the N-type common contact layer, and the first P electrode and the N electrode to realize short-wave infrared detection in the standard wavelength 0.9μm to 1.7μm spectrum band, and at the same time, the N-type common contact layer, the P-type doped region, the diffusion control layer, the second absorption layer, and the buffer layer are used. And a second P electrode and an N electrode to form a pin-type multi-quantum well structure detector to achieve short-wave infrared detection in the extended wavelength 1.7μm to 2.6μm spectrum band, so as to combine the nip-type InGaAs detector structure with the pin-type InGaAs / GaAsSb two-type MQWs detector structure based on the InP substrate and using the III-V group lattice matching material system, to achieve a dual-color wide-band short-wave infrared pinip-type detector structure design that responds to the standard wavelength 0.9μm to 1.7μm and the extended wavelength 1.7μm to 2.6μm. Moreover, in the method for manufacturing the dual-color wide-band short-wave infrared detector provided in the embodiment of the present application, each component structure is designed with an InP-based III-V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector has a wider response spectrum, higher sensitivity, and better manufacturability.

[0212] In addition, the present application also provides a dual-color wide-band short-wave infrared detector array, such as Fig.19 As shown, the dual-color wide-band short-wave infrared detector array provided in the embodiment of the present application includes:

[0213] A P-type doped InP substrate 10, optionally, the substrate is a single crystal substrate, and the substrate is a Zn-doped InP substrate;

[0214] A P-type doped InP lower contact layer 20 located on the first side surface of the substrate 10;

[0215] The first absorption layer 30 is located on the side of the lower contact layer 20 away from the substrate. The first absorption layer 30 exposes a portion of the lower contact layer 20 and is an intrinsic ln 0.53 Ga 0.47 As layer;

[0216] At least two first stacked structures are located on the surface of the first absorption layer 30 on the side away from the lower contact layer 20, the first stacked structure includes: a stacked common contact layer 40 and a second stacked structure 50, the second stacked structure 50 exposes a portion of the common contact layer 40, and includes: a stacked buffer layer 51, a second absorption layer 52, a diffusion control layer 53 and a top layer 54, and penetrates the top layer 54 along the first direction and extends to a P-type doped region 55 in the diffusion control layer 53;

[0217] A first P electrode 60 located in an exposed area of ​​the lower contact layer 20 and electrically connected to the lower contact layer 20;

[0218] An N-electrode 70 located in an exposed area of ​​the common contact layer 40 and electrically connected to the common contact layer 40 , wherein the N-electrode 70 corresponds to the first stacking structure in a one-to-one manner;

[0219] a second P electrode 80 located at a side of the second stacked structure 50 away from the first absorption layer 30 and electrically connected to the P-type doping region 55 , wherein the second P electrode 80 corresponds to the P-type doping region 55 in a one-to-one manner;

[0220] The common contact layer 40 includes N-type doped ln x Ga 1-x As layer, the buffer layer 51 is an intrinsic InGaAs layer, the second absorption layer 52 includes a multi-quantum well structure, the diffusion control layer 53 is an intrinsic InGaAs layer, and the top layer 54 is an N-type doped InP layer or InAlAs layer.

[0221] It should be noted that, in the embodiment of the present application, the first P electrode 60 is a ring electrode. Fig. 20 As shown, Fig. 20 It is a top view of a dual-color wide-spectrum short-wave infrared detector array, that is, in the embodiment of the present application, the first P electrode surrounds the at least two first stacked structures, and the at least two first stacked structures share the same first P electrode.

[0222] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the lower contact layer ranges from 0.2 μm to 1.0 μm, including the end value. Optionally, the lower contact layer is a Zn-doped lnP layer, and the P-type doping concentration of the lower contact layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0223] Based on the above embodiments, in one embodiment of the present application, the thickness of the first absorption layer ranges from 2.0 μm to 3.5 μm, including the end value, and optionally, the background carrier concentration in the first absorption layer is not greater than 5E+15 cm -3 .

[0224] Specifically, in one embodiment of the present application, the first stacking structure includes:

[0225] The common contact layer 40 is located on the side away from the first absorption layer 30 and away from the substrate 10. Optionally, the common contact layer thickness ranges from 0.1 μm to 1.0 μm, including the end value, and the N-type doping concentration of the common contact layer ranges from 2E+18 cm -3 ~8E+18cm -3 , including endpoint values;

[0226] a buffer layer 51 located on a side of the common contact layer 40 away from the first absorption layer 30;

[0227] A second absorption layer 52 located on a side of the buffer layer 51 away from the common contact layer 40;

[0228] a diffusion control layer 53 located on a side of the second absorption layer 52 away from the buffer layer 51;

[0229] a top layer 54 located on a side of the diffusion control layer 53 away from the second absorption layer 52;

[0230] The first direction X penetrates the top layer 54 and extends to the P-type doping region 55 in the diffusion control layer 53 .

[0231] It should be noted that, in the embodiment of the present application, the buffer layer located between the common contact layer and the second absorption layer is conducive to better growth of the second absorption layer.

[0232] On the basis of the above-mentioned embodiments, in one embodiment of the present application, the multi-quantum well structure includes: a quantum well layer 521 located on the side of the buffer layer 51 away from the common contact layer 40, and a quantum barrier layer 522 located on the side of the quantum well layer 521 away from the buffer layer 51; wherein, a plurality of the quantum well layers 521 and the quantum barrier layers 522 are arranged alternately, and the number of the quantum well layers 521 is one more than the number of the quantum barrier layers 522, so that a layer of the multi-quantum well structure in contact with the buffer layer is a quantum well layer, and a layer of the multi-quantum well structure in contact with the diffusion control layer is also a quantum well layer. Optionally, in the embodiment of the present application, the quantum well layer 521 is a lnGaAs layer, and the quantum barrier layer 522 is a GaAsSb layer.

[0233] It should be noted that, in an embodiment of the present application, the response cutoff wavelength of the second absorption layer is related to the thickness of the second absorption layer. Optionally, in an embodiment of the present application, the multi-quantum well structure includes quantum well layers and quantum barrier layers arranged in an alternating manner for 200 to 300 periods, that is, the number of quantum well layers and quantum barrier layers in the multi-quantum well structure ranges from 200 to 300, including endpoint values, but the present application does not limit this and it depends on the specific circumstances.

[0234] Specifically, in one embodiment of the present application, the quantum well layer is ln 0.53 Ga 0.47 As layer, the thickness of the quantum well layer is 6.4nm; the quantum barrier layer is GaAs 0.51 Sb 1-0.51 The thickness of the quantum barrier layer is 5.0 nm, but this application does not limit this and it depends on the specific situation.

[0235] Based on any of the above embodiments, in one embodiment of the present application, the diffusion control layer is an intrinsic ln 0.53 Ga 0.47 As layer, the intrinsic ln 0.53 Ga 0.47 The background carrier concentration in the As layer is no more than 5E+15cm -3 , so as to control the spatial distribution of Zn diffusion concentration in the diffusion control layer. Optionally, the thickness of the diffusion control layer ranges from 0.5 μm to 1.5 μm, including the endpoint values.

[0236] On the basis of any of the above embodiments, in one embodiment of the present application, the thickness of the top layer ranges from 0.3 μm to 1.5 μm, including the endpoint value, the N-type doping ion in the top layer is Si, and the doping concentration ranges from 1E+16 cm -3 ~5E+16cm -3 , including endpoint values. However, this application does not limit this, and it depends on the specific circumstances.

[0237] Based on any of the above embodiments, in one embodiment of the present application, the P-type doped region is formed by Zn ion diffusion, and the value range of the Zn ion diffusion concentration is 1E+18cm -3 ~5E+18cm -3 , including endpoint values. However, this application does not limit this, and it depends on the specific circumstances.

[0238] Continue to refer Figure 2 , Figure 2A curve diagram showing the change in response quantum efficiency of each dual-color wide-band short-wave infrared detector in the dual-color wide-band short-wave infrared detector array provided by an embodiment of the present application as a function of its spectral response wavelength is shown, wherein curve a is the response spectrum of the nip-type InGaAs detector formed by the lnP substrate, the lnP lower contact layer, the first absorption layer, the N-type common contact layer, the first P electrode and the N electrode in each dual-color wide-band short-wave infrared detector, and curve b is the response spectrum of the pin-type multi-quantum well structure detector formed by each P-type doped region, the diffusion control layer, the second absorption layer, the buffer layer, the N-type common contact layer, the second P electrode and the N electrode in each dual-color wide-band short-wave infrared detector.

[0239] from Figure 2 It can be seen that in the dual-color wide-band short-wave infrared detector array provided in the embodiment of the present application, each dual-color wide-band short-wave infrared detector can use the lnP substrate, the lnP lower contact layer, the first absorption layer, the N-type common contact layer, the first P electrode and the N electrode to form a nip-type InGaAs detector to achieve short-wave infrared detection in the standard wavelength 0.9μm~1.7μm spectrum band, and at the same time use the P-type doping region, the diffusion control layer, the second absorption layer, the buffer layer, the N-type common contact layer, and the second P electrode and the N electrode to form a pin-type multi-quantum well structure detector to achieve short-wave infrared detection in the extended wavelength 1.7μm~2.6μm spectrum band, so that the dual-color wide-band short-wave infrared detector array can achieve dual-color wide-band short-wave infrared detection.

[0240] On the basis of any of the above embodiments, in one embodiment of the present application, the dual-color wide-band short-wave infrared detector array further includes:

[0241] A lower restriction layer 21 is located between the lower contact layer 20 and the first absorption layer 30, wherein the lower restriction layer 21 exposes a portion of the lower contact layer 20, and the first absorption layer 30 is located on the surface of the lower restriction layer 21 away from the lower contact layer 20; optionally, the lower restriction layer is a P-type doped InAlAs layer.

[0242] Specifically, based on the above embodiments, in one embodiment of the present application, the thickness of the lower limiting layer ranges from 0.2 μm to 1.0 μm, including the end value, and the P-type doping concentration of the lower limiting layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0243] It should be noted that in the embodiment of the present application, since the band gap of the lower confinement layer is relatively wide, the lower confinement layer inserted between the lower contact layer and the first absorption layer can inhibit the diffusion of impurities in the substrate and the lower contact layer toward the first absorption layer, which is beneficial to improving the quality of the subsequent epitaxial structure.

[0244] On the basis of any of the above embodiments, in one embodiment of the present application, the first stacking structure further includes:

[0245] a first restriction layer 41 located between the first absorption layer 30 and the common contact layer 40;

[0246] a second restriction layer 42 located between the common contact layer 40 and the buffer layer 51, wherein the second restriction layer 42 exposes a portion of the common contact layer 40, and the buffer layer 51 is located on a surface of the second restriction layer 42 facing away from the common contact layer 40;

[0247] The first confinement layer 41 and the second confinement layer 42 are N-type doped InP layers or N-type doped InAlAs layers.

[0248] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the first restriction layer and the second restriction layer ranges from 0.2 μm to 1.5 μm, including the end value, and the doping ions of the first restriction layer and the second restriction layer are Si, and the doping concentration ranges from 1E+18 cm -3 ~8E+18cm -3 , including the endpoint values.

[0249] It should be noted that, in the above embodiment, the first confinement layer, the common contact layer and the second confinement layer form a double heterojunction, and then form an nBi heterostructure with the second absorption layer, so that the nBi heterostructure can be used to form a hole unipolar barrier at the heterointerface, effectively improving the dark current problem caused by surface recombination.

[0250] From the materials of each component structure in the dual-color wide-band short-wave infrared detector array in the above-mentioned embodiments, it can be seen that each component structure in the dual-color wide-band short-wave infrared detector array provided in the embodiments of the present application is designed with an InP-based III-V group lattice matching material system, so that each dual-color wide-band short-wave infrared detector in the dual-color wide-band short-wave infrared detector array has a wider response spectrum, higher sensitivity and better manufacturability.

[0251] On the basis of the above embodiments, in one embodiment of the present application, the dual-color wide-band short-wave infrared detector array further includes:

[0252] A second insulating layer 91 covering the first stacked structure and a partial area of ​​the lower contact layer 20, wherein the second insulating layer 91 has a first through hole, a plurality of second through holes and a third through hole;

[0253] Among them, the first through hole exposes a partial area of ​​the lower contact layer 20, and the first P electrode 60 is located in the first through hole and electrically connected to the lower contact layer 20; the second through hole exposes at least a partial area of ​​the P-type doped region 55, and the second P electrode 80 is located in the second through hole and electrically connected to the P-type doped region 55; the third through hole exposes a partial area of ​​the common contact layer 40, and the N electrode 70 is located in the third through hole and electrically connected to the common contact layer 40.

[0254] Optionally, based on the above embodiments, in one embodiment of the present application, the first P electrode (i.e., the P lower electrode) is a stacked structure of a Cr electrode and an Au electrode, or a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a metal-semiconductor ohmic contact process; the second P electrode and N electrode are a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a UBM (under bumping metallization) process, but the present application does not limit this and it depends on the specific circumstances.

[0255] Based on the above embodiments, in one embodiment of the present application, the N electrode 70 also extends to cover a portion of the surface of the second stacked structure 50, so that the electrical connection point between the N electrode 70 and the outside world and the electrical connection point between the second P electrode 80 and the outside world are flush, so as to facilitate the electrical connection between the N electrode and the second P electrode and the external structure.

[0256] Based on the above embodiments, in one embodiment of the present application, the second insulating layer 91 also covers the side of the N electrode 70 to insulate and protect the side wall of the N electrode, thereby reducing the probability of the N electrode short-circuiting with other structures or the probability of the N electrode being disconnected due to wear.

[0257] On the basis of the above embodiments, in one embodiment of the present application, the dual-color wide-band short-wave infrared detector array further includes:

[0258] A first electrical connection ball 71 located at a side of the N electrode 70 away from the top layer 54 and electrically connected to the N electrode. Optionally, the first electrical connection ball is an In ball for flip-chip interconnection with a readout circuit;

[0259] A second electrical connection ball 81 located at a side of the second P electrode 80 away from the top layer 54 and electrically connected to the second P electrode. Optionally, the second electrical connection ball is an In ball for flip-chip interconnection with a readout circuit;

[0260] The first antireflection film 11 is located on the side of the substrate 10 away from the first absorption layer 30. Optionally, the first antireflection film is an AR antireflection coating.

[0261] In summary, the dual-color wide-spectrum short-wave infrared detector array provided in the embodiment of the present application includes an lnP substrate, an lnP lower contact layer, a first absorption layer, a plurality of first stacked structures, a first P electrode, and a second P electrode and an N electrode. The lnP substrate, the lnP lower contact layer, the first absorption layer, the N-type common contact layer in the plurality of first stacked structures, and the first P electrode and the N electrode are used to form a plurality of nip-type InGaAs detectors to achieve short-wave infrared detection in the standard wavelength 0.9μm to 1.7μm spectrum band. At the same time, the P-type doping region, the diffusion control layer, the second absorption layer in the plurality of first stacked structures are used. , a buffer layer, an N-type common contact layer and the corresponding second P electrode and N electrode form a plurality of pin-type multi-quantum well structure detectors to realize short-wave infrared detection in the extended wavelength 1.7μm to 2.6μm spectrum band, so that based on the InP substrate and using a III-V group lattice matching material system, the plurality of nip-type InGaAs detectors correspond one-to-one with the plurality of pin-type multi-quantum well structure detectors and are combined to realize a dual-color wide-band short-wave infrared pinip-type detector structure design that responds to a standard wavelength of 0.9μm to 1.7μm and an extended wavelength of 1.7μm to 2.6μm.

[0262] Moreover, in the dual-color wide-band short-wave infrared detector array provided in the embodiment of the present application, each component structure is designed using an InP-based III-V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector array has a wider response spectrum, higher sensitivity, and better manufacturability.

[0263] Correspondingly, an embodiment of the present application also provides a method for manufacturing a dual-color, wide-spectrum, short-wave infrared detector array, which is used to manufacture the dual-color, wide-spectrum, short-wave infrared detector array provided by any of the above embodiments.

[0264] It should be noted that in one embodiment of the present application, MOCVD epitaxial technology is used to produce the dual-color wide-spectrum short-wave infrared detector array provided in any of the above embodiments, but the present application is not limited to this. MBE epitaxial technology can also be used to produce the dual-color wide-spectrum short-wave infrared detector array provided in any of the above embodiments, depending on the specific circumstances.

[0265] Specifically, Fig.21 As shown, the method for manufacturing the dual-color wide-band short-wave infrared detector array provided in the embodiment of the present application includes:

[0266] S10: Fig. 22 As shown, a stacked structure is formed on the first side surface of the P-type doped InP substrate 10, and the stacked structure includes a stacked lower contact layer 20, a first absorption layer 30, a common contact layer 40, a buffer layer 51, a second absorption layer 52, a diffusion control layer 53 and a top layer 54.

[0267] In one embodiment of the present application, the substrate is a single crystal substrate, and the substrate is a Zn-doped InP substrate, which is not limited in the present application and depends on the specific circumstances.

[0268] Specifically, based on the above embodiments, in one embodiment of the present application, forming a stacked structure on the first side surface of the P-type doped InP substrate 10 includes:

[0269] Forming a lower contact layer 20 on a first side surface of a P-type doped InP substrate 10;

[0270] A first absorption layer 30 is formed on the side of the lower contact layer 20 away from the substrate 10. The first absorption layer is an intrinsic ln 0.53 Ga 0.47 As layer;

[0271] A common contact layer 40 is formed on the side of the first absorption layer 30 away from the substrate 10. The common contact layer includes an N-type doped ln x Ga 1-x As layer;

[0272] A buffer layer 51 is formed on the side of the common contact layer 40 away from the first absorption layer 30, wherein the buffer layer is an intrinsic InGaAs layer;

[0273] A second absorption layer 52 is formed on a side of the buffer layer 51 away from the common contact layer 40, wherein the second absorption layer includes a multi-quantum well structure;

[0274] A diffusion control layer 53 is formed on the side of the second absorption layer 52 away from the buffer layer 51, and the diffusion control layer is an intrinsic InGaAs layer;

[0275] A top layer 54 is formed on the side of the diffusion control layer 53 away from the second absorption layer 52 , and the top layer is an N-type doped InP layer or InAlAs layer.

[0276] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the lower contact layer ranges from 0.2 μm to 1.0 μm, including the end value. Optionally, the lower contact layer is a Zn-doped lnP layer, and the P-type doping concentration of the lower contact layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0277] Based on the above embodiments, in one embodiment of the present application, the thickness of the first absorption layer ranges from 2.0 μm to 3.5 μm, including the end value, and optionally, the background carrier concentration in the first absorption layer is not greater than 5E+15 cm -3 .

[0278] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the common contact layer ranges from 0.1 μm to 1.0 μm, including the endpoint value, and the N-type doping concentration of the common contact layer ranges from 2E+18 cm -3 ~8E+18cm -3 , including the endpoint values.

[0279] It should be noted that, based on the above embodiments, in one embodiment of the present application, the buffer layer located between the common contact layer and the second absorption layer is conducive to better growth of the second absorption layer.

[0280] Based on the above embodiments, in one embodiment of the present application, continue to refer to Fig. 22 , forming a second absorption layer 52 on the side of the buffer layer 51 away from the common contact layer 40 includes:

[0281] A quantum well layer 521 is formed on the side of the buffer layer 51 away from the common contact layer 40, and a quantum barrier layer 522 is formed on the side of the quantum well layer 521 away from the buffer layer 51; wherein, a plurality of the quantum well layers 521 and the quantum barrier layers 522 are alternately arranged, the number of the quantum well layers 521 is one more than the number of the quantum barrier layers 522, and optionally, the quantum well layer 521 is a lnGaAs layer, and the quantum barrier layer 522 is a GaAsSb layer.

[0282] It should be noted that, in the above embodiments, the response cutoff wavelength of the second absorption layer is related to the thickness of the second absorption layer. Optionally, in one embodiment of the present application, the multi-quantum well structure includes quantum well layers and quantum barrier layers that are staggered in 200 to 300 cycles, that is, the number of quantum well layers and quantum barrier layers in the multi-quantum well structure ranges from 200 to 300, including endpoint values, but the present application does not limit this and it depends on the specific circumstances.

[0283] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the quantum well layer is 6.4 nm. Optionally, the thickness of the quantum well layer is ln 0.53 Ga 0.47 As layer; the thickness of the quantum barrier layer is 5.0nm, optionally, the quantum barrier layer is GaAs 0.51 Sb 0.49This application does not limit this, and it depends on the specific circumstances.

[0284] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the diffusion control layer ranges from 0.5 μm to 1.5 μm, including the end value, and optionally, the diffusion control layer is an intrinsic ln 0.53 Ga 0.47 As layer, the intrinsic ln 0.53 Ga 0.47 The background carrier concentration in the As layer is no more than 5E+15cm -3 , so as to control the spatial distribution of Zn diffusion concentration in the diffusion control layer.

[0285] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the top layer ranges from 0.3 μm to 1.5 μm, including the end value, the doping ion of the top layer is Si, and the doping concentration ranges from 1E+16 cm -3 ~5E+16cm -3 , including the endpoint values.

[0286] S20: Fig.23 As shown, P-type doping regions 55 are formed in a plurality of first regions of the top layer 54 , and the P-type doping regions 55 extend into the diffusion control layer 53 .

[0287] On the basis of the above embodiments, in one embodiment of the present application, the P-type doping region is Zn ion diffused, and the diffusion concentration range is 1E+18cm -3 ~5E+18cm -3 , including the endpoint values.

[0288] On the basis of the above embodiments, in one embodiment of the present application, a P-type doping region is formed in a plurality of first regions of the top layer, and the P-type doping region extends into the diffusion control layer, comprising:

[0289] A third dielectric film layer is deposited on the side of the top layer away from the diffusion control layer. Optionally, the third dielectric film layer is SiN X The dielectric film layer may be SiO 2 Dielectric film layer;

[0290] Performing photolithography on the third dielectric film layer so that the third dielectric film layer forms a third dielectric pattern exposing a plurality of first regions;

[0291] Using the third dielectric pattern as a mask, using a diffusion process, ion diffusion is performed in the plurality of first regions of the top layer 54 to form P-type doping regions 55 in the plurality of first regions of the top layer, and the P-type doping regions 55 extend to the diffusion control layer;

[0292] The third medium pattern is removed.

[0293] S30: Fig.24 As shown, the stacked structure is etched to the lower contact layer 20 to expose the second region of the lower contact layer 20 .

[0294] Based on the above embodiment, in one embodiment of the present application, etching the stack structure to the lower contact layer to expose the second region of the lower contact layer includes:

[0295] A fourth dielectric film layer is deposited on the side of the stacked structure away from the substrate, and the fourth dielectric film layer is passivated so that the fourth dielectric film layer plays a role in protecting the surface of the dual-color wide-spectrum short-wave infrared detector array. Optionally, the fourth dielectric film layer is SiN X Dielectric film, SiO 2 Dielectric film or Al 2 O 3 Dielectric film layer;

[0296] Using the fourth dielectric film layer as a mask, etching the second region of the stacked structure to expose the lower contact layer, wherein the second region is used to subsequently form a first P electrode;

[0297] The fourth dielectric film layer is removed.

[0298] It should be noted that, in one embodiment of the present application, the stacked structure is etched to the lower contact layer, just exposing the second region of the lower contact layer. In another embodiment of the present application, the stacked structure is etched to the lower contact layer and does not exceed the lower contact layer, exposing the second region of the lower contact layer. However, the present application does not limit this. It is only necessary to ensure that the stacked structure is etched to the lower contact layer and the second region of the lower contact layer is exposed, depending on the specific circumstances.

[0299] S40: Fig.25 As shown, the stacked structure is etched to the first absorption layer 30 to form at least two first stacked structures, and the first stacked structures correspond to the P-type doping regions 55 one by one.

[0300] Based on the above embodiment, in one embodiment of the present application, etching the stacked structure to the first absorption layer to form at least two first stacked structures includes:

[0301] A fifth dielectric film layer is deposited on the side of the stacked structure away from the substrate. Optionally, the fifth dielectric film layer is SiN X Dielectric film, SiO 2 Dielectric film or Al2 O 3 Dielectric film layer;

[0302] Performing photolithography on the fifth dielectric film layer so that the fifth dielectric film layer forms a fifth dielectric pattern exposing the fourth region of the stacked structure, and passivating the fifth dielectric pattern so that the fifth dielectric pattern plays a role in protecting the surface of the dual-color wide-spectrum short-wave infrared detector array;

[0303] The stacked structure is etched using the fifth dielectric pattern as a mask to expose the first absorption layer and form a shallow mesa, so that the stacked structure forms at least two first stacked structures.

[0304] It should be noted that, in one embodiment of the present application, the stacked structure is etched to the first absorption layer, just exposing the first absorption layer. In another embodiment of the present application, the stacked structure is etched to the first absorption layer and does not exceed the first absorption layer. However, the present application does not limit this. It is only necessary to ensure that the stacked structure is etched to expose the first absorption layer, depending on the specific circumstances.

[0305] It should also be noted that, in the embodiment of the present application, the stacked structure is etched to the first absorption layer to expose the first absorption layer and avoid etching the side wall of the first absorption layer, which can reduce the dark current problem caused by the surface state of the dual-color wide-band short-wave infrared detector array.

[0306] S50: Fig.26 As shown, the at least two first stacked structures are etched to the common contact layer 40 to form at least two second stacked structures 50 , and the second stacked structures 50 correspond to the first stacked structures one by one.

[0307] On the basis of the above embodiments, in one embodiment of the present application, etching the at least two first stacked structures to the common contact layer to form at least two second stacked structures includes:

[0308] A sixth dielectric film layer is deposited on the side of the stacked structure away from the substrate. Optionally, the sixth dielectric film layer is SiN X Dielectric film, SiO 2 Dielectric film or Al 2 O 3 Dielectric film layer;

[0309] Performing photolithography on the sixth dielectric film layer so that the sixth dielectric film layer forms a sixth dielectric pattern exposing the third region of the stacked structure, and passivating the sixth dielectric pattern so that the sixth dielectric pattern plays a role in protecting the surface of the dual-color wide-spectrum short-wave infrared detector array;

[0310] Using the sixth dielectric pattern as a mask, etching the third region of the at least two first stacked structures to expose the common contact layer, wherein the third region is used for subsequently forming an N electrode;

[0311] The sixth medium pattern is removed.

[0312] It should be noted that, in one embodiment of the present application, the first stacking structure is etched to the common contact layer, just exposing the common contact layer. In another embodiment of the present application, the first stacking structure is etched to the common contact layer and does not exceed the common contact layer. However, the present application does not limit this. It is only necessary to ensure that the first stacking structure is etched to expose the common contact layer, depending on the specific circumstances.

[0313] On the basis of any of the above embodiments, in one embodiment of the present application, etching the stacked structure includes: etching the stacked structure using a dry etching process; in another embodiment of the present application, etching the stacked structure includes: etching the stacked structure using a wet etching process; in other embodiments of the present application, other processes may also be used to etch the stacked structure, and the present application does not limit this, depending on the specific circumstances.

[0314] Based on any of the above embodiments, in one embodiment of the present application, Fig. 27 As shown, the stacking structure also includes:

[0315] A lower confinement layer 21 is formed between the lower contact layer 20 and the first absorption layer 30, the lower confinement layer 21 exposes a portion of the lower contact layer 20, and the first absorption layer 30 is located on the surface of the lower confinement layer 21 on a side away from the lower contact layer 20; optionally, the lower confinement layer is a P-type doped lnAlAs layer. It should be noted that in the embodiment of the present application, when the stacked structure is etched to expose a portion of the lower contact layer, the lower confinement layer is also etched to expose a portion of the lower contact layer.

[0316] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the lower limiting layer ranges from 0.2 μm to 1.0 μm, including the end value, and the P-type doping concentration of the lower limiting layer ranges from 1E+18 cm -3 ~5E+18cm -3 , including the endpoint values.

[0317] It should be noted that in the embodiment of the present application, the band gap of the lower confinement layer is relatively wide. The lower confinement layer inserted between the lower contact layer and the first absorption layer can inhibit the diffusion of impurities in the substrate and the lower contact layer toward the first absorption layer, which is beneficial to improving the quality of the subsequent epitaxial structure.

[0318] Based on any of the above embodiments, in one embodiment of the present application, continue to refer to Fig. 27 , the stacking structure further comprises:

[0319] A first restriction layer 41 is formed between the first absorption layer 30 and the common contact layer 40 ; a second restriction layer 42 is formed between the common contact layer 40 and the buffer layer 51 , the second restriction layer 42 exposes a portion of the common contact layer 40 , and the buffer layer 51 is located on the surface of the second restriction layer 42 facing away from the common contact layer 40 .

[0320] It should be noted that, when the first stacked structure further includes a first restriction layer and a second restriction layer, etching the first stacked structure further includes etching the second restriction layer to expose a portion of the surface of the third region of the common contact layer.

[0321] It should also be noted that, in the embodiment of the present application, the etching depth of the third region can be the sum of the thicknesses of the second restriction layer and the second stacking structure, or can be greater than the sum of the thicknesses of the second restriction layer and the second stacking structure, and less than the sum of the thicknesses of the second restriction layer, the second stacking structure and the common contact layer. The present application does not limit this, as long as a portion of the third region of the common contact layer is exposed to facilitate the subsequent formation of an N electrode electrically connected to the common contact layer.

[0322] Specifically, in one embodiment of the present application, the first confinement layer 41 and the second confinement layer 42 are N-type doped InP layers or N-type doped InAlAs layers.

[0323] On the basis of the above embodiments, in one embodiment of the present application, the thickness of the first limiting layer and the second limiting layer ranges from 0.2 μm to 1.5 μm, including the end value, the doping ion is Si, and the doping concentration ranges from 1E+18 cm -3 ~8E+18cm -3 , including the endpoint values.

[0324] It should be noted that, in the above embodiment, the first confinement layer, the common contact layer and the second confinement layer form a double heterojunction, and then form an nBi heterostructure with the second absorption layer, so that the nBi heterostructure can be used to form a hole unipolar barrier at the heterointerface, effectively improving the dark current problem caused by surface recombination.

[0325] Based on the above embodiments, in one embodiment of the present application, Fig.28 As shown, the method for manufacturing the dual-color wide-band short-wave infrared detector array also includes:

[0326] A second insulating layer 91 is formed on the surface of the entire dual-color wide-spectrum short-wave infrared detector array, and the second insulating layer 91 has a first through hole, a plurality of second through holes and a third through hole.

[0327] S60: Fig.29 As shown, a first P electrode 60 electrically connected to the lower contact layer 20 is formed in the exposed area of ​​the lower contact layer 20 , wherein the first P electrode 60 is located in the first through hole.

[0328] S70: Continue to refer Fig.29 An N-electrode 70 electrically connected to the common contact layer 40 is formed in the exposed area of ​​the common contact layer 40 , wherein the N-electrode 70 is located in the third through hole.

[0329] S80: Continue to refer Fig.29 A second P electrode 80 electrically connected to the P-type doping region 55 is formed on a side of the second stacked structure 50 away from the common contact layer 40 , wherein the second P electrode 80 is located in the second through hole.

[0330] Optionally, based on the above embodiments, in one embodiment of the present application, the first P electrode (i.e., the P lower electrode) is a stacked structure of a Cr electrode and an Au electrode, or a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a metal-semiconductor ohmic contact process; the second P electrode and N electrode are a stacked structure of a Ti electrode, a Pt electrode and an Au electrode, and the formation process is a UBM (under bumping metallization) process, but the present application does not limit this and it depends on the specific circumstances.

[0331] Based on the above embodiments, in one embodiment of the present application, the N electrode 70 also extends to cover a portion of the surface of the second stacked structure 50, so that the electrical connection point between the N electrode 70 and the outside world and the electrical connection point between the second P electrode 80 and the outside world are flush, so as to facilitate the electrical connection between the N electrode and the second P electrode and the external structure.

[0332] Based on the above embodiments, in one embodiment of the present application, continue to refer to Fig.29 The second insulating layer 91 also covers the side of the N electrode 70 to insulate and protect the side wall of the N electrode, thereby reducing the probability of the N electrode being short-circuited with other structures or the probability of the N electrode being disconnected due to wear.

[0333] Based on the above embodiments, in one embodiment of the present application, Fig.30 As shown, the method for manufacturing the dual-color wide-band short-wave infrared detector array also includes:

[0334] Roughly grinding and thinning the side of the substrate 10 away from the first absorption layer 30, and then polishing;

[0335] A first anti-reflection film 11 is formed on the side of the substrate 10 away from the first absorption layer 30 . Optionally, the first anti-reflection film is an AR anti-reflection coating film.

[0336] Based on the above embodiments, in one embodiment of the present application, Fig.31 As shown, the method for manufacturing the dual-color wide-band short-wave infrared detector array also includes:

[0337] A first electrical connection ball 71 electrically connected to the N electrode is formed on the side of the N electrode 70 away from the top layer 54. Optionally, the first electrical connection ball is an In ball for flip-chip interconnection with a readout circuit.

[0338] A second electrical connection ball 81 electrically connected to the second P electrode is formed on the side of the second P electrode 80 away from the top layer 54. Optionally, the second electrical connection ball is an In ball for flip-chip interconnection with a readout circuit.

[0339] In summary, in the method for manufacturing a dual-color wide-band short-wave infrared detector array provided in the embodiment of the present application, an lnP lower contact layer, a first absorption layer, a plurality of first stacked structures, a first P electrode, a second P electrode and an N electrode are formed on an lnP substrate, and a plurality of nip-type InGaAs detectors are formed by using the lnP substrate, the lnP lower contact layer, the first absorption layer, the N-type common contact layer in the plurality of first stacked structures, and the first P electrode and the N electrode to achieve short-wave infrared detection in the standard wavelength 0.9 to 1.7 μm spectrum band, and at the same time, the P-type doping region, the diffusion control layer in the plurality of first stacked structures are used. , a second absorption layer, a buffer layer, an N-type common contact layer and the corresponding second P electrode and N electrode form a plurality of pin-type multi-quantum well structure detectors to realize short-wave infrared detection in the extended wavelength 1.7 to 2.6 μm spectrum band. Based on the InP substrate and adopting the III-V group lattice matching material system, the plurality of nip-type InGaAs detectors correspond one-to-one with the plurality of pin-type multi-quantum well structure detectors and are combined to realize the dual-color wide-band short-wave infrared pinip-type detector structure design that responds to the standard wavelength 0.9 μm to 1.7 μm and the extended wavelength 1.7 μm to 2.6 μm.

[0340] Moreover, in the dual-color wide-band short-wave infrared detector array provided in the embodiment of the present application, each component structure is designed using an InP-based III-V group lattice matching material system, so that the dual-color wide-band short-wave infrared detector array has a wider response spectrum, higher sensitivity, and better manufacturability.

[0341] The various parts in this manual are described in a progressive manner, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.

[0342] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dual-color, wide-band, short-wave infrared detector. It is characterized in that include: P-type doped lnP substrate; A P-type doped InP lower contact layer located on the first side surface of the substrate; A first absorption layer is located on the side of the lower contact layer away from the substrate, wherein the first absorption layer exposes a portion of the lower contact layer and is an intrinsic ln 0.53 Ga 0.47 As layer; A first stacking structure located on a surface of the first absorption layer facing away from the lower contact layer, the first stacking structure comprising: a stacked common contact layer and a second stacking structure, the second stacking structure exposing a portion of the common contact layer, comprising: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, and a P-type doping region extending from the top layer to the diffusion control layer along a first direction; A first P electrode located in the exposed area of ​​the lower contact layer and electrically connected to the lower contact layer; An N electrode located in an exposed area of ​​the common contact layer and electrically connected to the common contact layer; a second P electrode located at a side of the second stacked structure away from the first absorption layer and electrically connected to the P-type doping region; Wherein, the common contact layer comprises N-type doped ln x Ga 1-x As layer, the buffer layer is an intrinsic lnGaAs layer, the second absorption layer comprises a multi-quantum well structure, the multi-quantum well structure comprises alternately stacked quantum well layers and quantum barrier layers, the quantum well layer is a lnGaAs layer, the quantum barrier layer is a GaAsSb layer, the diffusion control layer is an intrinsic lnGaAs layer, and the top layer is an N-type doped lnP layer or a lnAlAs layer.

2. The dual-color, wide-band, short-wave infrared detector according to claim 1, It is characterized in that The number of the quantum well layers is greater than the number of the quantum barrier layers by one.

3. The dual-color wide-band short-wave infrared detector according to claim 1, It is characterized in that Also includes: a lower limiting layer located between the lower contact layer and the first absorbing layer, the lower limiting layer exposing a portion of the lower contact layer, and the first absorbing layer being located on a surface of the lower limiting layer facing away from the lower contact layer; The lower confinement layer is a P-type doped InAlAs layer.

4. The dual-color, wide-band, short-wave infrared detector according to claim 3, It is characterized in that The thickness of the lower limiting layer ranges from 0.2 μm to 1.0 μm, including the end points.

5. The dual-color, wide-band, short-wave infrared detector according to claim 1, It is characterized in that The first stacking structure further includes: a first confinement layer between the first absorbing layer and the common contact layer; a second restriction layer located between the common contact layer and the buffer layer, the second restriction layer exposing a portion of the common contact layer, and the buffer layer being located on a surface of the second restriction layer facing away from the common contact layer; The first confinement layer and the second confinement layer are N-type doped InP layers or N-type doped InAlAs layers.

6. The dual-color, wide-band, short-wave infrared detector according to claim 5, It is characterized in that The thickness of the first restriction layer and the second restriction layer ranges from 0.2 μm to 1.5 μm, including the end points.

7. The dual-color, wide-band, short-wave infrared detector according to claim 1, It is characterized in that Also includes: A first insulating layer covering the first stacked structure and a partial area of ​​the lower contact layer, wherein the first insulating layer has a first through hole, a second through hole and a third through hole; Among them, the first through hole exposes a partial area of ​​the lower contact layer, and the first P electrode is located in the first through hole and electrically connected to the lower contact layer; the second through hole exposes at least a partial area of ​​the P-type doped region, and the second P electrode is located in the second through hole and electrically connected to the P-type doped region; the third through hole exposes a partial area of ​​the common contact layer, and the N electrode is located in the third through hole and electrically connected to the common contact layer.

8. The dual-color, wide-band, short-wave infrared detector according to claim 7, It is characterized in that The N electrode further extends to cover a portion of the surface of the second stacked structure.

9. A method for manufacturing a dual-color wide-band short-wave infrared detector. It is characterized in that include: Forming a P-type doped InP lower contact layer on the first side surface of the P-type doped InP substrate; A first absorption layer is formed on the side of the lower contact layer away from the substrate, the first absorption layer exposes a portion of the lower contact layer, and a first stacking structure is formed on the surface of the first absorption layer away from the lower contact layer, the first stacking structure includes: a stacked common contact layer and a second stacking structure, the second stacking structure exposes a portion of the common contact layer, and includes: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, and a P-type doping region extending into the diffusion control layer through the top layer in a first direction, the first absorption layer is an intrinsic ln 0.53 Ga 0.47 As layer; forming a first P electrode electrically connected to the lower contact layer in the exposed area of ​​the lower contact layer; forming an N electrode electrically connected to the common contact layer in an exposed area of ​​the common contact layer; forming a second P electrode electrically connected to the P-type doping region on a side of the second stacked structure away from the common contact layer; Wherein, the common contact layer comprises N-type doped ln x Ga 1-x As layer, the buffer layer is an intrinsic lnGaAs layer, the second absorption layer comprises a multi-quantum well structure, the multi-quantum well structure comprises alternately stacked quantum well layers and quantum barrier layers, the quantum well layer is a lnGaAs layer, the quantum barrier layer is a GaAsSb layer, the diffusion control layer is an intrinsic lnGaAs layer, and the top layer is an N-type doped lnP layer or a lnAlAs layer.

10. The method according to claim 9, It is characterized in that Also includes: A lower limiting layer is formed between the lower contact layer and the first absorbing layer, wherein the lower limiting layer exposes a portion of the lower contact layer, and the first absorbing layer is located on a surface of the lower limiting layer facing away from the lower contact layer; The lower confinement layer is a P-type doped InAlAs layer.

11. The method according to claim 9, It is characterized in that The first stacking structure further includes: a first confinement layer between the first absorbing layer and the common contact layer; a second restriction layer located between the common contact layer and the buffer layer, the second restriction layer exposing a portion of the common contact layer, and the buffer layer being located on a surface of the second restriction layer facing away from the common contact layer; The first confinement layer and the second confinement layer are N-type doped InP layers or N-type doped InAlAs layers.

12. A dual-color wide-band short-wave infrared detector array, It is characterized in that include: P-type doped lnP substrate; A P-type doped InP lower contact layer located on the first side surface of the substrate; A first absorption layer is located on the side of the lower contact layer away from the substrate, wherein the first absorption layer exposes a portion of the lower contact layer and is an intrinsic ln 0.53 Ga 0.47 As layer; At least two first stacked structures are located on the surface of the first absorption layer on a side away from the lower contact layer, the first stacked structure includes: a stacked common contact layer and a second stacked structure, the second stacked structure exposes a portion of the common contact layer, includes: a stacked buffer layer, a second absorption layer, a diffusion control layer and a top layer, penetrates the top layer along a first direction, and extends to a P-type doped region in the diffusion control layer; A first P electrode located in the exposed area of ​​the lower contact layer and electrically connected to the lower contact layer; An N-electrode located in an exposed area of ​​the common contact layer and electrically connected to the common contact layer, wherein the N-electrode corresponds to the first stacked structure in a one-to-one manner; a second P electrode located at a side of the second stacked structure away from the first absorption layer and electrically connected to the P-type doping region, the second P electrode corresponding to the P-type doping region in a one-to-one manner; Wherein, the common contact layer comprises N-type doped ln x Ga 1-x As layer, the buffer layer is an intrinsic lnGaAs layer, the second absorption layer comprises a multi-quantum well structure, the multi-quantum well structure comprises alternately stacked quantum well layers and quantum barrier layers, the quantum well layer is a lnGaAs layer, the quantum barrier layer is a GaAsSb layer, the diffusion control layer is an intrinsic lnGaAs layer, and the top layer is an N-type doped lnP layer or a lnAlAs layer.

13. The dual-color wide-band short-wave infrared detector array according to claim 12, It is characterized in that Also includes: a lower limiting layer located between the lower contact layer and the first absorbing layer, the lower limiting layer exposing a portion of the lower contact layer, and the first absorbing layer being located on a surface of the lower limiting layer facing away from the lower contact layer; The lower confinement layer is a P-type doped InAlAs layer.

14. The dual-color wide-band short-wave infrared detector array according to claim 12, It is characterized in that The first stacking structure further includes: a first confinement layer between the first absorbing layer and the common contact layer; a second restriction layer located between the common contact layer and the buffer layer, the second restriction layer exposing a portion of the common contact layer, and the buffer layer being located on a surface of the second restriction layer facing away from the common contact layer; The first confinement layer and the second confinement layer are N-type doped InP layers or N-type doped InAlAs layers.

15. A method for manufacturing a dual-color wide-band short-wave infrared detector array, It is characterized in that Used to manufacture the dual-color wide-band short-wave infrared detector array according to any one of claims 12 to 14, the manufacturing method comprising: Forming a stacking structure on the first side surface of the P-type doped InP substrate, the stacking structure comprising a stacked lower contact layer, a first absorption layer, a common contact layer, a buffer layer, a second absorption layer, a diffusion control layer and a top layer; forming a P-type doped region in a plurality of first regions of the top layer, wherein the P-type doped region extends into the diffusion control layer; Etching the stack structure to the lower contact layer to expose a second region of the lower contact layer; Etching the stacked structure to the first absorption layer to form at least two first stacked structures, wherein the first stacked structures correspond to the P-type doped regions one by one; Etching the at least two first stacked structures to the common contact layer to form at least two second stacked structures, wherein the second stacked structures correspond to the first stacked structures one by one; forming a first P electrode electrically connected to the lower contact layer in the exposed area of ​​the lower contact layer; forming an N electrode electrically connected to the common contact layer in an exposed area of ​​the common contact layer; A second P electrode electrically connected to the P-type doping region is formed on a side of the second stacked structure away from the common contact layer.

16. The method according to claim 15, It is characterized in that Forming a P-type doping region in a plurality of first regions of the top layer, wherein the P-type doping region extends into the diffusion control layer, comprises: A diffusion process is used to form P-type doping regions in a plurality of first regions of the top layer, and the P-type doping regions extend into the diffusion control layer.

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