Multi-type distributed management method and device for payment revocation

Abstract

Embodiments of the present application provide a multi-type distributed management method and device for payment revocation, the method comprising: obtaining processor cores participating in synchronization operation, and determining a manager processor core and a participant processor core in the processor cores; and setting a synchronization mark bit corresponding to the participant processor core in the manager processor core; when a synchronization operation request is received, marking the synchronization mark bit in the manager processor core as 1 according to a request processor core, and clearing the synchronization mark bit when a completion signal of the synchronization operation request is received; when a synchronization revocation request is received, detecting that the synchronization mark bit corresponding to the request processor core is 1, and revoking the synchronization mark bit corresponding to the request processor core. The method can support concurrency of in-array synchronization operation and corresponding synchronization revocation operation, and when it is found that there is an unfinished synchronization, a synchronization revocation request can be sent to the manager processor core to revoke the unfinished synchronization operation, so as to perform a job reservation recovery process.

Description

Technical Field

[0001] This invention relates to the field of multiprocessor technology, and in particular to a multi-type distributed management method and apparatus for payment revocation. Background Technology

[0002] Synchronization operations between multiple processor cores are frequent. To improve synchronization efficiency, hardware devices provide distributed synchronization management to achieve concurrent synchronization. However, during multiple concurrent synchronizations, the differences in execution flows among different processing cores lead to significant variations in their states. For a single synchronization, some processing cores may have already reached the synchronization point, while others may not, meaning the entire processor is in an intermediate state during synchronization. Job retention and recovery are frequently required based on the processor system workflow.

[0003] Traditionally, the state during synchronization is not favorable for the preservation and recovery execution process, which means that the preservation and recovery snapshot point must avoid these program segments and can only be performed before synchronization is initiated or after all synchronization is completed. Summary of the Invention

[0004] To address the problems existing in the prior art, embodiments of the present invention provide a multi-type distributed management method and apparatus for payment revocation.

[0005] This invention provides a multi-type distributed management method for payment revocation, including:

[0006] The processor cores participating in the synchronization operation are obtained, and the manager processor core and the participant processor cores among the processor cores are determined. The manager processor core is the processor core with the first number among the processor cores, and the participant processor cores are the other processor cores among the processor cores besides the manager processor core.

[0007] Obtain the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation, and set the corresponding synchronization flag bit in the manager processor core according to the synchronization bit;

[0008] When a synchronization operation request is received, all request processor cores corresponding to the synchronization operation request are obtained, and the synchronization flag bit in the manager processor core is marked as 1 according to the request processor core. When the completion signal of the synchronization operation request is received, the synchronization flag bit corresponding to the request processor core is cleared.

[0009] During the synchronization operation, when a synchronization cancellation request is received, it is detected whether the synchronization flag bit corresponding to the request processor core is 1, and when the synchronization flag bit corresponding to the request processor core is detected to be 1, the synchronization flag bit corresponding to the request processor core is cancelled.

[0010] In one embodiment, the method further includes:

[0011] When multiple synchronization operation requests are received, the range of request processor cores corresponding to each synchronization operation request is obtained, and the overlapping processor cores in the range of request processor cores are obtained.

[0012] When performing the synchronization operation of the multiple synchronization operation requests, the corresponding synchronization flag bit in the overlapping processor core is marked as 1.

[0013] In one embodiment, the method further includes:

[0014] The manager processor core generates a synchronization cancellation completion signal corresponding to the request processor core and sends it to the participant processor core.

[0015] In one embodiment, the method further includes:

[0016] Change the synchronization flag bit corresponding to the request processor core from flag 1 to flag 0.

[0017] In one embodiment, the method further includes:

[0018] Delete the synchronization flag bit in the manager processor core that corresponds to the request processor core.

[0019] This invention provides a multi-type distributed management device for payment revocation, comprising:

[0020] The first acquisition module is used to acquire the processor cores participating in the synchronization operation, and to determine the manager processor core and the participant processor cores among the processor cores. The manager processor core is the processor core with the first number among the processor cores, and the participant processor cores are the other processor cores among the processor cores besides the manager processor core.

[0021] The second acquisition module is used to acquire the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation, and set the corresponding synchronization flag bit in the manager processor core according to the synchronization bit.

[0022] The clearing module is used to obtain all request processor cores corresponding to the synchronization operation request when a synchronization operation request is received, mark the synchronization flag bit in the manager processor core as 1 according to the request processor core, and clear the synchronization flag bit corresponding to the request processor core when a completion signal of the synchronization operation request is received.

[0023] The cancellation module is used to, when a synchronization cancellation request is received during the synchronization operation, detect whether the synchronization flag bit corresponding to the request processor core is 1, and cancel the synchronization flag bit corresponding to the request processor core when the synchronization flag bit corresponding to the request processor core is detected to be 1.

[0024] In one embodiment, the device further includes:

[0025] The third acquisition module is used to acquire the range of request processor cores corresponding to each synchronization operation request when multiple synchronization operation requests are received, and to acquire overlapping processor cores in the range of request processor cores.

[0026] The marking module is used to mark the corresponding synchronization flag bit in the overlapping processor core as 1 when performing the synchronization operation of the multiple synchronization operation requests.

[0027] In one embodiment, the device further includes:

[0028] The sending module is used by the manager processor core to generate a synchronization cancellation completion signal corresponding to the request processor core and send it to the participant processor core.

[0029] This invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the aforementioned multi-type distributed management method for payment revocation.

[0030] This invention provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the aforementioned multi-type distributed management method for payment revocation.

[0031] This invention provides a multi-type distributed management method and apparatus for payment revocation. The method involves acquiring the processor cores participating in the synchronization operation and identifying the manager processor core and participant processor cores. The manager processor core is the processor core with the highest number among the processor cores, and the participant processor cores are the other processor cores besides the manager processor core. The method acquires the synchronization bit of each participant processor core when it reaches a synchronization point during the synchronization operation and sets a corresponding synchronization flag bit in the manager processor core based on the synchronization bit. When a synchronization operation request is received, the method acquires all requesting processor cores corresponding to the synchronization operation request and marks the synchronization flag bit in the manager processor core as 1 based on the requesting processor cores. Upon receiving a completion signal for the synchronization operation request, the method clears the synchronization flag bit corresponding to the requesting processor core. During the synchronization operation, when a synchronization revocation request is received, the method checks whether the synchronization flag bit corresponding to the requesting processor core is 1. If the synchronization flag bit corresponding to the requesting processor core is detected as 1, the synchronization flag bit corresponding to the requesting processor core is revoked. This supports concurrent synchronization operations and corresponding synchronization revocation operations within the array. When an incomplete synchronization operation is detected in a processor core, a synchronization revocation request can be sent to the manager processor core to revoke the incomplete synchronization operation, facilitating a job retention and recovery process. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of a multi-type distributed management method for payment revocation in an embodiment of the present invention;

[0034] Figure 2 This is a structural diagram of a multi-type distributed management device for payment revocation in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the electronic device structure in an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Figure 1 This is a flowchart illustrating a multi-type distributed management method for payment revocation provided in an embodiment of the present invention, as shown below. Figure 1 As shown, this embodiment of the invention provides a multi-type distributed management method for payment revocation, including:

[0038] Step S101: Obtain the processor cores participating in the synchronization operation, and determine the manager processor core and the participant processor cores among the processor cores. The manager processor core is the processor core with the first number among the processor cores, and the participant processor cores are the other processor cores among the processor cores besides the manager processor core.

[0039] Specifically, the processor cores in the computer that can participate in the synchronization operation are determined. The manager processor core is the processor core with the first or smallest number among those participating in the synchronization, and its number is usually set to one. The remaining processor cores are the participant processor cores.

[0040] Step S102: Obtain the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation, and set the corresponding synchronization flag bit in the manager processor core according to the synchronization bit.

[0041] Specifically, the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation is obtained, and a corresponding synchronization flag bit is set in the manager processor core according to the synchronization bit. Specifically, the synchronization bit can be obtained by the participant processor core sending a synchronization request to the manager processor core when synchronization is detected. The manager processor core has a synchronization flag bit corresponding to each processor core, which is used to register the processor core that has reached the synchronization point.

[0042] Step S103: When a synchronization operation request is received, obtain all request processor cores corresponding to the synchronization operation request, mark the synchronization flag bit in the manager processor core as 1 according to the request processor core, and clear the synchronization flag bit corresponding to the request processor core when the completion signal of the synchronization operation request is received.

[0043] Specifically, when the computer receives a synchronization operation request from a certain processor core, it obtains all the requesting processor cores corresponding to the synchronization operation request, and marks the synchronization flag bit as 1 according to the position of the synchronization flag bit of all requesting processor cores in the manager processor core. When it receives the completion information of the synchronization operation request, that is, when the synchronization flag bit of all requesting processor cores in the manager processor core is 1, the computer returns a synchronization completion signal to all participating processor cores, including the manager processor core. At the same time, it clears the corresponding synchronization flag bit in the manager processor core, that is, changes the flag 1 of the synchronization flag bit corresponding to the requesting processor core to the flag 0.

[0044] In addition, when multiple synchronization operation requests are received, the range of request processor cores corresponding to each synchronization operation request is obtained. Then, the overlapping processor cores in the range of request processor cores are determined according to the range of request processor cores. When performing synchronization operations for multiple synchronization operation requests, the corresponding synchronization flag bit in the overlapping processor core can be marked as 1. This enables the overlapping processor core to always be in a state of completing synchronization processing when processing multiple synchronization operation requests.

[0045] Step S104: During the synchronization operation, when a synchronization cancellation request is received, it is detected whether the synchronization flag bit corresponding to the request processor core is 1, and when the synchronization flag bit corresponding to the request processor core is detected to be 1, the synchronization flag bit corresponding to the request processor core is cancelled.

[0046] Specifically, during the synchronization operation, if a synchronization cancellation request is received, it checks whether the synchronization flag bit corresponding to the requesting processor core in the manager processor core is 1, and it can also check whether the information sent by the computer is invalid. When the synchronization flag bit is 1 and the signal is also invalid, the manager processor core generates a synchronization cancellation completion signal to the processor core, sends it to the participant processor core, and cancels and invalidates the synchronization flag bit corresponding to the processor core, that is, deletes the synchronization flag bit corresponding to the requesting processor core in the manager processor core.

[0047] This invention provides a multi-type distributed management method for payment revocation. The method involves acquiring the processor cores participating in the synchronization operation and identifying the manager processor core and participant processor cores. The manager processor core is the processor core with the highest number among the processor cores, and the participant processor cores are the other processor cores besides the manager processor core. The method acquires the synchronization bit of each participant processor core when it reaches a synchronization point during the synchronization operation and sets a corresponding synchronization flag bit in the manager processor core based on the synchronization bit. When a synchronization operation request is received, the method acquires all requesting processor cores corresponding to the synchronization operation request and marks the synchronization flag bit in the manager processor core as 1 based on the requesting processor cores. Upon receiving a completion signal for the synchronization operation request, the method clears the synchronization flag bit corresponding to the requesting processor core. During the synchronization operation, when a synchronization revocation request is received, the method checks whether the synchronization flag bit corresponding to the requesting processor core is 1. If the synchronization flag bit corresponding to the requesting processor core is detected as 1, the synchronization flag bit corresponding to the requesting processor core is revoked. This method supports concurrent synchronization operations and corresponding synchronization revocation operations within the array. When an incomplete synchronization operation is detected in a processor core, a synchronization revocation request can be sent to the manager processor core to revoke the incomplete synchronization operation, facilitating a job retention and recovery process.

[0048] Figure 2A multi-type distributed management device for payment revocation provided in an embodiment of the present invention includes: a first acquisition module S201, a second acquisition module S202, a clearing module S203, and a revocation module S204, wherein:

[0049] The first acquisition module S201 is used to acquire the processor cores participating in the synchronization operation, and to determine the manager processor core and the participant processor cores among the processor cores. The manager processor core is the processor core with the first number among the processor cores, and the participant processor cores are the other processor cores among the processor cores besides the manager processor core.

[0050] The second acquisition module S202 is used to acquire the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation, and set a corresponding synchronization flag bit in the manager processor core according to the synchronization bit.

[0051] The clearing module S203 is used to obtain all request processor cores corresponding to the synchronization operation request when a synchronization operation request is received, mark the synchronization flag bit in the manager processor core as 1 according to the request processor core, and clear the synchronization flag bit corresponding to the request processor core when a completion signal of the synchronization operation request is received.

[0052] The cancellation module S204 is used to detect whether the synchronization flag bit corresponding to the request processor core is 1 when a synchronization cancellation request is received during the synchronization operation, and cancel the synchronization flag bit corresponding to the request processor core when the synchronization flag bit corresponding to the request processor core is detected to be 1.

[0053] In one embodiment, the apparatus may further include:

[0054] The third acquisition module is used to acquire the range of request processor cores corresponding to each synchronization operation request when multiple synchronization operation requests are received, and to acquire overlapping processor cores in the range of request processor cores.

[0055] The marking module is used to mark the corresponding synchronization flag bit in the overlapping processor core as 1 when performing the synchronization operation of the multiple synchronization operation requests.

[0056] In one embodiment, the apparatus may further include:

[0057] The sending module is used by the manager processor core to generate a synchronization cancellation completion signal corresponding to the request processor core and send it to the participant processor core.

[0058] Specific limitations regarding a multi-type distributed management device for payment reversal can be found in the above-described limitations of a multi-type distributed management method for payment reversal, and will not be repeated here. Each module in the aforementioned multi-type distributed management device for payment reversal can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0059] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3 As shown, the electronic device may include: a processor 301, a memory 302, a communication interface 303, and a communication bus 304, wherein the processor 301, the memory 302, and the communication interface 303 communicate with each other through the communication bus 304. Processor 301 can call logic instructions in memory 302 to execute the following methods: obtain the processor cores participating in the synchronization operation, and determine the manager processor core and participating processor cores among the processor cores. The manager processor core is the processor core with the highest number among the processor cores, and the participating processor cores are the other processor cores among the processor cores besides the manager processor core; obtain the synchronization bit of the participating processor core when it reaches the synchronization point in the synchronization operation, and set the corresponding synchronization flag bit in the manager processor core according to the synchronization bit; when a synchronization operation request is received, obtain all requesting processor cores corresponding to the synchronization operation request, and mark the synchronization flag bit in the manager processor core as 1 according to the requesting processor cores, and clear the synchronization flag bit corresponding to the requesting processor core when a completion signal of the synchronization operation request is received; during the synchronization operation, when a synchronization cancellation request is received, check whether the synchronization flag bit corresponding to the requesting processor core is 1, and cancel the synchronization flag bit corresponding to the requesting processor core when the synchronization flag bit corresponding to the requesting processor core is detected to be 1.

[0060] Furthermore, the logical instructions in the aforementioned memory 302 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0061] On the other hand, embodiments of the present invention also provide a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the transmission methods provided in the above embodiments. For example, it includes: acquiring processor cores participating in the synchronization operation, and determining the manager processor core and participating processor cores among the processor cores, wherein the manager processor core is the processor core with the highest number among the processor cores, and the participating processor cores are other processor cores besides the manager processor core among the processor cores; acquiring the synchronization bit of the participating processor core when it reaches the synchronization point in the synchronization operation, and setting a corresponding synchronization flag bit in the manager processor core according to the synchronization bit; when a synchronization operation request is received, acquiring all requesting processor cores corresponding to the synchronization operation request, and marking the synchronization flag bit in the manager processor core as 1 according to the requesting processor cores, and clearing the synchronization flag bit corresponding to the requesting processor core when a completion signal of the synchronization operation request is received; during the synchronization operation, when a synchronization cancellation request is received, detecting whether the synchronization flag bit corresponding to the requesting processor core is 1, and canceling the synchronization flag bit corresponding to the requesting processor core when the synchronization flag bit corresponding to the requesting processor core is detected as 1.

[0062] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0063] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-type distributed management method for payment revocation, characterized in that, include: The processor cores participating in the synchronization operation are obtained, and the manager processor core and the participant processor cores among the processor cores are determined. The manager processor core is the processor core with the first number among the processor cores, and the participant processor cores are the other processor cores among the processor cores besides the manager processor core. Obtain the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation, and set the corresponding synchronization flag bit in the manager processor core according to the synchronization bit; When a synchronization operation request is received, all request processor cores corresponding to the synchronization operation request are obtained, and the synchronization flag bit in the manager processor core is marked as 1 according to the request processor core. When the completion signal of the synchronization operation request is received, the synchronization flag bit corresponding to the request processor core is cleared. During the synchronization operation, when a synchronization cancellation request is received, it is detected whether the synchronization flag bit corresponding to the request processor core is 1, and when the synchronization flag bit corresponding to the request processor core is detected to be 1, the synchronization flag bit corresponding to the request processor core is cancelled. The manager processor core generates a synchronization cancellation completion signal corresponding to the request processor core and sends it to the participant processor core; The step of revoking the synchronization flag bit corresponding to the request processor core includes: Delete the synchronization flag bit in the manager processor core that corresponds to the request processor core.

2. The multi-type distributed management method for payment revocation according to claim 1, characterized in that, The method further includes: When multiple synchronization operation requests are received, the range of request processor cores corresponding to each synchronization operation request is obtained, and the overlapping processor cores in the range of request processor cores are obtained. When performing the synchronization operation of the multiple synchronization operation requests, the corresponding synchronization flag bit in the overlapping processor core is marked as 1.

3. The multi-type distributed management method for payment revocation according to claim 1, characterized in that, Clearing the synchronization flag bit corresponding to the request processor core includes: Change the synchronization flag bit corresponding to the request processor core from flag 1 to flag 0.

4. A multi-type distributed management device for payment revocation, characterized in that, The device includes: The first acquisition module is used to acquire the processor cores participating in the synchronization operation, and to determine the manager processor core and the participant processor cores among the processor cores. The manager processor core is the processor core with the first number among the processor cores, and the participant processor cores are the other processor cores among the processor cores besides the manager processor core. The second acquisition module is used to acquire the synchronization bit of the participant processor core when it reaches the synchronization point in the synchronization operation, and set the corresponding synchronization flag bit in the manager processor core according to the synchronization bit. The clearing module is used to obtain all request processor cores corresponding to the synchronization operation request when a synchronization operation request is received, mark the synchronization flag bit in the manager processor core as 1 according to the request processor core, and clear the synchronization flag bit corresponding to the request processor core when a completion signal of the synchronization operation request is received. The cancellation module is used to, when a synchronization cancellation request is received during the synchronization operation, detect whether the synchronization flag bit corresponding to the request processor core is 1, and cancel the synchronization flag bit corresponding to the request processor core when the synchronization flag bit corresponding to the request processor core is detected to be 1. The sending module is used by the manager processor core to generate a synchronization cancellation completion signal corresponding to the request processor core and send it to the participant processor core; The step of revoking the synchronization flag bit corresponding to the request processor core includes: Delete the synchronization flag bit in the manager processor core that corresponds to the request processor core.

5. The multi-type distributed management device for payment revocation according to claim 4, characterized in that, The device further includes: The third acquisition module is used to acquire the range of request processor cores corresponding to each synchronization operation request when multiple synchronization operation requests are received, and to acquire overlapping processor cores in the range of request processor cores. The marking module is used to mark the corresponding synchronization flag bit in the overlapping processor core as 1 when performing the synchronization operation of the multiple synchronization operation requests.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the multi-type distributed management method for payment revocation as described in any one of claims 1 to 3.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the multi-type distributed management method for payment revocation as described in any one of claims 1 to 3.

Images