Memory access tracking for the host-resident translation layer

By using counters in the memory subsystem to track the number of read operations and suggesting activation or deactivation sub-region to the host system according to the threshold criteria, the problems of low random read performance and increased data services in the prior art are solved, and more efficient translation layer mapping table management and service quality improvement are achieved.

CN114077552BActive Publication Date: 2025-03-18MICRON TECHNOLOGY INC
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Patent Information

Application Number
CN202110961121.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-08-20
Filing Date
2021-08-20
Publication Date
2025-03-18
Estimated Expiration
2041-08-20

AI Technical Summary

Technical Problem

When the existing memory subsystem maintains the translation layer mapping table in the host resident translation layer, the random read performance is low, and the data service and waiting time are increased, and the service quality is reduced.

Method used

By maintaining multiple counters in the memory subsystem, the number of read operations performed on the zones and sub-regions of the logical address space of the memory device is tracked and periodically decremented counters in response to recent events on the memory device. Determine whether the cacheable or eviction threshold criteria are met based on the counter value, thereby suggesting to the host system to activate or deactivate the corresponding sub-region.

Benefits of technology

The effectiveness of the translation layer mapping information of the memory subsystem in the host resident translation layer is improved, data services and waiting time are reduced, and service quality of the host system is improved.

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Abstract

The present application relates to memory access tracking for a host resident translation layer. A processing device in a memory system receives a read command including an indication of a sub-region of a logical address space of the memory device from a host system. The processing device increments a counter associated with a region of the logical address space, the region including a plurality of sub-regions including the sub-region, the counter tracking the number of read operations performed on the plurality of sub-regions of the region, wherein the counter is periodically decremented in response to the occurrence of a recent event on the memory device. The processing device further determines whether the value of the counter satisfies a cacheability threshold criterion, and in response to the value of the counter satisfying the cacheability threshold criterion, sends a recommendation to activate the sub-region to the host system.
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