Organic light emitting diode display

Abstract

An organic light emitting diode display is disclosed. In one aspect, a semiconductor layer is on a substrate and the semiconductor layer is curved. A gate metal line is on the semiconductor layer, an insulating layer covers the semiconductor layer and the gate metal line and has a plurality of contact holes connected to the semiconductor layer. A data metal line is on the insulating layer and electrically connected to the semiconductor layer via a selected one of the contact holes. An OLED is electrically connected to the gate metal line and the data metal line, the semiconductor layer includes a narrow semiconductor layer having a first width and an expanded semiconductor layer formed adjacent to the selected contact hole and having a second width greater than the first width.

Description

[0001] This application is a divisional application of patent application No. 201610290634.4, filed on May 4, 2016, entitled "Organic Light Emitting Diode Display". Technical Field

[0002] The technology described generally relates to organic light-emitting diode (OLED) displays. Background Technology

[0003] Organic light-emitting diodes (OLEDs) consist of two electrodes and an inserted organic light-emitting layer. Electrons injected from the cathode electrode and holes injected from the anode electrode combine with each other in the organic light-emitting layer to form excitons. Light is emitted as the excitons release energy.

[0004] OLED displays consist of a matrix of pixels, each pixel including multiple thin-film transistors and capacitors for driving the OLED. Transistors typically include switching transistors and driving transistors.

[0005] As the demand for higher resolution increases, the shrinking pixel size reduces process margins. This makes it easier for defects to arise due to changes in wiring width, via size, or orientation errors. Specifically, as resolution increases, actual wiring may have a smaller width than the predetermined and designed wiring in the product, and the actual vias formed in the product may be larger than the predetermined and designed vias, or interlayer orientation errors may easily increase.

[0006] When the etchant used to etch data metal lines penetrates a semiconductor component exposed by misaligned contact holes, the semiconductor component may become open. Consequently, uneven illumination between adjacent pixels occurs because pixels in the open semiconductor component do not emit light while pixels in the closed semiconductor component do.

[0007] The information disclosed in this background section is intended only to enhance the understanding of the background of this disclosure, and therefore may contain information that does not constitute prior art known to a person skilled in the art in this country. Summary of the Invention

[0008] One aspect of the invention relates to an OLED display that can prevent the breakage of semiconductor components in a high-resolution structure.

[0009] On the other hand, there is an organic light-emitting diode (OLED) display, the OLED display comprising: a substrate; a semiconductor layer located on the substrate, wherein the semiconductor layer is non-linear; a gate metal line located on the semiconductor layer; an insulating layer covering the semiconductor layer and the gate metal line and having a plurality of contact holes connected to the semiconductor layer; a data metal line located on the insulating layer and electrically connected to the semiconductor layer via one of the contact holes; and an OLED electrically connected to the gate metal line and the data metal line, wherein the semiconductor layer includes a narrow semiconductor portion having a first width and an expanded semiconductor portion adjacent to the selected contact hole and having a second width greater than the first width.

[0010] In the aforementioned OLED display, the expanded semiconductor section surrounds the selected contact holes.

[0011] In the aforementioned OLED display, the expanded semiconductor portion includes a contact semiconductor region superimposed with the selected contact hole in the depth dimension of the OLED display and a non-contact semiconductor region not superimposed with the selected contact hole in the depth dimension of the OLED display, wherein the edge of the expanded semiconductor portion is separated from the edge of the selected contact hole in the non-contact semiconductor region.

[0012] The aforementioned OLED display further includes: scan lines located on a substrate and configured to transmit scan signals; data lines and drive voltage lines intersecting the scan lines and configured to transmit data voltage and drive voltage respectively; a switching transistor electrically connected to the scan lines and the data lines; a drive transistor electrically connected to the switching transistor and including a portion of a semiconductor layer as a drive channel, a drive gate electrode superimposed on the drive channel in the depth dimension of the OLED display, and a drive source electrode and a drive drain electrode located at the ends of the drive channel; a compensation transistor including another portion of a semiconductor layer as a compensation channel, a compensation gate electrode superimposed on the compensation channel in the depth dimension of the OLED display, and a compensation source electrode and a compensation drain electrode located at opposite ends of the compensation channel, wherein the compensation source electrode is electrically connected to the drive drain electrode; and a drive connector configured to electrically connect the compensation drain electrode to the drive gate electrode, wherein the gate metal lines include scan lines, and wherein the data metal lines include drive connectors.

[0013] The aforementioned OLED display further includes: a previous scan line, substantially parallel to the scan line and configured to transmit a previous scan signal; an initialization voltage line, configured to transmit an initialization voltage configured to initialize a driving transistor; and an initialization transistor, configured to be turned on based on the previous scan signal and including an initialization channel, an initialization gate electrode, an initialization source electrode, and an initialization drain electrode, wherein the expanded semiconductor portion includes a first expanded semiconductor portion configured to electrically connect a compensation drain electrode to the initialization drain electrode.

[0014] In the aforementioned OLED display, the selected contact holes include: compensation contact holes located where the drive connector and the first expanded semiconductor portion overlap each other in the depth dimension of the OLED display.

[0015] In the aforementioned OLED display, the first expanded semiconductor portion includes a first contact semiconductor region superimposed with the compensation contact hole in the depth dimension of the OLED display and a first non-contact semiconductor region not superimposed with the compensation contact hole in the depth dimension of the OLED display, wherein the edge of the first expanded semiconductor portion and the edge of the compensation contact hole are separated from each other in the first non-contact semiconductor region.

[0016] In the aforementioned OLED display, the first non-contact semiconductor region is located on the shortest path that passes in front of the compensation contact hole, wherein the shortest path extends from the vertical portion of the narrow semiconductor portion to the horizontal portion of the narrow semiconductor portion.

[0017] In the aforementioned OLED display, the first non-contact semiconductor region is located on a detour around the compensating contact hole.

[0018] In the aforementioned OLED display, the data metal line also includes a data line, and the expanded semiconductor section further includes a second expanded semiconductor section superimposed on the data line.

[0019] In the aforementioned OLED display, the contact hole also includes a switch contact hole located where the data line and the second expanded semiconductor portion overlap each other in the depth dimension of the OLED display.

[0020] In the aforementioned OLED display, the insulating layer includes: a first gate insulating layer covering the semiconductor layer; a second gate insulating layer covering the scan lines; and an interlayer insulating layer covering the second gate insulating layer, wherein the compensation contact hole and the switch contact hole penetrate the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0021] In the aforementioned OLED display, the OLED includes: a pixel electrode electrically connected to a driving transistor; an organic emitting layer located on the pixel electrode; and a common electrode located on the organic emitting layer.

[0022] On the other hand, there is an organic light-emitting diode (OLED) display, the OLED display comprising: a substrate; a semiconductor layer located on the substrate, wherein the semiconductor layer is non-linear; a gate metal line located on the semiconductor layer; an insulating layer covering the semiconductor layer and the gate metal line and having a plurality of contact holes connected to the semiconductor layer; a data metal line located on the insulating layer and electrically connected to the semiconductor layer via one of the contact holes; and an OLED electrically connected to the gate metal line and the data metal line, wherein the data metal line comprises a normal data metal layer having a first width and an expanded data metal portion adjacent to the selected contact hole and having a second width greater than the first width.

[0023] In the aforementioned OLED display, the expanded data metal portion surrounds the selected contact hole.

[0024] In the aforementioned OLED display, the semiconductor layer includes a bent semiconductor portion adjacent to a selected contact hole and a semiconductor strip portion having a generally linear shape, wherein the bent semiconductor portion and the expanded data metal portion are stacked in the depth dimension of the OLED display.

[0025] In the aforementioned OLED display, the extended data metal portion includes a contact data region superimposed on the depth dimension of the OLED display with the selected contact hole and a non-contact data region not superimposed on the depth dimension of the OLED display with the selected contact hole, wherein the edge of the extended data metal portion and the edge of the selected contact hole are separated from each other in the non-contact data region.

[0026] The aforementioned OLED display further includes: scan lines located on a substrate and configured to transmit scan signals; data lines and drive voltage lines intersecting the scan lines and configured to transmit data voltage and drive voltage respectively; a switching transistor electrically connected to the scan lines and the data lines; a drive transistor electrically connected to the switching transistor and including a portion of a semiconductor layer as a drive channel, a drive gate electrode superimposed on the drive channel in the depth dimension of the OLED display, and a drive source electrode and a drive drain electrode located at the end of the drive channel; a compensation transistor including another portion of a semiconductor layer as a compensation channel, a compensation gate electrode superimposed on the compensation channel in the depth dimension of the OLED display, and a compensation source electrode and a compensation drain electrode located at the end of the compensation channel, wherein the compensation source electrode is electrically connected to the drive drain electrode; and a drive connector configured to electrically connect the compensation drain electrode to the drive gate electrode, wherein the gate metal lines include scan lines, and wherein the data metal lines include drive connectors.

[0027] In the aforementioned OLED display, the contact hole includes a compensation contact hole located where the drive connector and the first expanded semiconductor portion overlap each other in the depth dimension of the OLED display.

[0028] In the aforementioned OLED display, the driving connector includes: a driving connection portion having a first width; and a driving expansion portion adjacent to the compensation contact hole and having a second width greater than the first width.

[0029] In the aforementioned OLED display, the driving expansion portion includes a contact data region superimposed on the depth dimension of the OLED display with the compensation contact hole and a non-contact data region not superimposed on the depth dimension of the OLED display with the compensation contact hole, wherein the edge of the driving expansion portion and the edge of the compensation contact hole are separated from each other in the non-contact data region.

[0030] In the aforementioned OLED display, the insulating layer includes: a first gate insulating layer covering the semiconductor layer; a second gate insulating layer covering the scan lines; and an interlayer insulating layer covering the second gate insulating layer, wherein the compensation contact hole penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0031] According to at least one of the disclosed embodiments, by forming an expanded semiconductor portion having a width larger than that of the narrow semiconductor portion at a location corresponding to the contact hole in the semiconductor layer, a sufficient current flow path can be obtained in the expanded semiconductor portion. Therefore, openings in the expanded semiconductor portion caused by the penetration of etchant used for data metal lines through the contact hole due to interlayer alignment errors can be prevented.

[0032] Therefore, uneven illumination between neighboring pixels can be prevented in high-resolution structures. Attached Figure Description

[0033] Figure 1 This is an equivalent circuit diagram of the pixels of an OLED display according to an exemplary embodiment.

[0034] Figure 2 This is a timing diagram of signals applied to pixels of an OLED display according to an exemplary embodiment.

[0035] Figure 3 This is a schematic layout diagram of a plurality of pixels of an OLED display according to exemplary embodiments of the present disclosure.

[0036] Figure 4 It is a schematic layout diagram of transistors and capacitors forming red, green and blue pixels of an OLED display according to an exemplary embodiment.

[0037] Figure 5 yes Figure 4 A detailed layout diagram of one pixel.

[0038] Figure 6 yes Figure 4 The enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 in the diagram.

[0039] Figure 7 When interlayer orientation error causes the data metal line to shift to the right side Figure 6 The enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 in the diagram.

[0040] Figure 8 When interlayer orientation error causes the data metal line to shift to the left... Figure 6 The enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 in the diagram.

[0041] Figure 9 It is intercepted along line IX-IX. Figure 5 A cross-sectional view of an OLED display.

[0042] Figure 10 It is intercepted along lines XX and X'-X'. Figure 5 A cross-sectional view of an OLED display.

[0043] Figure 11 It is intercepted along line XI-XI. Figure 7 A cross-sectional view of an OLED display.

[0044] Figure 12 This is an enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 of the red and green pixels of an OLED display according to another exemplary embodiment.

[0045] Figure 13 Is in Figure 12 An enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 when interlayer orientation error occurs.

[0046] Figure 14 This is an enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 of the red and green pixels of an OLED display according to another exemplary embodiment.

[0047] Figure 15 Is in Figure 14 An enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 when interlayer orientation error occurs. Detailed Implementation

[0048] In the following, the present disclosure will be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments of the disclosure. As those skilled in the art will recognize, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0049] The accompanying drawings and descriptions are to be considered illustrative in nature, not restrictive. Throughout the specification, the same reference numerals designate the same elements.

[0050] Furthermore, this disclosure is not limited to the dimensions and thicknesses of the constituent components shown in the accompanying drawings, which are arbitrarily given for better understanding and ease of description. The thicknesses of layers, films, panels, regions, etc., are exaggerated in the drawings for clarity. The thicknesses of some layers and regions are exaggerated in the drawings for better understanding and ease of description.

[0051] Furthermore, unless explicitly stated otherwise, the word "comprising" and its variations such as "including" or "comprising..." will be understood to mean including the stated element but not excluding any other elements. Additionally, throughout this specification, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Throughout this specification, it will be understood that the term "on" and similar terms are used generally and not necessarily in relation to a gravity reference.

[0052] Furthermore, in the instruction manual, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a sectional view" means when viewing a cross-section taken by vertically cutting the portion of the object from the side.

[0053] In the accompanying drawings, an active-matrix (AM) organic light-emitting diode (OLED) display is shown as a 7Tr-2Cap structure having seven transistors and two capacitors for each pixel, but this disclosure is not limited thereto. Therefore, in an OLED display, each pixel can have multiple transistors and at least one capacitor, and can be formed with various structures by further forming additional wiring or omitting existing wiring. In this case, a pixel is the smallest unit for displaying an image, and the OLED display displays an image through multiple pixels. In this disclosure, the term "substantially" includes completely, almost completely, or, in some applications, to any degree that would be apparent to those skilled in the art. The term "connection" can include electrical connections.

[0054] An exemplary embodiment of an OLED display according to the present disclosure will now be described in detail with reference to the accompanying drawings.

[0055] Figure 1 This is an equivalent circuit diagram of a pixel of an OLED display according to an exemplary embodiment of the present disclosure.

[0056] like Figure 1 As shown, the OLED display includes multiple signal lines 151, 152, 153, 158, 171, 172 and 192, and multiple pixels PX arranged in a matrix and connected to the multiple signal lines.

[0057] A pixel PX includes multiple transistors T1, T2, T3, T4, T5, T6 and T7 connected to multiple signal lines 151, 152, 153, 158, 171, 172 and 192, a storage capacitor Cst and an organic light-emitting diode OLED.

[0058] Transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, a light-emitting control transistor T6, and a bypass transistor T7.

[0059] Signal lines 151, 152, 153, 158, 171, 172, and 192 include a scan line 151 for transmitting the scan signal Sn, a previous scan line 152 for transmitting the previous scan signal Sn-1 to the initialization transistor T4, a light emission control line 153 for transmitting the light emission control signal EM to the operation control transistor T5 and the light emission control transistor T6, a bypass control line 158 for transmitting the bypass signal BP to the bypass transistor T7, a data line 171 for crossing the scan line 151 and transmitting the data signal Dm, a drive voltage line 172 for transmitting the drive voltage ELVDD and being set to be substantially parallel to the data line 171, and an initialization voltage line 192 for transmitting the initialization voltage Vint that initializes the drive transistor T1.

[0060] The gate electrode G1 of the driving transistor T1 is connected to one end Cst1 of the storage capacitor Cst. The source electrode S1 of the driving transistor T1 is connected to the driving voltage line 172 via the operation control transistor T5. The drain electrode D1 of the driving transistor T1 is electrically connected to the anode of the OLED via the light-emitting control transistor T6. The driving transistor T1 receives the data signal Dm according to the switching operation of the switching transistor T2 to supply the driving current I to the OLED. d .

[0061] The gate electrode G2 of switching transistor T2 is connected to scan line 151, the source electrode S2 of switching transistor T2 is connected to data line 171, and the drain electrode D2 of switching transistor T2 is connected to the source electrode S1 of driving transistor T1 and is connected to driving voltage line 172 via operation control transistor T5. Switching transistor T2 is turned on according to the scan signal Sn received through scan line 151 to perform a switching operation that transmits the data signal Dm transmitted to data line 171 to the source electrode of driving transistor T1.

[0062] The gate electrode G3 of the compensation transistor T3 is directly connected to the scan line 151. The source electrode S3 of the compensation transistor T3 is connected to the drain electrode D1 of the driving transistor T1 and is connected to the anode of the OLED via the light-emitting control transistor T6. The drain electrode D3 of the compensation transistor T3 is also connected to one end Cst1 of the storage capacitor Cst, the drain electrode D4 of the initialization transistor T4, and the gate electrode G1 of the driving transistor T1. The compensation transistor T3 is turned on according to the scan signal Sn received through the scan line 151 to connect the gate electrode G1 and the drain electrode D1 of the driving transistor T1, thus diode-connecting the driving transistor T1.

[0063] The gate electrode G4 of the initialization transistor T4 is connected to the previous scan line 152, the source electrode S4 of the initialization transistor T4 is connected to the initialization voltage line 192, and the drain electrode D4 of the initialization transistor T4 is simultaneously connected to one end Cst1 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 through the drain electrode D3 of the compensation transistor T3. The initialization transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line 152 to deliver the initialization voltage Vint to the gate electrode G1 of the driving transistor T1, and then performs an initialization operation to initialize the voltage of the gate electrode G1 of the driving transistor T1.

[0064] The gate electrode G5 of the operation control transistor T5 is connected to the light emission control line 153, the source electrode S5 of the operation control transistor T5 is connected to the drive voltage line 172, and the drain electrode D5 of the operation control transistor T5 is connected to the source electrode S1 of the drive transistor T1 and the drain electrode D2 of the switch transistor T2.

[0065] The gate electrode G6 of the light-emitting control transistor T6 is connected to the light-emitting control line 153. The source electrode S6 of the first light-emitting control transistor T6 is connected to the drain electrode D1 of the driving transistor T1 and the source electrode S3 of the compensation transistor T3. The drain electrode D6 of the light-emitting control transistor T6 is electrically connected to the anode of the OLED. The operation control transistor T5 and the first light-emitting control transistor T6 are turned on substantially simultaneously (or synchronously) according to the light-emitting control signal EM transmitted to the light-emitting control line 153, so that the driving voltage ELVDD is compensated through the diode-connected driving transistor T1 and transmitted to the OLED.

[0066] The gate electrode G7 of the bypass transistor T7 is connected to the bypass control line 158, and the source electrode S7 of the bypass transistor T7 is simultaneously connected to the drain electrode D6 of the light-emitting control transistor T6 and the anode of the OLED. The drain electrode D7 of the bypass transistor T7 is also connected to the initialization voltage line 192 and the source electrode S4 of the initialization transistor T4. In this case, the previous scan line 152 is connected to the scan line 151 that transmits the scan signal Sn in the previous pixel (not shown), and the bypass control line 158 corresponds to the previous scan line 152 such that the bypass signal BP is the same as the previous scan signal Sn-1.

[0067] The other end of the storage capacitor Cst, Cst2, is connected to the driving voltage line 172, and the cathode of the OLED is connected to the common voltage line 741 that transmits the common voltage ELVSS.

[0068] The exemplary embodiments of this disclosure describe a structure of 7 transistors and 1 capacitor including a bypass transistor T7; however, this disclosure is not limited thereto, and the number of transistors and the number of capacitors can be varied in various ways.

[0069] In the following text, reference will be made to Figure 2 The detailed operation of a pixel of an OLED display according to exemplary embodiments of the present disclosure is described in detail.

[0070] Figure 2 This is a timing diagram of signals applied to a pixel of an OLED display according to an exemplary embodiment of the present disclosure.

[0071] like Figure 2 As shown, firstly, during the initialization period, a previous scan signal Sn-1 with a low level is supplied through the previous scan line 152. Then, the initialization transistor T4 is turned on in response to the previous scan signal Sn-1 with a low level, and the initialization voltage Vint is connected to the gate electrode G1 of the driving transistor T1 through the initialization voltage line 192 via the initialization transistor T4. The driving transistor T1 is then initialized by the initialization voltage Vint.

[0072] Subsequently, during the data programming period, a scan signal Sn with a low level is supplied through scan line 151. Then, switching transistor T2 and compensation transistor T3 are turned on in response to the scan signal Sn with a low level. At this time, driving transistor T1 is diode-connected through the turned-on compensation transistor T3 and is forward-biased.

[0073] Then, the compensation voltage Dm+Vth (Vth is a negative value) obtained by subtracting the threshold voltage Vth of the driving transistor T1 from the data signal Dm supplied from the data line 171 is applied to the gate electrode G1 of the driving transistor T1. That is, the gate voltage Vg applied to the gate electrode G1 of the driving transistor T1 becomes the compensation voltage (Dm+Vth).

[0074] The driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to the two terminals of the storage capacitor Cst, and the charge corresponding to the voltage difference between the two terminals is stored in the storage capacitor Cst.

[0075] Next, during the light-emitting period, the light-emitting control signal EM supplied from the light-emitting control line 153 changes from a high level to a low level. Therefore, during the light-emitting period, the operating control transistor T5 and the light-emitting control transistor T6 are turned on by the low-level light-emitting control signal EM.

[0076] Therefore, the drive current I is generated based on the voltage difference between the gate voltage of the gate electrode G1 of the driving transistor T1 and the drive voltage ELVDD. d And drive current I d The OLED is supplied with light through the light-emitting control transistor T6. During the light-emitting period, the gate-source voltage Vgs of the driving transistor T1 is maintained at "(Dm+Vth)-ELVDD" through the storage capacitor Cst. Based on the current-voltage relationship of the driving transistor T1, the driving current I... d The square of the value obtained by subtracting the threshold voltage from the gate-source voltage is "(Dm-ELVDD)". 2 "Proportional. Therefore, the drive current I..." d It is deterministic regardless of the threshold voltage Vth of the driving transistor T1.

[0077] In this situation, bypass transistor T7 is turned on by the bypass signal BP transmitted from bypass control line 158. Therefore, the drive current I... d The bypass current I is partially discharged through the bypass transistor T7. bp .

[0078] When the minimum current of the driving transistor T1, which displays a black image, flows as the driving current, the black image cannot be displayed correctly if the OLED is also omitted. Therefore, the bypass transistor T7 of the OLED display according to an exemplary embodiment of this disclosure can use the portion of the minimum current of the driving transistor T1 flowing through other current paths beside the current path on the OLED side as a bypass current I. bpDispersion. Here, the minimum current of driving transistor T1 refers to the current under the condition that driving transistor T1 is turned off because the gate-source voltage Vgs of driving transistor T1 is smaller than the threshold voltage Vth. The minimum driving current (e.g., approximately 10 pA or less) under the condition that driving transistor T1 is turned off is delivered to the OLED to represent an image with black brightness. When the minimum driving current representing the black image flows, the bypass current I... bp The effect of bypass propagation is significant, but when a large drive current flows to represent an image such as a normal image or a white image, the effect on the bypass current I is small. bp The impact can be very small. Therefore, when the drive current flows to display a black image, the flow from the drive current I is reduced. d The bypass current I flowing out through bypass transistor T7 bp The luminous current I of the OLED oled It has a minimum current level that can accurately represent a black image. Therefore, by using a bypass transistor T7, a black luminance image is accurately achieved, thereby improving the contrast ratio. Figure 2 In this process, the bypass signal BP is the same as the previous scan signal Sn-1, but it is not limited to this.

[0079] Next, refer to Figure 3 Description of formation Figure 1 and Figure 2 The diagram shows the structure of multiple pixels in an OLED display.

[0080] Figure 3 This is a schematic layout diagram of a plurality of pixels of an OLED display according to exemplary embodiments of the present disclosure.

[0081] like Figure 3 As shown, multiple green pixels G corresponding to the second pixel are arranged at predetermined intervals in the first row 1N. Red pixels R corresponding to the first pixel and blue pixels B corresponding to the third pixel are alternately arranged in the second row 2N adjacent to the first row 1N. Multiple green pixels G are arranged at predetermined intervals in the adjacent third row 3N. Blue pixels B and red pixels R are alternately arranged in the fourth row 4N adjacent to the third row 3N. This arrangement of pixels is repeated until the Nth row. In this case, blue pixels B and red pixels R are set to be larger than green pixels G.

[0082] In this configuration, the green pixel G in the first row 1N is mismatched with the red pixel R and blue pixel B in the second row 2N. Therefore, the red pixel R and blue pixel B are alternately arranged in the first column 1M, the green pixel G is separated at predetermined intervals in the second column 2M adjacent to the first column 1M, the blue pixel B and red pixel R are alternately arranged in the third column 3M adjacent to the second column 2M, and the green pixel G is separated at predetermined intervals in the fourth column 4M adjacent to the third column 3M. This pixel arrangement is repeated until the Mth column.

[0083] The aforementioned pixel arrangement structure is called a pentile matrix. By using a rendering driver that shares adjacent pixels to represent colors, high resolution with a small number of pixels can be achieved.

[0084] Now, refer to Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The application description has Figure 3 The detailed structure of an OLED display with such pixel arrangement according to an exemplary embodiment of the present disclosure is shown in the figure.

[0085] Figure 4 This is a schematic layout diagram of transistors and capacitors forming red, green, and blue pixels of an OLED display according to an exemplary embodiment of the present disclosure. Figure 5 yes Figure 4 A detailed layout diagram of one pixel. Figure 6 yes Figure 4 The enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 in the diagram. Figure 7 When interlayer orientation error causes the data metal line to shift to the right side Figure 6 The enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 in the diagram. Figure 8 When interlayer orientation error causes the data metal line to shift to the left... Figure 6 The enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 in the diagram. Figure 9 It is intercepted along line IX-IX. Figure 5 A cross-sectional view of an OLED display. Figure 10 It is intercepted along lines XX and X'-X'. Figure 5 A cross-sectional view of an OLED display. Figure 11 It is intercepted along line XI-XI. Figure 7 A cross-sectional view of an OLED display.

[0086] In the following text, we will first refer to Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The detailed planar structure of the OLED display according to exemplary embodiments of the present disclosure is described in detail, and reference will be made to... Figure 9 , Figure 10 and Figure 11 Describe the detailed cross-sectional structure.

[0087] like Figure 4 and Figure 5 As shown, the OLED display according to an exemplary embodiment of the present disclosure includes gate metal lines (151, 152, 153, and 158), which include scan line 151, previous scan line 152, light emission control line 153, and bypass control line 158 disposed in the row direction, respectively applying a scan signal Sn, a previous scan signal Sn-1, a light emission control signal EM, and a bypass signal BP. In this exemplary embodiment, the bypass control line 158 is substantially the same as the previous scan line 152.

[0088] In addition, it includes a data line 171 and a drive voltage line 172 that intersect the scan line 151, the previous scan line 152, the light emission control line 153, and the bypass control line 158, and respectively apply the data signal Dm and the drive voltage ELVDD to the pixel PX. The initialization voltage Vint is transmitted from the initialization voltage line 192 to the compensation transistor T3 through the initialization transistor T4. The initialization voltage line 192 is provided with alternating straight portions 192a and tilted portions 192b. The straight portion 192a is set to be parallel to the scan line 121, and the tilted portion 192b extends at a predetermined angle relative to the straight portion 192a.

[0089] In addition, the pixel PX is equipped with a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, a light emission control transistor T6, a bypass transistor T7, a storage capacitor Cst, and an OLED. Figure 4 and Figure 5 The pixel PX shown can correspond to the red pixel R, green pixel G, and blue pixel B that form the pixel arrangement matrix structure.

[0090] The OLED includes a pixel electrode 191, an organic emitter layer 370, and a common electrode 270. In this case, the compensation transistor T3 and the initialization transistor T4 are composed of transistors with a dual-gate structure to cut off leakage current.

[0091] Each of the driving transistor T1, switching transistor T2, compensation transistor T3, initialization transistor T4, operation control transistor T5, light-emitting control transistor T6, and bypass transistor T7 has a channel disposed within a connected semiconductor component (or semiconductor layer) 130, which can be bent into various shapes. The semiconductor component 130 may be formed of polysilicon or oxide semiconductor. Oxide semiconductors may include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), and one of the following composite oxides thereof: indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (In-Zn-O), zinc-tin oxide (Zn-Sn-O), indium-gallium oxide (In-Ga-O), indium-tin oxide (In-Sn-O), indium-zirconium oxide (In-Zr-O), indium-zirconium-zinc oxide (In-Zr-Zn-O), indium-zirconium-tin oxide (In-Zr-Sn-O), indium-zirconium-gallium oxide (In-Zr-Ga-O), and indium-aluminum oxide (In-Al). Indium-zinc-aluminum oxide (In-Zn-Al-O), indium-tin-aluminum oxide (In-Sn-Al-O), indium-aluminum-gallium oxide (In-Al-Ga-O), indium-tantalum oxide (In-Ta-O), indium-tantalum-zinc oxide (In-Ta-Zn-O), indium-tantalum-tin oxide (In-Ta-Sn-O), indium-tantalum-gallium oxide (In-Ta-Ga-O), indium-germanium oxide (In-Ge-O), indium-germanium-zinc oxide (In-Ge-Zn-O), indium-germanium-tin oxide (In-Ge-Sn-O), indium-germanium-gallium oxide (In-Ge-Ga-O), titanium-indium-zinc oxide (Ti-In-Zn-O), and hafnium-indium-zinc oxide (Hf-In-Zn-O). When the semiconductor component 130 is formed of an oxide semiconductor material, a separate passivation layer can be added to protect the oxide semiconductor material from external environmental influences such as high temperatures.

[0092] Semiconductor component 130 includes: a channel doped with N-type or P-type impurities; a source-doped portion and a drain-doped portion disposed on corresponding sides of the channel and doped with impurities of the opposite type to those doped on the channel. In an exemplary embodiment, the source-doped portion corresponds to the source electrode, and the drain-doped portion corresponds to the drain electrode. The source electrode and drain electrode disposed in semiconductor component 130 can be formed by doping only the corresponding regions. Furthermore, in semiconductor component 130, the regions between the source electrodes and drain electrodes of different transistors are doped, thereby allowing the source electrodes and drain electrodes to be electrically connected to each other.

[0093] like Figure 5As shown, the channel 131 includes a driving channel 131a disposed in the driving transistor T1, a switching channel 131b disposed in the switching transistor T2, a compensation channel 131c disposed in the compensation transistor T3, an initialization channel 131d disposed in the initialization transistor T4, an operation control channel 131e disposed in the operation control transistor T5, a light emission control channel 131f disposed in the light emission control transistor T6, and a bypass channel 131g disposed in the bypass transistor T7.

[0094] The driving transistor T1 includes a driving channel 131a, a driving gate electrode 155a, a driving source electrode 136a, and a driving drain electrode 137a. The driving channel 131a can be curved and can have a meandering or sawtooth shape. Thus, by forming a curved driving channel 131a, the driving channel 131a can be configured to extend in a narrow space. Therefore, the driving range of the driving gate-source voltage Vgs between the driving gate electrode 155a and the driving source electrode 136a is increased due to the extended driving channel 131a. Because the driving range of the gate voltage is increased, the grayscale of the light emitted from the OLED can be finely controlled by changing the magnitude of the gate voltage. As a result, the resolution of the OLED display device can be improved, and the display quality can be enhanced. Various examples such as "inverse S", "S", "M", and "W" can be achieved by modifying the shape of the driving channel 131a in different ways.

[0095] The drive gate electrode 155a is stacked on top of the drive channel 131a. The drive source electrode 136a and the drive drain electrode 137a are disposed on corresponding sides of the drive channel 131a to close it. The drive gate electrode 155a is connected to the drive connection member (or drive connector) 174 through the contact hole 61. The drive gate electrode 155a corresponds to the gate metal line, and the drive connection member 174 corresponds to the data metal line.

[0096] The switching transistor T2 includes a switching channel 131b, a switching gate electrode 155b, a switching source electrode 136b, and a switching drain electrode 137b. The switching gate electrode 155b, as part of a portion extending downward from the scan line 151, is stacked on top of the switching channel 131b. The switching source electrode 136b and the switching drain electrode 137b are located adjacent to each other on corresponding sides of the switching channel 131b. The switching source electrode 136b is connected to the data line 171 via a switching contact hole 62.

[0097] The compensation transistor T3 includes a compensation channel 131c, a compensation gate electrode 155c, a compensation source electrode 136c, and a compensation drain electrode 137c. The compensation gate electrode 155c, as part of the scan line 151, is formed in two configurations to prevent leakage current and is stacked with the compensation channel 131c. The compensation source electrode 136c and the compensation drain electrode 137c are positioned adjacent to their respective sides of the compensation channel 131c. The compensation drain electrode 137c is connected to the drive connection member 174 via a contact hole 63.

[0098] The initialization transistor T4 includes an initialization channel 131d, an initialization gate electrode 155d, an initialization source electrode 136d, and an initialization drain electrode 137d. The initialization gate electrode 155d, as part of the previous scan line 152, is formed in pairs to prevent leakage current and is stacked with the initialization channel 131d. The initialization source electrode 136d and the initialization drain electrode 137d are positioned adjacent to their respective sides of the initialization channel 131d. The initialization source electrode 136d is connected to the initialization connection member 175 via a contact hole 64.

[0099] The operation control transistor T5 includes an operation control channel 131e, an operation control gate electrode 155e, an operation control source electrode 136e, and an operation control drain electrode 137e. The operation control gate electrode 155e, as part of the light-emitting control line 153, is stacked on top of the operation control channel 131e. The operation control source electrode 136e and the operation control drain electrode 137e are positioned adjacent to their respective sides of the operation control channel 131e. The operation control source electrode 136e is connected via a contact hole 65 to a portion extending from the drive voltage line 172.

[0100] The light-emitting control transistor T6 includes a light-emitting control channel 131f, a light-emitting control gate electrode 155f, a light-emitting control source electrode 136f, and a light-emitting control drain electrode 137f. The light-emitting control gate electrode 155f, as part of the light-emitting control line 153, is stacked with the light-emitting control channel 131f. The light-emitting control source electrode 136f and the light-emitting control drain electrode 137f are positioned adjacent to their respective sides of the light-emitting control channel 131f. The light-emitting control drain electrode 137f is connected to the pixel connection member 179 via a contact hole 66.

[0101] The bypass transistor T7 includes a bypass channel 131g, a bypass gate electrode 155g, a bypass source electrode 136g, and a bypass drain electrode 137g. The bypass gate electrode 155g, which is part of the bypass control line 158, is stacked on the bypass channel 131g, and the bypass source electrode 136g and the bypass drain electrode 137g are configured to be adjacent to the corresponding sides of the bypass channel 131g.

[0102] The bypass source electrode 136g is directly connected to the light-emitting control drain electrode 137f, and the bypass drain electrode 137g is directly connected to the initialization source electrode 136d.

[0103] One end of the driving channel 131a of the driving transistor T1 is connected to the switching drain electrode 137b and the operation control drain electrode 137e. The other end of the driving channel 131a is connected to the compensation source electrode 136c and the light emission control source electrode 136f.

[0104] like Figure 6 As shown, the semiconductor component 130 includes a narrow semiconductor portion (or narrow semiconductor layer) 31 having a first width d2 and an expanded semiconductor portion (or expanded semiconductor layer) 32 having a second width d1 that is larger than the first width d2. The narrow semiconductor portion 31 corresponds to the channel 131 and most of the source and drain electrodes.

[0105] The expansion semiconductor section 32 includes: a first expansion semiconductor section 32a, which connects the compensation drain electrode 137c and the initialization drain electrode 137d to each other; and a second expansion semiconductor section 32b, which is stacked with the data line 171.

[0106] The compensation contact hole 63 is located in the first expanded semiconductor section 32a on a plane, and the switch contact hole 62 is located in the second expanded semiconductor section 32b. The compensation contact hole 63 is disposed on a plane at the position where the first expanded semiconductor section 32a and the drive connection member 174 intersect each other, and the switch contact hole 62 is disposed on a plane at the position where the second expanded semiconductor section 32b and the data line 171 overlap each other.

[0107] The width d1 of the first expanded semiconductor portion 32a can be larger than the width d2 of the narrow semiconductor portion 31. Furthermore, the edge of the first expanded semiconductor portion 32a surrounds the edge of the compensation contact hole 63. That is, the first expanded semiconductor portion 32a includes a first contact semiconductor region P1 superimposed on the compensation contact hole 63 and a first non-contact semiconductor region Q1 not superimposed on the compensation contact hole 63. The edge of the first expanded semiconductor portion 32a and the edge of the compensation contact hole 63 are separated from each other in the first non-contact semiconductor region Q1. The first non-contact semiconductor region Q1 is located on the shortest path A that connects the compensation drain electrode 137c and the initialization drain electrode 137d to each other. The shortest path A passes in front of the compensation contact hole 63. Therefore, a sufficient current flow path can be obtained by providing the first non-contact semiconductor region Q1 in the first expanded semiconductor portion 32a.

[0108] The width d3 of the second expanded semiconductor portion 32b can be larger than the width d2 of the narrow semiconductor portion. That is, the second expanded semiconductor portion 32b includes a second contact semiconductor region P2 that overlaps with the switch contact hole 62 and a second non-contact semiconductor region Q2 that does not overlap with the switch contact hole 62. The edges of the second expanded semiconductor portion 32b and the edges of the switch contact hole 62 are separated from each other in the second non-contact semiconductor region Q2. Therefore, a sufficient current flow path can be obtained through the second non-contact semiconductor region Q2 provided in the second expanded semiconductor portion 32b.

[0109] Figure 7 This illustrates when interlayer orientation errors cause the data metal lines to shift... Figure 6 The right side of the diagram shows an enlarged layout of the switching transistor T2 and the compensation transistor T3.

[0110] like Figure 7 As shown, interlayer alignment errors can easily occur during the manufacturing process of high-resolution structures. When interlayer alignment errors occur, the drive connection member 174 and the data line 171 are shifted to the right by a predetermined interval t1 relative to their positions in the original design. Therefore, one end of the drive connection member 174 does not completely cover the compensation contact hole 63, leaving a portion of the compensation contact hole 63 exposed. Etching agent penetrates through the exposed compensation contact hole 63, damaging a portion of the first expanded semiconductor portion 32a. However, even if the first contact semiconductor region P1 of the first expanded semiconductor portion 32a is damaged, the first non-contact semiconductor region Q1 remains undamaged, thus obtaining a current movement path A between the compensation drain electrode 137c and the initialization drain electrode 137d. This current movement path corresponds to the shortest path A.

[0111] As described above, a first non-contact semiconductor region Q1, which passes in front of the compensation contact hole 63 and corresponds to the shortest path, is provided in the first expanded semiconductor section 32a located at the position corresponding to the compensation contact hole 63, thereby ensuring a sufficient current flow path in the first expanded semiconductor section 32a. Therefore, openings in the first expanded semiconductor section 32a caused by etchant penetration through the compensation contact hole 63 due to interlayer alignment errors can be prevented. Thus, uneven illumination between adjacent pixels can be prevented in a high-resolution structure.

[0112] Figure 8 This illustrates when interlayer orientation errors cause the data metal lines to shift... Figure 6 The left side of the diagram shows an enlarged layout of the switching transistor T2 and the compensation transistor T3.

[0113] like Figure 8As shown, when interlayer alignment errors occur during the manufacturing process of the high-resolution structure, the drive connection member 174 and the data line 171 are shifted to the left by a predetermined interval t2 relative to their positions in the original design. Therefore, the data line 171 does not completely cover the switch contact hole 62, leaving a portion of the switch contact hole 62 exposed. Etching agent penetrates through the exposed switch contact hole 62, damaging a portion of the second expanded semiconductor portion 32b. However, even if the second contact semiconductor region P2 of the second expanded semiconductor portion 32b is damaged by the etchant, the second non-contact semiconductor region Q2 remains undamaged, thus obtaining a current flow path B between the data line 171 and the switch source electrode 136b.

[0114] As described above, the width d3 of the second expanded semiconductor portion 32b, located at the position corresponding to the switch contact hole 62, is larger than the width d2 of the narrow semiconductor portion, thereby ensuring a sufficient current flow path within the second expanded semiconductor portion 32b. Therefore, openings in the second expanded semiconductor portion 32b caused by etchant penetration through the switch contact hole 62 due to interlayer alignment errors can be prevented. Consequently, in a high-resolution structure, uneven illumination between adjacent pixels can be prevented.

[0115] On the other hand, the capacitor Cst includes a first storage electrode 155a and a second storage electrode 156, and a second gate insulating layer 142 is disposed between the first storage electrode 155a and the second storage electrode 156. The first storage electrode 155a corresponds to the drive gate electrode 155a. Furthermore, the second storage electrode 156 is a portion extending from the storage line 157 and occupies a wider area than the drive gate electrode 155a, completely covering the drive gate electrode 155a.

[0116] Here, the second gate insulating layer 142 is a dielectric material, and the storage capacitance is determined by the charge in the storage capacitor Cst and the voltage between electrodes 155a and 156. In this way, the driving gate electrode 155a serves as the first storage electrode 155a, thereby ensuring space for the storage capacitor to be placed in the space narrowed due to the large area occupied by the driving channel 131a within the pixel.

[0117] The first storage electrode 155a, serving as the driving gate electrode 155a, is connected to one end of the driving connection member 174 via a driving contact hole 61. The storage opening 51 is an opening provided in the second storage electrode 156. Therefore, one end of the driving connection member 174 and the driving contact hole 61 of the driving gate electrode 155a are located inside the storage opening 51. The driving connection member 174 is disposed on the same layer as the data line 171 and is substantially parallel to the data line 171. Furthermore, the other end of the driving connection member 174 is connected to the compensation drain electrode 137c of the compensation transistor T3 and the initialization drain electrode 137d of the initialization transistor T4 via a compensation contact hole 63. Therefore, the driving connection member 174 connects the driving gate electrode 155a to the compensation drain electrode 137c of the compensation transistor T3 and the initialization drain electrode 137d of the initialization transistor T4.

[0118] The second storage electrode 156 is connected to the drive voltage line 172 through the contact hole 69.

[0119] Therefore, the storage capacitor Cst stores the storage capacitance corresponding to the difference between the driving voltage ELVDD transmitted to the second storage electrode 156 via the driving voltage line 172 and the gate voltage Vg of the driving gate electrode 155a.

[0120] Pixel connection member 179 is connected to pixel electrode 191 through contact hole 81. Additionally, initialization connection member 175 is connected to initialization voltage line 192 through contact hole 82.

[0121] In the following text, reference will be made to Figure 9 , Figure 10 and Figure 11 The cross-sectional structure of the OLED display device according to exemplary embodiments of the present disclosure is described in detail according to the stacking order.

[0122] In this case, since the stacked structure of the operation control transistor T5 is largely the same as that of the light-emitting control transistor T6, a detailed description of it will be omitted.

[0123] A buffer layer 120 may be disposed on an insulating substrate 110. The insulating substrate 110 may be formed of an insulating material such as glass, quartz, ceramic, or plastic. The buffer layer 120 blocks impurities from the insulating substrate 110 during the crystallization process used to form a polycrystalline semiconductor, thereby improving the properties of the polycrystalline semiconductor and reducing the stress acting on the insulating substrate 110.

[0124] Semiconductor component 130 is disposed on buffer layer 120. Semiconductor component 130 includes a channel 131 having a driving channel 131a, a switching channel 131b, a compensation channel 131c, an initialization channel 131d, an operation control channel 131e, a light emission control channel 131f, and a bypass channel 131g. In semiconductor component 130, driving source electrode 136a and driving drain electrode 137a are disposed on corresponding sides of driving channel 131a. Switching source electrode 136b and switching drain electrode 137b are disposed on corresponding sides of switching channel 131b. Compensation source electrode 136c and compensation drain electrode 137c are disposed on both sides of compensation channel 131c. Initialization source electrode 136d and initialization drain electrode 137d are disposed on both sides of initialization channel 131d. The operation control source electrode 136e and the operation control drain electrode 137e are disposed on both sides of the operation control channel 131e, and the light emission control source electrode 136f and the light emission control drain electrode 137f are disposed on both sides of the light emission control channel 131f. The bypass source electrode 136g and the bypass drain electrode 137g are disposed on the corresponding sides of the bypass channel 131g.

[0125] Semiconductor component 130 includes a narrow semiconductor portion 31 having a first width d2 and an expanded semiconductor portion 32 having a second width d1 larger than the first width d2. The narrow semiconductor portion 31 corresponds to the channel 131 and most of the source and drain electrodes. The expanded semiconductor portion 32 includes: a first expanded semiconductor portion 32a, connecting the compensation drain electrode 137c and the initialization drain electrode 137d; and a second expanded semiconductor portion 32b, stacked with the data line 171. The width d1 of the first expanded semiconductor portion 32a may be larger than the width d2 of the narrow semiconductor portion.

[0126] A first gate insulating layer 141 covering the semiconductor component 130 is disposed on the semiconductor component 130. A first gate metal line (151, 152, 153, 158 and 155a) including a switching gate electrode 155b, a scan line 151 having a compensation gate electrode 155c, a previous scan line 152 having an initialization gate electrode 155d, a light emission control line 153 having an operation control gate electrode 155e and a light emission control gate electrode 155f, a bypass control line 158 having a bypass gate electrode 155g, and a driving gate electrode (first storage electrode) 155a is disposed on the first gate insulating layer 141.

[0127] A second gate insulating layer 142 covering the first gate metal lines (151, 152, 153, 158, and 155a) and the first gate insulating layer 141 is disposed on the first gate metal lines (151, 152, 153, 158, and 155a) and the first gate insulating layer 141. The first gate insulating layer 141 and the second gate insulating layer 142 may be made of silicon nitride (SiN). x ) or silicon dioxide (SiO)x )form.

[0128] A second gate metal line (157 and 156) including a storage line 157 parallel to the scan line 151 and a storage electrode 156 as an extension of the storage line 157 is disposed on the second gate insulating layer 142.

[0129] The second storage electrode 156 is wider than the first storage electrode 155a, which is used as the driving gate electrode, such that the second storage electrode 156 completely covers the driving gate electrode 155a.

[0130] The gate metal lines (151, 152, 153, 158, and 155a) including the first gate metal lines (151, 152, 153, 158, and 155a) and the second gate metal lines (156 and 157) can be formed as a multilayer of metal layers stacked with any material selected from copper (Cu), copper alloys, aluminum (Al), aluminum alloys, molybdenum (Mo), and molybdenum alloys.

[0131] An interlayer insulating layer 160 is disposed on the second gate insulating layer 142 and the second gate metal lines (157 and 156). The interlayer insulating layer 160 may be made of silicon nitride (SiN). x ) or silicon dioxide (SiO) x )form.

[0132] The interlayer insulating layer 160 has contact holes 61, 62, 63, 64, 65, 66, and 69. Data metal lines (171, 172, 174, 175, and 179), including a data line 171, a drive voltage line 172, a drive connection member 174, an initialization connection member 175, and a pixel connection member 179, are disposed on the interlayer insulating layer 160. The data metal lines (171, 172, 174, 175, and 179) can be formed as a multilayer of stacked metal layers containing any material selected from titanium (Ti), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, molybdenum (Mo), and molybdenum alloys. For example, the data metal lines (171, 172, 174, 175, and 179) can be formed as a three-layer titanium / aluminum / titanium (Ti / Al / Ti), a three-layer molybdenum / aluminum / molybdenum (Mo / Al / Mo), or a three-layer molybdenum / copper / molybdenum (Mo / Cu / Mo).

[0133] Data line 171 is connected to switch source electrode 136b via switch contact holes 62 provided in the first gate insulating layer 141, second gate insulating layer 142, and interlayer insulating layer 160. One end of drive connection member 174 is connected to first storage electrode 155a via drive contact holes 61 provided in the second gate insulating layer 142 and interlayer insulating layer 160. The other end of drive connection member 174 is connected to compensation drain electrode 137c and initialization drain electrode 137d via compensation contact holes 63 provided in the first gate insulating layer 141, second gate insulating layer 142, and interlayer insulating layer 160.

[0134] An initialization connection member 175, substantially parallel to the data line 171, is connected to the initialization source electrode 136d via initialization contact holes 64 provided in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 160. Furthermore, a pixel connection member 179 is connected to the light emission control drain electrode 137f via light emission control contact holes 66 provided in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 160.

[0135] A passivation layer 180 covering the data metal lines (171, 172, 174, 175, and 179) and the interlayer insulating layer 160 is disposed on the data metal lines (171, 172, 174, 175, and 179) and the interlayer insulating layer 160. The passivation layer 180 covers the data metal lines (171, 172, 174, 175, and 179) to make them flat, so that the pixel electrode 191 can be disposed on the passivation layer 180 without steps. The passivation layer 180 may be formed of a stack of organic materials such as polyacrylate resin or polyimide resin, or a stack of organic and inorganic materials.

[0136] Pixel electrode 191 and initialization voltage line 192 are disposed on passivation layer 180. Pixel connection member 179 is connected to pixel electrode 191 through contact hole 81 disposed in passivation layer 180. Initialization connection member 175 is connected to initialization voltage line 192 through contact hole 82 disposed in passivation layer 180.

[0137] A pixel defining layer (PDL) 350, covering the passivation layer 180, the initialization voltage line 192, and the edges of the pixel electrode 191, is disposed on the passivation layer 180, the initialization voltage line 192, and the edges of the pixel electrode 191. The pixel defining layer 350 has a pixel opening 351 exposing the pixel electrode 191. The pixel defining layer 350 can be formed of organic materials such as polyacrylate resin and polyimide resin, as well as silicon-based organic materials.

[0138] An organic emitting layer 370 is disposed on the pixel electrode 191 exposed through the pixel opening 351, and a common electrode 270 is disposed on the organic emitting layer 370. The common electrode 270 is also disposed on the pixel defining layer 350 above the plurality of pixels PX. In this way, an OLED including the pixel electrode 191, the organic emitting layer 370, and the common electrode 270 is formed.

[0139] Here, pixel electrode 191 serves as the anode, acting as a hole injection electrode, and common electrode 270 serves as the cathode, acting as an electron injection electrode. However, the exemplary embodiments of this disclosure are not limited to this; according to the driving method of the foldable display device, pixel electrode 191 can be the cathode and common electrode 270 can be the anode. Holes and electrons are injected into the organic emitter layer 370 from pixel electrode 191 and common electrode 270, respectively. Furthermore, excitons generated by combining the injected holes and electrons are degraded from the excited state to the ground state.

[0140] The organic emitter layer 370 is formed of a low-molecular-weight organic material or a high-molecular-weight organic material such as poly(3,4-ethylenedioxythiophene) (PEDOT). Furthermore, the organic emitter layer 370 can be formed as a multilayer comprising at least one of an emitter layer, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). When the organic emitter layer 370 comprises all layers, the hole injection layer is disposed on the pixel electrode 191, which serves as the positive electrode. The hole transport layer, the emitter layer, the electron transport layer, and the electron injection layer are sequentially stacked on the hole injection layer.

[0141] The organic emission layer 370 may include a red organic emission layer that emits red light, a green organic emission layer that emits green light, and a blue organic emission layer that emits blue light. The red, green, and blue organic emission layers are respectively disposed at red, green, and blue pixels to achieve a color image.

[0142] Furthermore, in the organic emission layer 370, the red, green, and blue organic emission layers are stacked together on the red, green, and blue pixels, respectively. A red, green, and blue color filter is formed for each pixel to achieve a color image. As another example, a white organic emission layer emitting white light is formed on all the red, green, and blue pixels. A red, green, and blue color filter is formed for each pixel to achieve a color image. When a color image is achieved using a white organic emission layer and color filters, in some embodiments, a deposition mask for depositing the red, green, and blue organic emission layers on individual pixels (i.e., red, green, and blue pixels) is not used.

[0143] In another example, the white organic emitting layer described can be formed from a single organic emitting layer and can include a structure that emits white light by stacking multiple organic emitting layers. As an example, the white organic emitting layer includes a structure capable of emitting white light by combining at least one yellow organic emitting layer and at least one blue organic emitting layer. The white organic emitting layer can include a structure capable of emitting white light by combining at least one cyan organic emitting layer and at least one red organic emitting layer, a structure capable of emitting white light by combining at least one magenta organic emitting layer and at least one green organic emitting layer, and so on.

[0144] An encapsulation component (not shown) protecting the OLED can be disposed on the common electrode 270. The encapsulation component can be sealed to the substrate 110 by a sealant and can be formed from various materials such as glass, quartz, ceramic, plastic and metal. The thin film encapsulation layer can be disposed on the common electrode 270 by depositing an inorganic layer and an organic layer and using a sealant.

[0145] In an exemplary embodiment, the first non-contact semiconductor region is located on the shortest path preceding the compensation contact hole, but as another exemplary embodiment, the first non-contact semiconductor region may be located on a detour path following the compensation contact hole.

[0146] Next, refer to Figure 12 and Figure 13 Describes an OLED display according to another exemplary embodiment of the present disclosure.

[0147] Figure 12 This is an enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 of the red and green pixels of an OLED display according to another exemplary embodiment of the present disclosure. Figure 13 Is in Figure 12 An enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 when interlayer orientation error occurs.

[0148] Apart from the first non-contact semiconductor region located on the detour path behind the compensation contact hole, Figure 12 and Figure 13 The exemplary embodiments shown in the figure are similar to those shown in the figure. Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The exemplary embodiments shown are substantially the same, thus omitting repeated descriptions.

[0149] like Figure 12As shown, the width d1 of the first expanded semiconductor portion 32a of the OLED display according to the present exemplary embodiment of the present disclosure can be larger than the width d2 of the narrow semiconductor portion. Furthermore, the edge of the first expanded semiconductor portion 32a surrounds the edge of the compensation contact hole 63. That is, the first expanded semiconductor portion 32a includes a first contact semiconductor region P1 superimposed on the compensation contact hole 63 and a first non-contact semiconductor region Q1 not superimposed on the compensation contact hole 63. The edge of the first expanded semiconductor portion 32a and the edge of the compensation contact hole 63 are separated from each other in the first non-contact semiconductor region Q1. The first non-contact semiconductor region Q1 is located on a detour path C behind the compensation contact hole 63. Therefore, a sufficient current flow path can be obtained through the first non-contact semiconductor region Q1 provided in the first expanded semiconductor portion 32a.

[0150] Figure 13 When interlayer orientation error causes the data metal line to shift to Figure 12 The right side of the diagram shows an enlarged layout of the switching transistor T2 and the compensation transistor T3.

[0151] like Figure 13 As shown, when interlayer alignment errors occur during the manufacturing process of a high-resolution structure, the drive connection member 174 and the data line 171 are shifted to the right by a predetermined interval t1 relative to their positions in the original design. Therefore, one end of the drive connection member 174 does not completely cover the compensation contact hole 63, exposing a portion of the compensation contact hole 63. Etching agent penetrates through the exposed compensation contact hole 63, damaging a portion of the first expanded semiconductor section 32a. However, even if the first contact semiconductor region P1 of the first expanded semiconductor section 32a is damaged, the first non-contact semiconductor region Q1 remains undamaged, thus obtaining a current flow path between the compensation drain electrode 137c and the initialization drain electrode 137d. This current flow path corresponds to the circuitous path C following the compensation contact hole 63.

[0152] As described above, by forming a first non-contact semiconductor region Q1 corresponding to the detour path C behind the compensation contact hole 63 in the first expanded semiconductor section 32a provided at the position corresponding to the compensation contact hole 63, a sufficient current flow path can be obtained in the first expanded semiconductor section 32a. Therefore, openings in the first expanded semiconductor section 32a caused by the penetration of etchant used for data metal lines through the compensation contact hole 63 due to interlayer alignment errors can be prevented. Therefore, uneven illumination between adjacent pixels can be prevented in a high-resolution structure.

[0153] On the other hand, in an exemplary embodiment, in order to prevent openings in the semiconductor component, the width of the expanded semiconductor portion is larger than the width of the narrow semiconductor portion. As another exemplary embodiment, the width of the expanded data metal portion may be larger than the width of the data metal portion to prevent openings in the semiconductor component.

[0154] Next, refer to Figure 14 and Figure 15 Describes an OLED display according to another exemplary embodiment of the present disclosure.

[0155] Figure 14 This is an enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 of the red and green pixels of an OLED display according to another exemplary embodiment of the present disclosure. Figure 15 Is in Figure 14 An enlarged layout diagram of the switching transistor T2 and the compensation transistor T3 when interlayer orientation error occurs.

[0156] In addition to the expanded data metal section, which has a width greater than that of a normal data metal section, Figure 14 and Figure 15 The exemplary embodiments shown in the figure are similar to those shown in the figure. Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The exemplary embodiments shown are the same, so repeated descriptions are omitted.

[0157] like Figure 14 and Figure 15 As shown, as part of the data metal lines (171, 172, 174, 175 and 179) of the OLED display according to the present exemplary embodiment of the present disclosure, the drive connection member 174 includes: a drive connection portion 174b, as a normal data metal portion having a first width d4; and a drive expansion portion 174a, as an expanded data metal portion having a second width d5 ​​that is larger than the first width d4.

[0158] The normal data metal section 174b corresponds to most of the data metal lines such as data line 171 and drive voltage line 172.

[0159] The semiconductor component 130 includes: a bent semiconductor portion 33, which is disposed at a position corresponding to the compensation contact hole 63 and has a bent shape; and a semiconductor strip portion 34, which has a strip shape. The bent semiconductor portion 33 is stacked on the plane with the drive expansion portion 174a.

[0160] The edge of the drive expansion portion 174a surrounds the edge of the compensation contact hole 63. That is, the drive expansion portion 174a includes a contact data region P3 that overlaps with the compensation contact hole 63 and a non-contact data region Q3 that does not overlap with the compensation contact hole 63. The edge of the drive expansion portion 174a is separated from the edge of the compensation contact hole 63 within the non-contact data region Q3. Therefore, a sufficient current movement path can be obtained through the non-contact data region Q3 provided in the drive expansion portion 174a.

[0161] Figure 15 This illustrates when interlayer orientation errors cause the drive connection member to shift to... Figure 14 The right side of the diagram shows an enlarged layout of the switching transistor T2 and the compensation transistor T3.

[0162] like Figure 15 As shown, when interlayer orientation error occurs in the manufacturing process of the high-resolution structure, the drive connection member 174 and the data line 171 are shifted to the right by a predetermined interval t1 relative to their positions in the original design.

[0163] Therefore, the drive expansion portion 174a of the green pixel G does not completely cover the compensation contact hole 63, leaving a portion of the compensation contact hole 63 exposed. Etching agent penetrates through the exposed compensation contact hole 63, causing partial damage to the bent semiconductor portion 33. However, even though the portion of the bent semiconductor portion 33 is damaged by the etchant, a current movement path D between the compensation drain electrode 137c and the initialization drain electrode 137d is still obtained in the green pixel G.

[0164] In this case, the width d5 ​​of the drive expansion portion 174a of the drive connection member 174 is larger than the width d4 of the drive connection portion 174b. The drive expansion portion 174a also surrounds the compensation contact hole 63 through the non-contact data area Q3, so that the drive expansion portion 174a of the red pixel R effectively completely covers the compensation contact hole 63, thereby preventing the bent semiconductor portion 33 of the red pixel R from being damaged by the etchant.

[0165] Therefore, the opening of the bent semiconductor portion 33 caused by the penetration of etchant used for data metal lines through the compensation contact hole 63 due to interlayer orientation errors can be prevented. Thus, uneven illumination between adjacent pixels in a high-resolution structure can be prevented.

[0166] While the inventive techniques have been described in conjunction with what are now considered to be actual exemplary embodiments, it is to be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An organic light-emitting diode (OLED) display, the OLED display comprising: Base; A semiconductor layer is located on the substrate, wherein the semiconductor layer is curved in a plan view; A first metal layer is located on the semiconductor layer and includes scan lines configured to transmit scan signals; An insulating layer covers the semiconductor layer and the first metal layer and has a plurality of contact holes connected to the semiconductor layer; A second metal layer, located on the insulating layer, includes data lines and a drive connector. The data lines intersect the scan lines and are configured to transmit data voltage. The drive connector is electrically connected to the semiconductor layer via a selected contact hole from the plurality of contact holes. Organic light-emitting diodes are electrically connected to the scan lines and the data lines. The semiconductor layer includes a narrow semiconductor portion having a first width and an expanded semiconductor portion having a second width greater than the first width. The narrow semiconductor portion has a first portion extending in the extension direction of the scan line and a second portion extending in the extension direction of the data line. The expanded semiconductor portion is disposed between the first portion and the second portion. Wherein, the first width is the distance between the edges of the narrow semiconductor portions, and the second width is the distance between the edges of the expanded semiconductor portions. Wherein, a portion of the edge of the expanded semiconductor portion is a diagonal line disposed between the first portion and the second portion of the narrow semiconductor portion, and another portion of the edge of the expanded semiconductor portion is a corner disposed between the first portion and the second portion of the narrow semiconductor portion. The selected contact hole is positioned closer to the corner than to the diagonal line, and The drive connector is superimposed on at least a portion of the expanded semiconductor portion, but not on the entire expanded semiconductor portion.

2. The organic light-emitting diode display according to claim 1, wherein, The edge of the expanded semiconductor portion surrounds the selected contact hole.

3. The organic light-emitting diode display according to claim 1, wherein, The expanded semiconductor portion includes a contact semiconductor region that overlaps with the selected contact hole in the depth dimension of the organic light-emitting diode display and a non-contact semiconductor region that does not overlap with the selected contact hole in the depth dimension of the organic light-emitting diode display. The edge of the expanded semiconductor portion is separated from the edge of the selected contact hole in the non-contact semiconductor region.

4. The organic light-emitting diode display according to claim 3, further comprising: The driving voltage line intersects the scan line and is configured to transmit the driving voltage; A switching transistor is electrically connected to the scan line and the data line; A driving transistor, electrically connected to the switching transistor, and including a portion of the semiconductor layer as a driving channel, a driving gate electrode superimposed on the driving channel at the depth dimension of the organic light-emitting diode display, and a driving source electrode and a driving drain electrode located at the end of the driving channel. A compensation transistor includes another portion of the semiconductor layer as a compensation channel, a compensation gate electrode superimposed on the compensation channel at the depth dimension of the organic light-emitting diode display, and a compensation source electrode and a compensation drain electrode located at opposite ends of the compensation channel, wherein the compensation source electrode is electrically connected to the driving drain electrode. The drive connector is configured to electrically connect the compensation drain electrode to the drive gate electrode. The previous scan line is substantially parallel to the scan line and is configured to transmit the previous scan signal; An initialization voltage line is configured to transmit an initialization voltage, which is configured to initialize the drive transistor; and An initialization transistor is configured to be turned on based on the previous scan signal and includes initialization of the channel, gate electrode, source electrode, and drain electrode. The expanded semiconductor section includes a first expanded semiconductor section configured to electrically connect the compensation drain electrode to the initialization drain electrode.

5. The organic light-emitting diode display according to claim 4, wherein, The selected contact holes include: a compensation contact hole located where the drive connector and the first expanded semiconductor portion overlap each other in the depth dimension of the organic light-emitting diode display, and The first expanded semiconductor portion includes a first contact semiconductor region superimposed with the compensation contact hole on the depth dimension of the organic light-emitting diode display and a first non-contact semiconductor region not superimposed with the compensation contact hole on the depth dimension of the organic light-emitting diode display, wherein the edge of the first expanded semiconductor portion and the edge of the compensation contact hole are separated from each other in the first non-contact semiconductor region.

6. The organic light-emitting diode display according to claim 5, wherein, A portion of the edge of the first expanded semiconductor portion is a diagonal line disposed between the first portion and the second portion of the narrow semiconductor portion, and another portion of the edge of the first expanded semiconductor portion is a corner disposed between the first portion and the second portion of the narrow semiconductor portion, wherein the first non-contact semiconductor region is disposed between the diagonal line and the edge of the compensation contact hole.

7. The organic light-emitting diode display according to claim 5, wherein, A portion of the edge of the first expanded semiconductor portion is a diagonal line disposed between the first portion and the second portion of the narrow semiconductor portion, and another portion of the edge of the first expanded semiconductor portion is a corner disposed between the first portion and the second portion of the narrow semiconductor portion, wherein the first non-contact semiconductor region is located between the corner and the edge of the compensation contact hole.

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