An Overload-Proof Passive Adder for Discrete Sigma-Delta Modulators

Abstract

The present invention proposes an anti-overload passive adder for a discrete Sigma-Delta modulator, comprising a non-overlapping clock source, a switched capacitor circuit, a voltage comparator and an OR gate. The output voltage of the passive adder is obtained by using a charge redistribution technique, and the polarity is determined by a voltage comparator and an OR gate with a reference voltage. The polarity signal output by the OR gate is used to control the sampling capacitance value of an integrator in the modulator, and the coefficient of the integrator is adjusted to ensure that the modulator still operates in a stable state when the input signal amplitude is large. The invention improves and retains the advantage of low power consumption of the passive adder through a simple circuit, and effectively avoids the problem of a sharp drop in the signal-to-noise ratio of the output signal caused by an overload of the modulator.

Description

Technical Field

[0001] The invention discloses an overload-proof passive adder for a discrete Sigma-Delta modulator, belongs to the technical field of analog integrated circuits, and is mainly applied to a discrete feedforward Sigma-Delta analog-to-digital converter. Background Art

[0002] As a high-precision analog-to-digital converter, Sigma-Delta ADC is widely used in modern communications, medical, and portable electronic systems. As integrated circuit manufacturing processes continue to evolve towards deep submicron, power supply voltages are reduced, and application systems, especially biomedical systems, have increasingly higher requirements for power consumption. The design of high-precision Sigma-Delta ADCs faces increasingly complex challenges and has become one of the most active areas of concern in academia and industry in recent years. Sigma-Delta ADC is the most widely used converter in the field of modern voice bands and high-resolution precision measurements. It uses oversampling and noise shaping technology to trade speed for accuracy, achieving higher accuracy with lower analog circuit complexity. Therefore, how to reduce the power consumption of the system while achieving high-precision conversion has become a mainstream research hotspot.

[0003] The current Sigma-Delta modulator is mainly composed of two basic structures, feedback structure and feedforward structure. Among them, the feedforward structure is more conducive to achieving low power consumption. Although the feedback structure can obtain a better signal transfer function, it requires a larger integrator voltage amplitude range, which requires the transconductance amplifier in each stage of the integrator to achieve a high slew rate and a large swing, which increases power consumption; while the feedforward structure greatly reduces the voltage amplitude range of the integrator, thereby reducing the design requirements of the transconductance amplifier in each stage of the integrator. Therefore, low-power Sigma-Delta modulators mostly use feedforward systems, and feedforward systems generally use adders.

[0004] However, one of the problems with Sigma-Delta modulators is the stability of the overall circuit. The modulator usually requires multiple integrators to be cascaded. When the input signal amplitude is large, the modulator is easily overloaded, that is, the output of each integrator exceeds its output swing, and even the voltage at one end is as high as the power supply voltage, and the voltage at the other end is as low as the ground potential. At this time, the signal-to-noise ratio of the modulator output signal drops significantly, and serious distortion occurs.

[0005] Therefore, for the Sigma-Delta modulator, the overall system stability must be considered during design, and the coefficients of each stage of the integrator must be adjusted properly. At the same time, when the input signal swing is large, the entire modulator must still be kept in a stable state to avoid overload. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and propose an anti-overload passive adder for a discrete Sigma-Delta modulator. Through simple circuit improvement, the multi-channel signal summing function is realized. At the same time, by controlling the sampling capacitor value of the integrator in the modulator, the overload problem of the modulator under a large input signal amplitude is solved. The present invention can be widely used in discrete feedforward Sigma-Delta modulators.

[0007] The technical solution to achieve the purpose of the present invention is:

[0008] An overload-proof passive adder for a discrete Sigma-Delta modulator comprises a non-overlapping clock generation source for generating two-phase non-overlapping clocks; a switched capacitor circuit for realizing a multi-channel signal summing function; a voltage comparator and an OR gate for generating a polarity signal for controlling an integrator sampling capacitor value according to an output voltage of the adder and a reference voltage Vref.

[0009] Among them, one end of the first switch SW1 is connected to the first input port Vip1, and the other end is connected to the left end of the first capacitor Ca1; one end of the second switch SW2 is connected to the second input port Vip2, and the other end is connected to the left end of the second capacitor Ca2; one end of the third switch SW3 is connected to the third input port Vin2, and the other end is connected to the left side of the third capacitor Ca3; one end of the fourth switch SW4 is connected to the fourth input port Vin1, and the other end is connected to the left side of the fourth capacitor Ca4.

[0010] One end of the fifth switch SW5 is connected to the reference voltage Vcm, and the other end is connected to the left end of the first capacitor Ca1; one end of the sixth switch SW6 is connected to the reference voltage Vcm, and the other end is connected to the left end of the second capacitor Ca2; one end of the seventh switch SW7 is connected to the reference voltage Vcm, and the other end is connected to the left end of the third capacitor Ca3; one end of the eighth switch SW8 is connected to the reference voltage Vcm, and the other end is connected to the left end of the fourth capacitor Ca4; one end of the ninth switch SW9 is connected to the reference voltage Vcm, and the other end is connected to the right end of the second capacitor Ca2; one end of the tenth switch SW10 is connected to the reference voltage Vcm, and the other end is connected to the left end of the third capacitor Ca3.

[0011] The positive input of the first comparator Com1 is connected to the first output port Vop of the adder, and the negative input is connected to the reference voltage Vref; the positive input of the second comparator Com2 is connected to the second output port Von of the adder, and the negative input is connected to the reference voltage Vref; the outputs of the first comparator Com1 and the second comparator Com2 are connected to the input of the OR gate OR, and the output of the OR gate is the third output port Vc of the adder.

[0012] An overload protection passive adder for discrete Sigma-Delta modulators. The working steps of the circuit are briefly described as follows.

[0013] Step 1: In the high phase of CK2, switches SW5, SW6, SW7, SW8, SW9, and SW10 are closed, switches SW1, SW2, SW3, and SW4 are opened, and the charges on capacitors Ca1, Ca2, Ca3, and Ca4 are cleared. In the high phase of CK1, switches SW1, SW2, SW3, and SW4 are closed, and switches SW5, SW6, SW7, SW8, SW9, and SW10 are opened. According to the values ​​of input signals Vip1, Vip2, Vin1, Vin2 and capacitors Ca1, Ca2, Ca3, and Ca4, the multi-channel signal summation voltage Vop and Von of the switched capacitor circuit are obtained.

[0014] Step 2: In step 1, the summed voltage Vop, Von and the reference voltage Vref of the multiple signals are connected to the positive and negative terminals of the comparators Com1 and Com2 respectively. The comparison will determine the polarity of the difference between the summed voltage and the reference voltage. The output signals of the two comparators finally output the corresponding logic level Vc through the OR gate OR. Finally, the signal Vc is used to control the sampling capacitor value of the integrator to prevent the modulator from working in an overload state. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 1 is a schematic diagram of a non-overlapping clock generation submodule used in the present invention.

[0016] Figure 2 This is a circuit diagram of the anti-overload passive adder proposed by the present invention.

[0017] Figure 3 This is an exemplary circuit structure diagram of the overload protection passive adder proposed by the present invention used in a modulator. DETAILED DESCRIPTION

[0018] In order to make the purpose and technical advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of application of the present invention.

[0019] like Figure 2 The circuit structure diagram of the present invention is shown, which is an anti-overload passive adder for discrete Sigma-Delta modulator, including a non-overlapping clock generation source for generating two-phase non-overlapping clocks; a switched capacitor circuit for realizing the multi-channel signal summing function; a voltage comparator and an OR gate for generating a polarity signal for controlling the switch and integrator capacitance value in the adder according to the output voltage of the adder and the value of the reference voltage Vref.

[0020] Among them, one end of the first switch SW1 is connected to the first input port Vip1, and the other end is connected to the left end of the first capacitor Ca1; one end of the second switch SW2 is connected to the second input port Vip2, and the other end is connected to the left end of the second capacitor Ca2; one end of the third switch SW3 is connected to the third input port Vin2, and the other end is connected to the left side of the third capacitor Ca3; one end of the fourth switch SW4 is connected to the fourth input port Vin1, and the other end is connected to the left side of the fourth capacitor Ca4.

[0021] One end of the fifth switch SW5 is connected to the reference voltage Vcm, and the other end is connected to the left end of the first capacitor Ca1; one end of the sixth switch SW6 is connected to the reference voltage Vcm, and the other end is connected to the left end of the second capacitor Ca2; one end of the seventh switch SW7 is connected to the reference voltage Vcm, and the other end is connected to the left end of the third capacitor Ca3; one end of the eighth switch SW8 is connected to the reference voltage Vcm, and the other end is connected to the left end of the fourth capacitor Ca4; one end of the ninth switch SW9 is connected to the reference voltage Vcm, and the other end is connected to the right end of the second capacitor Ca2; one end of the tenth switch SW10 is connected to the reference voltage Vcm, and the other end is connected to the left end of the third capacitor Ca3.

[0022] The positive input of the first comparator Com1 is connected to the first output port Vop of the adder, and the negative input is connected to the reference voltage Vref; the positive input of the second comparator Com2 is connected to the second output port Von of the adder, and the negative input is connected to the reference voltage Vref; the outputs of the first comparator Com1 and the second comparator Com2 are connected to the input of the OR gate OR, and the output of the OR gate is the third output port Vc of the adder.

[0023] The circuit uses two-phase non-overlapping clock operation:

[0024] In the high phase of CK2, switches SW5, SW6, SW7, SW8, SW9, and SW10 are closed, switches SW1, SW2, SW3, and SW4 are opened, the charges on capacitors Ca1, Ca2, Ca3, and Ca4 are cleared, and the output voltages of the adder Vop=Vcm and Von=Vcm.

[0025] In the high phase of CK1, switches SW1, SW2, SW3, and SW4 are closed, and switches SW5, SW6, SW7, SW8, SW9, and SW10 are opened. According to the values ​​of input signals Vip1, Vip2, Vin1, and Vin2 and capacitors Ca1, Ca2, Ca3, and Ca4, the multi-channel signal sum voltage of the switched capacitor circuit is obtained:

[0026]

[0027]

[0028] The summed voltage Vop, Von of multiple signals and the reference voltage Vref are connected to the positive and negative terminals of the comparators Com1 and Com2 respectively. The comparison will determine the polarity of the difference between the summed voltage and the reference voltage. The output signals of the two comparators finally output the corresponding logic level Vc through the OR gate OR. Finally, the signal Vc is used to control the switch of the first-stage integrator to change the sampling capacitor value of the integrator to prevent the modulator from working in an overload state.

[0029] like Figure 3 The figure shows an example of the present invention being applied to a Sigma-Delta modulator.

[0030] When the value of the summed voltage Vop and Von of the adder is less than the reference voltage Vref, the polarity signal Vc is at a low level, and its value is the ground voltage, indicating that the entire modulator is working normally, and the sampling capacitor value of the first-stage integrator remains unchanged at Cs1+Cs3. When the summed voltage Vop or Von of the adder is greater than the reference voltage Vref, the polarity signal Vc output by the adder is at a high level, and its value is the power supply voltage, indicating that the input signal amplitude is too large and the modulator has been working in an overload state. The control signal Vc adjusts the sampling capacitor value of the first-stage integrator to Cs1, reduces the coefficient of the first-stage integrator, and allows the entire modulator to get rid of the overload state at this input amplitude and return to stability, thereby avoiding a significant decrease in the output signal-to-noise ratio.

Claims

1. An overload-proof passive adder for discrete Sigma-Delta modulators, characterized in that: include: A non-overlapping clock generation source for generating two-phase non-overlapping clocks (Ck1) and (Ck2); A switched capacitor circuit, for generating corresponding output voltages (Vop) and (Von) according to the voltage values ​​of the first input port (Vip1), the second input port (Vip2), the third input port (Vin2), and the fourth input port (Vin1), and the capacitance values ​​of the first capacitor (Ca1), the second capacitor (Ca2), the third capacitor (Ca3), and the fourth capacitor (Ca4); A voltage comparator and an OR gate for generating a polarity signal for controlling a capacitance value of an integrator according to an output voltage of the adder and a value of a reference voltage (Vref); In the switched capacitor circuit, one end of the first switch (SW1) is connected to the first input port (Vip1), and the other end is connected to the left end of the first capacitor (Ca1); one end of the second switch (SW2) is connected to the second input port (Vip2), and the other end is connected to the left end of the second capacitor (Ca2); one end of the third switch (SW3) is connected to the third input port (Vin2), and the other end is connected to the left side of the third capacitor (Ca3); one end of the fourth switch (SW4) is connected to the fourth input port (Vin1), and the other end is connected to the left side of the fourth capacitor (Ca4); A fifth switch (SW5) has one end connected to a reference voltage (Vcm) and the other end connected to the left end of the first capacitor (Ca1); a sixth switch (SW6) has one end connected to the reference voltage (Vcm) and the other end connected to the left end of the second capacitor (Ca2); a seventh switch (SW7) has one end connected to the reference voltage (Vcm) and the other end connected to the left end of the third capacitor (Ca3); an eighth switch (SW8) has one end connected to the reference voltage (Vcm) and the other end connected to the left end of the fourth capacitor (Ca4); a ninth switch (SW9) has one end connected to the reference voltage (Vcm) and the other end connected to the right ends of the first capacitor (Ca1) and the second capacitor (Ca2); a tenth switch (SW10) has one end connected to the reference voltage (Vcm) and the other end connected to the right ends of the third capacitor (Ca3) and the fourth capacitor (Ca4); The positive input of the first comparator (Com1) is connected to the first output port (Vop) of the adder, and the negative input is connected to the reference voltage (Vref); the positive input of the second comparator (Com2) is connected to the second output port (Von) of the adder, and the negative input is connected to the reference voltage (Vref); the outputs of the first comparator (Com1) and the second comparator (Com2) are connected to the two input terminals of the OR gate (OR), and the output of the OR gate is the third output port (Vc) of the adder.

2. The overload protection passive adder for discrete Sigma-Delta modulator according to claim 1, characterized in that: The switched capacitor circuit has two working phases, which are controlled by clocks (CK1) and (CK2). The fifth switch (SW5), the sixth switch (SW6), the seventh switch (SW7), the eighth switch (SW8), the ninth switch (SW9), and the tenth switch (SW10) are closed, the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) are opened, the charges on the first capacitor (Ca1), the second capacitor (Ca2), the third capacitor (Ca3), and the fourth capacitor (Ca4) are cleared, the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) are closed, the fifth switch (SW5), the sixth switch (SW6), the seventh switch (SW7), the eighth switch (SW8), the ninth switch (SW9), and the tenth switch (SW10) are opened, and the output voltages (Vop) and (Von) of the switched capacitor circuit are obtained.

3. The overload protection passive adder for discrete Sigma-Delta modulator according to claim 1, characterized in that: According to the output voltage (Vop) and (Von) of the adder and the reference voltage (Vref), the output polarity signal (Vc) is obtained through the comparator and OR gate logic. The value of the signal (Vc) is used to determine whether the modulator is working in an overload state. When the (Vc) signal is at a low level, the modulator is stable and in normal working condition. When the (Vc) signal is at a high level, it means that the input signal amplitude is too large and the modulator is overloaded. The switch of the integrator is controlled to adjust the sampling capacitor value to return the entire modulator to a stable state.

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