Tight back-end process pitch ladder interconnects
By using PVD to form trapezoidal trenches in the dielectric and combining it with CVD/ALD to deposit thin films, the problem of reduced conductor area caused by excessive barrier layer thickness is solved, and a low-resistance and high-performance interconnect structure is achieved.
Patent Information
- Application Number
- CN202080050904.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-09-17
- Filing Date
- 2020-08-14
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2040-08-14
AI Technical Summary
When forming interconnects with tight back-end process spacing in existing technologies, the barrier layer is too thick, resulting in a reduction in conductor area and an increase in resistance. In addition, traditional thin film deposition technology makes it difficult to effectively control the trench profile.
Physical vapor deposition (PVD) is used to deposit a thick liner in the dielectric to open the trapezoidal trench profile, followed by selective removal of the liner and deposition of a thin conformal barrier layer and wetting layer, combined with chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the interconnect structure.
By increasing the conductor area, reducing the interconnect resistance, and improving chip performance, especially when using cobalt (Co), ruthenium (Ru) or copper (Cu) as conductors, the electromigration performance is significantly improved.