Tight back-end process pitch ladder interconnects

By using PVD to form trapezoidal trenches in the dielectric and combining it with CVD/ALD to deposit thin films, the problem of reduced conductor area caused by excessive barrier layer thickness is solved, and a low-resistance and high-performance interconnect structure is achieved.

CN114127912BActive Publication Date: 2025-09-16INTERNATIONAL BUSINESS MACHINE CORPORATION
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Patent Information

Application Number
CN202080050904.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-09-17
Filing Date
2020-08-14
Publication Date
2025-09-16
Estimated Expiration
2040-08-14

AI Technical Summary

Technical Problem

When forming interconnects with tight back-end process spacing in existing technologies, the barrier layer is too thick, resulting in a reduction in conductor area and an increase in resistance. In addition, traditional thin film deposition technology makes it difficult to effectively control the trench profile.

Method used

Physical vapor deposition (PVD) is used to deposit a thick liner in the dielectric to open the trapezoidal trench profile, followed by selective removal of the liner and deposition of a thin conformal barrier layer and wetting layer, combined with chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the interconnect structure.

Benefits of technology

By increasing the conductor area, reducing the interconnect resistance, and improving chip performance, especially when using cobalt (Co), ruthenium (Ru) or copper (Cu) as conductors, the electromigration performance is significantly improved.

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Abstract

Techniques for forming a trapezoidal interconnect are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench having a V-shaped profile with a rounded bottom in a dielectric; depositing a liner into the trench using PVD, the PVD opening the trench to create a trapezoidal profile in the trench; removing the liner from the trench selectively relative to the dielectric, whereby, after removal, the trench having the trapezoidal profile remains in the dielectric; depositing a conformal barrier layer into the trench having the trapezoidal profile and lining the trench; depositing a conductor over the conformal barrier layer and filling the trench having the trapezoidal profile; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.
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