Logic diagram compilation detection method, system, electronic device and storage medium

Abstract

The present application relates to a logic diagram compilation detection method, system, electronic device, and storage medium. The method comprises: obtaining an initial logic diagram to be compiled and extracting the logical elements and logical structure of the initial logic diagram; converting the logical elements in the initial logic diagram into intermediate code based on the logical structure; and determining whether the intermediate code is consistent with the initial logic diagram based on a comparison result between the intermediate code and the initial logic diagram. This application avoids errors in the logic diagram compilation process, ensuring the correct output of the control system. This solves the problem in related technologies of additional losses caused by the process control system failing to output correct results, thereby achieving detection of the logic diagram compilation process.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a logic diagram compilation detection method, system, electronic device, and storage medium. Background Art

[0002] With the advent of an era of industrial informatization and technological advancement, industrial automation process control systems, with their high efficiency, low energy consumption, and low cost, have broad application prospects in industries such as petrochemicals, chemicals, and building materials. For example, various automated instruments, actuators, and other systems can be controlled by process control systems to complete specific process flows. As a universal control system, process control systems require specific control programs to be written within their configuration software for specific process sites to complete the specific process flows described above. Generally, logic diagrams used to write control programs include graphical programming languages, text-based programming languages, and cause-and-effect tables.

[0003] In related technologies, when using a process control system, the executable code compiled from the logic diagram is directly used to implement the control of the process treatment process. If an error occurs in the logic diagram during the compilation process, resulting in the executable code finally used being inconsistent with the control logic in the logic diagram, the process control system will not be able to output the correct results, thereby causing additional losses.

[0004] There is currently no effective solution to the problem of how to avoid errors in the logic diagram during editing, storage, and compilation, and ensure the correct output of the control system. Summary of the Invention

[0005] In this embodiment, a logic diagram compilation detection method, system, electronic device and storage medium are provided to solve the problem in the related art of how to avoid errors in the logic diagram during compilation and ensure the correct output of the control system.

[0006] In a first aspect, a logic diagram compilation detection method is provided in this embodiment, including:

[0007] Obtaining an initial logic diagram to be compiled and extracting logic elements and a logic structure of the initial logic diagram;

[0008] According to the logic structure, converting the logic elements in the initial logic diagram into intermediate codes;

[0009] According to the comparison result between the intermediate code and the initial logic diagram, it is determined whether the intermediate code is consistent with the initial logic diagram.

[0010] In some embodiments, converting the logic elements in the initial logic diagram into intermediate codes according to the logic structure includes:

[0011] According to the logic structure, converting the plurality of logic elements in the initial logic diagram into corresponding intermediate statements to obtain a plurality of intermediate statements;

[0012] determining an intermediate statement sequence according to the plurality of intermediate statements;

[0013] The intermediate code is obtained according to a plurality of intermediate statement sequences.

[0014] In some embodiments, converting the plurality of logic elements in the initial logic diagram into corresponding intermediate statements according to the logic structure includes:

[0015] Convert each of the initial logic elements into a corresponding logic instruction statement;

[0016] According to the logic structure, the logic instruction statements are grouped into intermediate statements.

[0017] In some embodiments, determining whether the intermediate code is consistent with the initial logic diagram based on a comparison result between the intermediate code and the initial logic diagram includes:

[0018] Converting the initial logic diagram into a first verification expression, and converting the intermediate code into a second verification expression;

[0019] Whether the intermediate code is consistent with the initial logic diagram is determined according to the comparison result of the first verification expression and the second verification expression.

[0020] In some embodiments, determining whether the intermediate code is consistent with the initial logic diagram based on a comparison result between the intermediate code and the initial logic diagram includes:

[0021] Converting the intermediate code into a verification logic diagram, wherein the language of the verification logic diagram is consistent with the language of the initial logic diagram;

[0022] The logical elements of the verification logic diagram are compared with the logical elements of the initial logic diagram, and whether the intermediate code is consistent with the initial logic diagram is determined based on the comparison result.

[0023] In some embodiments, determining whether the intermediate code is consistent with the initial logic diagram based on the comparison result further includes:

[0024] Identifying differences in logic elements between the verification logic diagram and the initial logic diagram, and generating difference information based on the differences in logic elements;

[0025] Whether the intermediate code is consistent with the initial logic diagram is determined according to the difference information.

[0026] In some embodiments, before extracting the logic elements of the initial logic diagram, the method includes:

[0027] Performing syntax checking and semantic parsing on the initial logic diagram.

[0028] In a second aspect, a logic diagram compilation detection system is provided in this embodiment, including: an acquisition module, a conversion module, and a judgment module;

[0029] The acquisition module is used to acquire the initial logic diagram to be compiled and extract the logic elements and logic structure of the initial logic diagram;

[0030] The conversion module is used to convert the logical elements in the initial logic diagram into intermediate codes according to the logical structure;

[0031] The judgment module is used to judge whether the intermediate code is consistent with the initial logic diagram based on the comparison result between the intermediate code and the initial logic diagram.

[0032] In a third aspect, an electronic device is provided in this embodiment, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the logic diagram compilation detection method described in the first aspect when executing the computer program.

[0033] In a fourth aspect, a storage medium is provided in this embodiment, on which a computer program is stored. When the program is executed by a processor, the logic diagram compilation detection method described in the first aspect is implemented.

[0034] Compared with the related art, the logic diagram compilation detection method provided in this embodiment first obtains the initial logic diagram to be compiled and extracts the logical elements and logical structure of the initial logic diagram; then, according to the logical structure, the logical elements in the initial logic diagram are converted into intermediate code; finally, based on the comparison result between the intermediate code and the initial logic diagram, it is judged whether the intermediate code is consistent with the initial logic diagram, which solves the problem of additional losses caused by logic diagram compilation errors in the related art and realizes the detection of the compilation process of the logic diagram.

[0035] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0037] Figure 1 This is a hardware structure block diagram of a terminal of the logic diagram compilation detection method according to an embodiment of the present application;

[0038] Figure 2 is a flow chart of a logic diagram compilation detection method according to an embodiment of the present application;

[0039] Figure 3 is a flowchart of the intermediate code generation method according to an embodiment of the present application;

[0040] Figure 4 is a schematic diagram of the intermediate code of an embodiment of the present application;

[0041] Figure 5 This is a flow chart of a logic diagram compilation detection method according to a preferred embodiment of the present application;

[0042] Figure 6 It is a structural block diagram of the device for logic diagram compilation and detection in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0044] Unless otherwise defined, the technical terms or scientific terms involved in this application should have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "an", "a", "the", "these" and the like in this application do not indicate quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Generally, the character " / " indicates that the related objects are in an "or" relationship. The terms "first," "second," "third," etc. used in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0045] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. For example, running on a terminal, Figure 1 FIG. 1 is a block diagram of the hardware structure of the terminal of the logic diagram compilation detection method of this embodiment. Figure 1 As shown, the terminal may include one or more ( Figure 1 Only one is shown) a processor 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0046] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the logic diagram compilation detection method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0047] The transmission device 106 is used to receive or send data via a network. The network may include a wireless network provided by the terminal's telecommunications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0048] In this embodiment, a logic diagram compilation detection method is provided. Figure 2 Flowchart of the logic diagram compilation detection method of this embodiment is as follows: Figure 2 As shown, the process includes the following steps:

[0049] Step S201, obtaining an initial logic diagram to be compiled and extracting the logic elements and logic structure of the initial logic diagram;

[0050] In this embodiment, the initial logic diagram to be compiled needs to be analyzed and its logical elements are obtained, wherein the logic diagram can be a graphical programming language, a text programming language, a cause-and-effect table, etc. Furthermore, the graphical programming language can be a ladder diagram (LD), an instruction list (IL), a function block diagram (FBD), or a sequential function chart (SFC). Logical elements are represented differently in different types of logic diagrams. For example, in a function block diagram, logical elements can be function blocks and the lines connecting them. Function blocks represent the processing of input data. Each function block has a type name and an instance name, which are displayed graphically. Function blocks can be called, and lines represent assignments. Furthermore, function blocks can include conditional jumps and returns. In ladder diagrams, logical elements can be buses, rungs, editing elements, and contacts. In an instruction list, they can be a series of instructions, each consisting of a function instruction and its operands. In a sequential function flow chart, they can be steps, transitions, and actions. A logical structure represents the associations between logical elements and describes the relationships between them. Furthermore, a logical structure can represent the relationships between functional modules in a logic diagram. A functional module is a module composed of multiple logical elements that performs a specific function. Multiple functional modules can form a complete logic diagram.

[0051] Step S202: converting the logic elements in the initial logic diagram into intermediate codes according to the logic structure;

[0052] After obtaining the logical elements of the initial logic diagram, the logical elements can be compiled and transcoded by the compiler into executable code used by the machine. During the transcoding process, the intermediate code that completely corresponds to the executable code can be output based on the logical structure of the logic diagram.

[0053] The logical structure is the logical relationship between data elements, that is, it describes data from a logical relationship perspective. It refers to a collection of data elements that have one or more specific relationships with each other. In this embodiment, the logical structure is a collection of relationships between logical elements. It can be based on the input and output of each logical element, the address type, etc. The intermediate code can be displayed on the human-computer interaction interface for visualization and can be saved in a text document format.

[0054] Step S203: Based on the comparison result between the intermediate code and the initial logic diagram, it is determined whether the intermediate code is consistent with the initial logic diagram.

[0055] The output results of each line of intermediate code are compared with the corresponding logical elements and the connection relationship between the logical elements in the initial logic diagram to determine whether the control method corresponding to the intermediate code is consistent with the control method corresponding to the initial logic diagram. This comparison can be performed manually or by the compiler itself or a third-party tool.

[0056] Through the above steps S201 to S203, this embodiment can generate a visual intermediate code during the logic diagram compilation process, and then realize the detection of the logic diagram compilation process by comparing the intermediate code with the initial logic diagram, thereby avoiding the possibility that errors may occur in the logic diagram during the compilation process when using the process control system, which may cause the final executable code used to be inconsistent with the control method in the logic diagram, ensuring the correct output of the control system, thereby solving the additional losses caused by the process control system's inability to output correct results and reducing unnecessary losses in process control equipment.

[0057] In some of these embodiments, Figure 3 This is a flow chart of the intermediate code generation method of the embodiment of the present application. Figure 3 As shown, the method includes the following steps:

[0058] Step S301: convert multiple logical elements in the initial logic diagram into corresponding intermediate statements according to the logical structure to obtain multiple intermediate statements;

[0059] In this embodiment, logical elements can be converted into intermediate statements according to the compilation order of each logical element on the initial logic diagram. Each logical element corresponds to an intermediate statement. The data structure of the intermediate statement includes an operator, an operator type, and multiple operands. For each operand, the corresponding name, data type, address, and address type must be specified. Each intermediate statement corresponds to an operator type.

[0060] Step S302, determining an intermediate statement sequence according to the plurality of intermediate statements;

[0061] Intermediate statements are generated in the order in which the logical elements are executed. The intermediate statement sequence is generated by arranging the intermediate statements of different operator types. Furthermore, the order in which the intermediate statements are arranged is based on the order in which the logical elements are executed. Specifically, an example of an intermediate statement sequence is as follows:

[0062] {

[0063] Statement 1;

[0064] Statement 2;

[0065] Statement 3;

[0066] …

[0067] Statement N

[0068] }

[0069] Optionally, the intermediate statement sequence may include multiple assignment statements and call statements, and the arrangement order of the intermediate statements is implemented according to the execution order of the control method in the initial logic diagram.

[0070] Step S303: Obtain intermediate code according to the intermediate statement sequence.

[0071] Each initial logic diagram corresponds to an intermediate statement sequence, so the intermediate statements in the intermediate statement sequence can be converted into intermediate codes. The conversion process is carried out sequentially according to the arrangement order of the intermediate statements. The intermediate code can be a table consisting of operators, operands, and expressions used to summarize the intermediate statements. Each row of the table has a corresponding sequence number. The entire table is outputted sequentially from multiple intermediate codes according to their arrangement order. Furthermore, the intermediate code can also be a pseudocode similar to assembly language, such as C-like language or structured text programming language (ST language) and other languages that can be expressed in text. Its common forms include reverse Polish notation, ternary form, quadruple form, and tree form.

[0072] Through steps S301 to S303, intermediate code is generated based on the intermediate statements. This intermediate code fully corresponds to the executable code ultimately generated from the intermediate statements, forming a mapping relationship between the intermediate code and the executable code. The intermediate code fully reflects the logic diagram compilation process. The generation of intermediate code visualizes the logic diagram compilation process, facilitating verification of the initial logic diagram compilation process. Furthermore, the verification results effectively avoid additional losses caused by logic diagram compilation errors.

[0073] In some embodiments, converting multiple logic elements in an initial logic diagram into corresponding intermediate statements based on the logic structure includes: first converting the logic elements into logic instruction statements, and then, based on the logic structure, assembling the logic instruction statements into intermediate statements. The specific content of the logic instruction statements may be represented differently in different types of logic diagrams. For example, in a function block diagram, the logic elements may be lines or function blocks. Function blocks may also include pins, which may be input pins (IN) or output pins (OUT). The input or output type may be data and / or events. Lines in the initial logic diagram may be converted into assignment statements, and function blocks in the initial logic diagram may be converted into call statements. An assignment statement is used to assign a specific value to a variable, while a call statement is used to transfer program execution to another code segment while saving necessary information so that execution returns to the call point after the called segment completes. Furthermore, in an instruction table, the logic elements may be instruction statements consisting of operators and operands. Each statement includes a command portion and a data portion. The command portion may specify a logic function, and the data portion may specify an address number and / or value of a function memory. The instruction statements are then converted into corresponding logic instruction statements based on the logic function. After obtaining the logic instruction statements, the logic instruction statements can be combined into intermediate statements according to the logical structure. In this embodiment, by converting the logic elements into intermediate statements according to the logical structure, the intermediate statements are structured data containing simple semantics, which provide a basis for the subsequent generation of intermediate code.

[0074] Figure 4 is a schematic diagram of the intermediate code according to an embodiment of the present application, such as Figure 4 As shown, in the case of multiple assignment statements and call statements, in the intermediate code, for each row of data, the first column from left to right is the sequence number, which is the same as the execution order of the corresponding intermediate statements. The second column is the operator, and columns 3-5 represent the operands. Furthermore, in actual operation, an additional column can be inserted after the fifth column to indicate the interpretation of the operands. Specifically, the meaning represented by each cell expression in this column can be found in the corresponding logical element in the logic diagram.

[0075] In some embodiments, determining whether the intermediate code is consistent with the initial logic diagram includes: converting the initial logic diagram into a first verification expression, converting the intermediate code into a second verification expression; and determining whether the intermediate code is consistent with the initial logic diagram based on a comparison result of the first verification expression and the second verification expression. The first verification expression and the second verification expression are formulas composed of letters, symbols and / or words, which can be generated by the compiler itself or a third-party tool. In this embodiment, automatic checking can be achieved by the compiler itself or a third-party tool, which greatly reduces the workload of manual checking and improves the efficiency of logic diagram compilation and checking.

[0076] In some embodiments, determining whether the intermediate code is consistent with the initial logic diagram can also be achieved by the following method: converting the intermediate code into a verification logic diagram, the language of the verification logic diagram being consistent with the language of the initial logic diagram; comparing the logical elements of the verification logic diagram with the logical elements of the initial logic diagram, and identifying the differences in the logical elements between the verification logic diagram and the initial logic diagram during the comparison process, wherein the differences are logical elements that cannot correspond to each other in the verification logic diagram and the initial logic diagram, generating difference information based on the differences in the logical elements, and further, the difference information indicates the difference in the meaning of the logical elements; and determining whether the intermediate code is consistent with the initial logic diagram based on the difference information. In this embodiment, the intermediate code is converted into a verification logic diagram, and the differences between the verification logic diagram and the initial logic diagram are actively identified to generate difference information. The difference information is then used to determine whether the differences are essentially different, thereby determining the correctness of the logic diagram compilation. At the same time, this embodiment can identify compilation problems caused by failures in the configuration editor or memory.

[0077] In some embodiments, before extracting logical elements from the initial logic diagram, the initial logic diagram is subjected to syntax checking and semantic parsing. Syntax checking can first verify the logic of the initial logic diagram itself, and semantic analysis can then lay the foundation for extracting logical elements, facilitating subsequent detection.

[0078] The present embodiment is described and illustrated below through preferred embodiments.

[0079] Figure 5 This is a flow chart of a logic diagram compilation detection method according to a preferred embodiment of the present application. Figure 5 As shown, the logic diagram compilation detection method includes the following steps:

[0080] Step S501, obtaining an initial logic diagram to be compiled;

[0081] Step S502: performing syntax checking and semantic parsing on the initial logic diagram, and extracting its logical elements and logical structure;

[0082] Step S503, converting the logical elements into an intermediate statement sequence according to the logical structure;

[0083] Step S504, obtaining intermediate code according to the intermediate statement sequence;

[0084] Step S505: converting the initial logic diagram into a first verification expression, converting the intermediate code into a second verification expression, and comparing the first verification expression with the second verification expression;

[0085] Step S506: judging whether the intermediate code is consistent with the initial logic diagram based on the comparison result of the first verification expression and the second verification expression.

[0086] Through steps S501 to S506, this embodiment visualizes the compilation process of the initial logic diagram using intermediate code. The intermediate code and the initial logic diagram are then converted into a first verification expression and a second verification expression, respectively, by a third party, including third-party software and / or third-party personnel, to avoid common cause failures. Finally, the two verification expressions are compared, and the comparison result is used to determine whether the intermediate code is consistent with the initial logic diagram. This automates the logic diagram compilation test and greatly improves the test efficiency.

[0087] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0088] In this embodiment, a logic diagram compilation and detection system is also provided. This system is used to implement the above-mentioned embodiments and preferred implementations. Details that have already been described will not be repeated. The terms "module," "unit," "subunit," etc. used below refer to a combination of software and / or hardware that implements a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0089] Figure 6 This is a structural block diagram of the logic diagram compilation and detection system of this embodiment. Figure 6 As shown, the device includes: an acquisition module 61, a conversion module 62 and a judgment module 63;

[0090] An acquisition module 61 is used to acquire an initial logic diagram to be compiled and extract the logic elements and logic structure of the initial logic diagram;

[0091] A conversion module 62 is used to convert the logic elements in the initial logic diagram into intermediate codes according to the logic structure;

[0092] The judgment module 63 is used to judge whether the intermediate code is consistent with the initial logic diagram based on the comparison result between the intermediate code and the initial logic diagram.

[0093] Through the above-described logic diagram compilation detection system, this embodiment uses an acquisition module 61 to extract logical elements from the initial logic diagram to be compiled. The conversion module 62 visualizes the logic diagram compilation process based on the logical elements and generates intermediate code. Finally, the judgment module 63 compares the intermediate code with the initial logic diagram and determines the compilation correctness of the logic diagram based on the comparison results. This prevents errors in the logic diagram compilation process and ensures the correct output of the control system. This solves the problem of the process control system failing to output correct results, which would cause additional losses, and effectively verifies the correctness of the logic diagram compilation process.

[0094] Furthermore, the conversion module 62 is also used to convert multiple logical elements in the initial logic diagram into corresponding intermediate statements according to the logical structure to obtain multiple intermediate statements; determine the intermediate statement sequence according to the multiple intermediate statements; and obtain intermediate codes according to the multiple intermediate statement sequences.

[0095] Furthermore, the conversion module 62 is further configured to convert each of the initial logic elements into a corresponding logic instruction statement; and to group the logic instruction statements into intermediate statements according to the logic structure.

[0096] Furthermore, the judgment module 63 is also used to convert the initial logic diagram into a first verification expression and convert the intermediate code into a second verification expression; and judge whether the intermediate code is consistent with the initial logic diagram based on the comparison result of the first verification expression and the second verification expression.

[0097] Furthermore, the judgment module 63 is also used to convert the intermediate code into a verification logic diagram, and the language of the verification logic diagram is consistent with the language of the initial logic diagram; the logical elements of the verification logic diagram are compared with the logical elements of the initial logic diagram, and whether the intermediate code is consistent with the initial logic diagram is determined based on the comparison results.

[0098] Furthermore, the judgment module 63 is also used to identify the difference points of logic elements between the verification logic diagram and the initial logic diagram, generate difference information according to the difference points of logic elements, and judge whether the intermediate code is consistent with the initial logic diagram according to the difference information.

[0099] Furthermore, the acquisition module 61 is also used to perform syntax checking and semantic analysis on the initial logic diagram.

[0100] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0101] This embodiment further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0102] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0103] Optionally, in this embodiment, the processor may be configured to execute the following steps through a computer program:

[0104] S1, obtaining an initial logic diagram to be compiled and extracting the logic elements and logic structure of the initial logic diagram;

[0105] S2, converts the logic elements in the initial logic diagram into intermediate codes according to the logic structure;

[0106] S3, based on the comparison result between the intermediate code and the initial logic diagram, determine whether the intermediate code is consistent with the initial logic diagram.

[0107] It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0108] In addition, in conjunction with the logic diagram compilation detection method provided in the above embodiments, a storage medium may be provided in this embodiment to implement the method. The storage medium stores a computer program that, when executed by a processor, implements any of the logic diagram compilation detection methods in the above embodiments.

[0109] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0110] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

[0111] The term "embodiment" as used in this application refers to specific features, structures, or characteristics described in conjunction with the embodiment that can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily mean that the embodiment is the same, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is understood, either explicitly or implicitly, by those skilled in the art that the embodiments described in this application can be combined with other embodiments when there is no conflict.

[0112] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A logic diagram compilation detection method, characterized in that: include: Obtaining an initial logic diagram to be compiled and extracting logic elements and a logic structure of the initial logic diagram; According to the logic structure, converting the logic elements in the initial logic diagram into intermediate codes; According to the comparison result between the intermediate code and the initial logic diagram, determining whether the intermediate code is consistent with the initial logic diagram; The converting of the logic elements in the initial logic diagram into intermediate codes according to the logic structure includes: According to the logic structure, the plurality of logic elements in the initial logic diagram are converted into corresponding intermediate statements to obtain a plurality of intermediate statements; each of the intermediate statements corresponds to an operator type; Determining an intermediate statement sequence based on the plurality of intermediate statements; the intermediate statement sequence is generated by arranging the intermediate statements of different operator types; Obtaining the intermediate code according to the plurality of intermediate statement sequences; Converting the plurality of logic elements in the initial logic diagram into corresponding intermediate statements according to the logic structure includes: Convert each of the initial logic elements into a corresponding logic instruction statement; According to the logic structure, the logic instruction statements are combined into intermediate statements; The initial logic diagram includes a functional module diagram and an instruction table; When the initial logic diagram is a function module diagram, the types of the logic elements are lines and function blocks; converting each of the initial logic elements into a corresponding logic instruction statement includes: Converting the lines in the initial logic diagram into assignment statements, and converting the function blocks in the initial logic diagram into call statements; When the initial logic diagram is an instruction table, the logic elements are instruction statements consisting of operators and operands, and each instruction statement includes a command portion and a data portion; converting each of the initial logic elements into a corresponding logic instruction statement includes: The instruction statements are converted into corresponding logical instruction statements according to the logical functions.

2. The logic diagram compilation detection method according to claim 1, characterized in that: The determining, based on a comparison result between the intermediate code and the initial logic diagram, whether the intermediate code is consistent with the initial logic diagram comprises: Converting the initial logic diagram into a first verification expression, and converting the intermediate code into a second verification expression; Whether the intermediate code is consistent with the initial logic diagram is determined according to the comparison result of the first verification expression and the second verification expression.

3. The logic diagram compilation detection method according to claim 1, characterized in that: The determining, based on a comparison result between the intermediate code and the initial logic diagram, whether the intermediate code is consistent with the initial logic diagram comprises: Converting the intermediate code into a verification logic diagram, wherein the language of the verification logic diagram is consistent with the language of the initial logic diagram; The logical elements of the verification logic diagram are compared with the logical elements of the initial logic diagram, and whether the intermediate code is consistent with the initial logic diagram is determined based on the comparison result.

4. The logic diagram compilation detection method according to claim 3, characterized in that: The determining whether the intermediate code is consistent with the initial logic diagram according to the comparison result further includes: Identifying differences in logic elements between the verification logic diagram and the initial logic diagram, and generating difference information based on the differences in logic elements; Whether the intermediate code is consistent with the initial logic diagram is determined according to the difference information.

5. The logic diagram compilation detection method according to claim 1, characterized in that: Before extracting the logic elements of the initial logic diagram, the method includes: Performing syntax checking and semantic parsing on the initial logic diagram.

6. A logic diagram compilation detection system, characterized in that: include: Acquisition module, conversion module and judgment module; The acquisition module is used to acquire the initial logic diagram to be compiled and extract the logic elements and logic structure of the initial logic diagram; The conversion module is used to convert the logical elements in the initial logic diagram into intermediate codes according to the logical structure; The judgment module is used to judge whether the intermediate code is consistent with the initial logic diagram based on the comparison result between the intermediate code and the initial logic diagram; The conversion module is further configured to convert the plurality of logic elements in the initial logic diagram into corresponding intermediate statements according to the logic structure, thereby obtaining a plurality of intermediate statements; each intermediate statement corresponds to an operator type; determining an intermediate statement sequence according to the plurality of intermediate statements; The intermediate statement sequence is generated by arranging the intermediate statements of different operator types; Obtaining the intermediate code according to the plurality of intermediate statement sequences; The conversion module is further configured to convert each of the initial logic elements into a corresponding logic instruction statement; According to the logic structure, the logic instruction statements are combined into intermediate statements; Wherein, the initial logic diagram includes a functional module diagram and an instruction table; When the initial logic diagram is a function module diagram, the types of the logic elements are lines and function blocks; converting each of the initial logic elements into a corresponding logic instruction statement includes: Converting the lines in the initial logic diagram into assignment statements, and converting the function blocks in the initial logic diagram into call statements; When the initial logic diagram is an instruction table, the logic elements are instruction statements consisting of operators and operands, and each instruction statement includes a command portion and a data portion; converting each of the initial logic elements into a corresponding logic instruction statement includes: The instruction statements are converted into corresponding logical instruction statements according to the logical functions.

7. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to execute the logic diagram compilation detection method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of logic diagram compilation detection according to any one of claims 1 to 5 are implemented.

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