Semiconductor device

Abstract

The present disclosure provides a semiconductor device in which a portion of a plurality of through-holes formed in a non-transistor region is a floating via having a floating potential.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-152505, filed on September 11, 2020, the contents of which are incorporated herein by reference. Background Technology

[0003] The present invention relates to a semiconductor device, for example, a technique effectively applicable to a semiconductor device having through-holes(s).

[0004] Non-patent document 1 (Kobe Steel Technical Report, Vol. 52, No. 2 (September 2002)) discloses a technology related to plasma charging. Summary of the Invention

[0005] Semiconductor devices used in artificial intelligence and data centers house neural networks such as large-scale product and computation circuits and require real-time processing of massive amounts of data. In other words, semiconductor devices used in AI and data centers require wideband, high-capacity memory devices while minimizing power consumption due to the need to store and update large amounts of image data and rapidly store and update the weight data of large-capacity neural networks. Therefore, research is underway on semiconductor devices in which semiconductor chips, such as wideband memory, are three-dimensionally stacked via (multiple) through-holes.

[0006] However, when through-holes are formed on semiconductor chips for stacking, damage to these through-holes due to plasma charging becomes a problem. This damage introduces defects into the semiconductor chip, leading to reduced reliability and manufacturing yield of the semiconductor device. Therefore, to improve the reliability and manufacturing yield of semiconductor devices, it is desirable to suppress through-hole damage caused by plasma charging.

[0007] In one embodiment, some of the through-holes formed in the non-transistor region are through-holes with a floating potential.

[0008] According to one embodiment, the reliability of semiconductor devices can be improved. Attached Figure Description

[0009] Figure 1 It is a plan view showing a schematic configuration of semiconductor devices;

[0010] Figure 2 It is along Figure 1 A cross-sectional view taken from line AA;

[0011] Figure 3This is a diagram illustrating an example of the mechanism by which the destruction of a through-hole occurs through charging by plasma generated in the formation of the through-hole;

[0012] Figure 4 is a photograph showing the through-hole in which dielectric breakdown has occurred;

[0013] Figure 5 This is a schematic diagram illustrating the state of a short-circuit fault occurring in a through-hole;

[0014] Figure 6 These are diagrams used to illustrate related technologies;

[0015] Figure 7 The diagram schematically illustrates "active vias" and "floating vias";

[0016] Figure 8 This diagram illustrates the qualitative mechanism by which "floating vias" are more likely to cause dielectric breakdown due to plasma charging compared to "active vias".

[0017] Figure 9 This is a diagram used to illustrate the spatial inhomogeneity of the plasma occurring at that location;

[0018] Figure 10 This is a schematic diagram showing the area near the boundary between the transistor region and the non-transistor region formed on the base chip;

[0019] Figure 11 It is along Figure 10 A cross-sectional view taken from line AA;

[0020] Figure 12 This is a schematic diagram showing the area near the boundary between the transistor region and the non-transistor region formed on the base chip;

[0021] Figure 13 It is along Figure 12 A cross-sectional view taken from line AA;

[0022] Figure 14 This diagram illustrates why dielectric breakdown is prone to occur due to floating vias arranged in the protrusions of the boundary line.

[0023] Figure 15 It is a schematic diagram showing the vicinity of the first boundary region between the first transistor region and the non-transistor region formed on the base chip and the vicinity of the second boundary region between the second transistor region and the non-transistor region formed on the base chip;

[0024] Figure 16 It is along Figure 15 A cross-sectional view of line AA; and

[0025] Figure 17 This is a diagram used to illustrate the design in the application example. Detailed Implementation

[0026] In the embodiments described below, for convenience, the invention will be described in multiple sections or embodiments as needed. However, unless otherwise stated, these sections or embodiments are not unrelated to each other, and one section or embodiment relates to all or part of another section or embodiment as an example of modification, detail, or supplementary description thereof.

[0027] Furthermore, in the embodiments described below, when referring to the number of elements (including the number of items, values, quantities, ranges, etc.), the number of elements is not limited to a specific number, unless otherwise stated or except where the number is obviously limited to a specific number in principle, and numbers larger or smaller than a specific number also apply.

[0028] Furthermore, in the embodiments described below, it goes without saying that components (including element steps) are not always essential, unless otherwise stated or except where the component is obviously essential in principle.

[0029] Similarly, in the following embodiments, when referring to the shape of components, their positional relationships, etc., this includes substantially similar and similar shapes, unless otherwise stated or except where such exclusion is clearly conceivable in principle. The same applies to the numerical values ​​and ranges described above.

[0030] Throughout the accompanying drawings used to describe the embodiments, components with the same function are represented by the same reference numerals, and repeated descriptions thereof will be omitted. Incidentally, in the drawings used in the following embodiments, section lines are used even in plan views to facilitate reading of the drawings.

[0031] (Semiconductor device configuration)

[0032] The technical concept of this embodiment is applicable to, for example, semiconductor devices that house a central processing unit (CPU) composed of logic ICs and also, similarly, semiconductor devices used in artificial intelligence or data centers that house wideband, high-capacity memory devices.

[0033] Figure 1 It is a plan view showing a schematic configuration of semiconductor devices.

[0034] exist Figure 1In this design, the semiconductor device 1 has, for example, a rectangular wiring substrate 10. Mounted on the wiring substrate 10 are: a semiconductor chip 11, in which a central processing unit composed of logic ICs is formed; and a stacked chip structure 12, in which multiple memory chips are stacked in three dimensions. This semiconductor device 1 will be put into practical use as a high-performance memory product for next-generation network systems and artificial intelligence / data center accelerators.

[0035] Figure 2 It is along Figure 1 The cross-sectional view taken from line AA.

[0036] Focus Figure 2 The semiconductor device 1 includes a stacked chip structure 12, comprising a base chip 13 disposed in the lowest layer, and a plurality of memory chips 14 stacked and disposed on the base chip 13. Such a semiconductor device 1 has a stacked chip structure 12 to realize a high-capacity memory device. The respective chips constituting the stacked chip structure 12 are then electrically connected via through-vias (TSVs). That is, through-vias (TSVs) are formed on each chip of the stacked chip structure 12, and the circuitry formed on the respective chips is electrically connected via through-vias (TSVs). Therefore, according to the semiconductor device 1, a three-dimensional memory device is realized through the stacked chip structure 12. The advantage of the semiconductor device 1 having such a stacked chip structure 12 is that a high-capacity memory device can be mounted without increasing the planar dimensions of the semiconductor device 1.

[0037] Formed in the base chip 13, which is disposed on the lowest layer of the stacked chip structure 12, are: an integrated circuit formed on the base chip 13 itself; a first power supply wiring for providing a first power supply potential to the integrated circuit; and a second power supply wiring for providing a second power supply potential not only to the ground wiring for providing a ground potential but also to the integrated circuit formed on the stacked memory chip 14. This is because the base chip 13 is disposed on the lowest layer of the stacked chip structure 12 such that the second power supply potential is provided to the memory chip 14 disposed above the via vias via the base chip 13. That is, the second power supply wiring formed on the base chip 13 is connected to the through-via TSV formed on the base chip 13, and the second power supply potential is provided to the integrated circuit formed on the memory chip 14 via the through-via TSV. Furthermore, the through-via TSV is also formed in the memory chip 14, and multiple memory chips 14 are electrically connected to each other via the through-via TSV. Therefore, through-hole TSVs are essential for electrically connecting the corresponding chips that constitute the stacked chip structure 12, and from the viewpoint of improving the reliability of the semiconductor device 1 including the stacked chip structure 12, it is very important to improve the reliability of the through-hole TSVs.

[0038] In particular, from the viewpoint of improving the manufacturing yield of semiconductor device 1, it is important to improve the reliability of the through-vias (TSVs) formed in the base chip 13. This is because, in semiconductor device 1, the stacked chip structure 12 is manufactured by mounting multiple memory chips 14 on the base chip 13. Therefore, if the manufacturing yield of the base chip 13 decreases, multiple defect-free memory chips 14 mounted on the base chip 13, which is a defective product, are wasted, thus leading to a significant increase in manufacturing costs.

[0039] Therefore, a technical concept regarding through-hole TSVs will be described, with particular focus on the base chip 13. However, the technical concept in this embodiment is not limited to through-hole TSVs formed in the base chip 13, and can also be widely applied to through-hole TSVs formed, for example, on the memory chip 14.

[0040] (Aspects for improvement in the reliability of through-holes)

[0041] Next, there is room for improvement in the reliability of through-holes. In particular, by focusing on plasma charging that occurs during the formation of (multiple) through-holes, as a phenomenon affecting the reliability of through-holes, the room for improvement that becomes apparent in the formation of through-holes will be described.

[0042] Figure 3 This is a diagram illustrating an example of the mechanism by which a through-hole is destroyed by plasma charging generated in the formation of the through-hole. Incidentally, in this specification, the final state in which conductive material is embedded in the through-hole is referred to as a "through-hole" and is used separately from the term "through-hole".

[0043] exist Figure 3 In, for example, on the positive surface side of the substrate 100 made of silicon ( Figure 3 A diffusion layer 101 and a silicon oxide film 102, which serves as an interlayer insulating layer, are formed on the lower part of the substrate 100. Meanwhile, on the back surface side of the substrate 100 (… Figure 3 A silicon nitride film 103 is formed on the upper part of the substrate 100. Through-holes OP are formed in such a substrate 100.

[0044] The through-hole OP is formed using techniques such as photolithography and etching. Specifically, after applying a photoresist film to the back surface side of the substrate 100, the photoresist film is exposed and developed to pattern it. Then, the substrate 100 is etched using the patterned photoresist film as a mask. Thus, the through-hole OP is formed in the substrate 100. Subsequently, the patterned photoresist film is removed. This step of removing the photoresist film is called the ashing step.

[0045] Here, for example, such as Figure 3 As shown, when the aspect ratio of the through-hole OP is high, due to the difference in spatial momentum between electrons and ions (positive ions), and the obstruction of electron inflow into the through-hole OP, electrons are likely to adhere to the upper edge of the through-hole OP. Simultaneously, positive ions and free radicals are selectively accumulated on the bottom and side surfaces of the through-hole OP. Specifically, during the ashing step to remove the resist film, positive ions and free radicals are easily captured on the inner wall of the through-hole OP as the product (polymer) reattaches; the product is generated through the decomposition of the resist film. As a result, the balance of electrons and ions around the through-hole OP is disrupted, inducing plasma charging. This phenomenon is called the "electron shielding effect."

[0046] When this "electron shielding effect" occurs, a high electric field is generated between the positive ions accumulated within the through-hole OP and the electrons adhering to the upper edge of the through-hole OP (see [link]). Figure 3 (The arrow in the image). Then, due to the high electric field caused by plasma charging, dielectric breakdown occurs in the inner wall of the through-hole OP. For example, Figure 4A and Figure 4B Each of these images shows a through-hole where dielectric breakdown has occurred due to plasma charging.

[0047] Then, when a through-hole is formed by embedding conductive material inside the through-hole OP in which dielectric breakdown has already occurred, a short circuit fault occurs at the location where dielectric breakdown has already occurred.

[0048] Specifically, Figure 5 This diagram schematically illustrates the state of a short-circuit fault occurring in a through-hole.

[0049] Figure 5 The diagram shows power supply wiring VDDM1 and ground wiring VSS1 formed on a base chip, and power supply wiring VDDM2 and ground wiring VSS2 formed on a memory chip mounted on the base chip.

[0050] The power supply wiring VDDM1 formed on the base chip is a wiring used to provide a second power supply potential to the circuit formed on the memory chip, and is electrically connected to the power supply wiring VDDM2 formed on the memory chip via a through-hole TSV1.

[0051] In addition, the ground wiring VSS1 formed on the base chip is a wiring used to provide ground potential, and is electrically connected to the ground wiring VSS2 formed on the memory chip via the through-hole TSV2.

[0052] Incidentally, in addition to the power supply wiring VDDM1 and the ground wiring VSS1, a power supply wiring VDDL is formed on the base chip to provide a first power supply potential that is different from the second power supply potential to the circuit formed in the base chip itself (on top).

[0053] exist Figure 5 For example, suppose a dielectric breakdown due to plasma charging occurs in a through-hole TSV1 that connects a power supply wiring VDDM1 formed on a base chip to a power supply wiring VDDM2 formed on a memory chip. In this case, a short-circuit fault occurs at the location where the dielectric breakdown occurs, and between the substrate (ground potential) surrounding the through-hole TSV1 and the second power supply potential applied to the internal conductor of the through-hole TSV1. As a result, the circuitry formed on the memory chip may be damaged.

[0054] Meanwhile, for example, suppose a dielectric breakdown due to plasma charging occurs in a through-hole TSV2 that connects a ground wiring VSS1 formed on a base chip and a ground wiring VSS2 formed on a memory chip. In this case, the substrate (ground potential) surrounding the through-hole TSV2 and the internal conductor of the through-hole TSV2 cause conduction at the location where dielectric breakdown occurs. However, since the potential of the substrate surrounding the through-hole TSV2 and the potential of the internal conductor of the through-hole TSV2 are both ground potentials, a short-circuit fault will not occur.

[0055] Therefore, in a through-hole TSV2 with an applied ground potential, even if dielectric breakdown occurs in the through-hole OP, a short-circuit fault will not occur at the site of dielectric breakdown. Conversely, in a through-hole TSV1 with an applied potential different from the ground potential, if dielectric breakdown occurs in the through-hole OP, a short-circuit fault will occur between the substrate (ground potential) surrounding the through-hole TSV2 and the potential applied to the internal conductor of the through-hole TSV2. Thus, it is understandable that it is particularly necessary to suppress dielectric breakdown in through-hole TSV2 with an applied potential different from the ground potential.

[0056] As described above, for example, when plasma charging occurs in the via formed by plasma charging, dielectric breakdown occurs on the inner wall of the via due to the "electron shielding effect," and thus, short-circuit faults may occur in the via through which internal conductors are embedded. Therefore, for example, to improve the manufacturing yield of the substrate chip, it is necessary to improve the reliability of the vias. Specifically, it is important to prevent dielectric breakdown of the vias formed in the substrate chip. In this regard, related techniques described below exist to reduce dielectric breakdown of vias due to plasma charging.

[0057] (Related technical specifications)

[0058] The “related technologies” mentioned in this specification are not known technologies, but rather problematic technologies discovered by the inventors of this invention, and are technologies that serve as the premise of this invention.

[0059] Figure 6 It is a diagram used to illustrate the relevant technology.

[0060] exist Figure 6 In this design, a protection circuit PC is disposed between the power supply wiring VDDM1 and the ground wiring VSS1, which are formed on the base chip. This protection circuit PC has the function of leaking charge accumulation generated in the via OP. As a result, in related technologies with the protection circuit PC, plasma charging in the via OP can be suppressed, thereby preventing dielectric breakdown in the via OP. According to related technologies, this makes it possible to suppress short-circuit faults in the via TSV1 caused by plasma charging.

[0061] (Aspects for improvement in related technologies)

[0062] However, if the protection circuit PC is mounted on the base chip, the chip area of ​​the base chip increases. Specifically, the protection circuit PC mounted on the base chip is a protection circuit related to the memory chip-specific power supply used in the circuitry formed on the memory chip. That is, as... Figure 6 As shown, a protection circuit PC is provided to prevent short-circuit faults connected to a through-hole TSV1 of a power supply wiring VDDM1, which provides a second power supply potential to the memory chip. This means that an additional protection circuit PC must be formed on the base chip, which is not initially intended to protect the circuit(s) formed on the base chip itself. In other words, according to related technologies, a protection circuit PC not directly related to the base chip must be provided, making the increase in chip area of ​​the base chip significant. This represents an area for improvement in related technologies.

[0063] Meanwhile, if the protection circuit PC is not set on the base chip, the short circuit fault through the via TSV1 caused by plasma charging becomes obvious.

[0064] Therefore, in this embodiment, without the presence of a protection circuit PC, a design (invention) is provided to prevent short-circuit faults in a through-hole TSV1 connected to a power supply wiring VDDM1 that provides a second power supply potential to a memory chip. The technical concept of this embodiment, in which such a design is provided, will be described below.

[0065] (Basic idea in the embodiments)

[0066] The basic idea of ​​this embodiment is to protect other vias connected to the circuit(s) from dielectric breakdown by intentionally providing vias that cause dielectric breakdown due to plasma charging. In other words, the basic idea of ​​this embodiment is to prevent dielectric breakdown of other vias connected to the circuit by intentionally providing vias that do not cause short-circuit faults even if dielectric breakdown occurs, and by causing dielectric breakdown due to plasma charging in these vias. According to this basic idea, even if plasma charging occurs, dielectric breakdown is suppressed in the vias connected to the circuit, and therefore, short-circuit faults in the vias connected to the circuit are prevented. According to this basic idea, this makes it possible to improve the reliability of semiconductor devices including vias.

[0067] Specifically, in this basic idea, in addition to the through-holes connected to the circuit, there are intentionally provided through-holes not connected to the circuit and having a floating potential, and dielectric breakdown is caused by the through-holes with the floating potential. Therefore, in this basic idea, due to the intentional dielectric breakdown in the through-holes with the floating potential, electron and positive ion bonding occurs. This means that charge imbalance is eliminated and the high electric field causing dielectric breakdown is reduced, thereby protecting other through-holes connected to the circuit from dielectric breakdown. Thus, even if dielectric breakdown occurs in a through-hole with a floating potential that is not connected to the circuit, a short-circuit fault will not occur in the circuit, and therefore, the circuit formed in the semiconductor device can be protected. For example, even if dielectric breakdown occurs in a through-hole with a floating potential, the through-hole with the floating potential is only electrically connected to the substrate (ground potential) around the through-hole, and therefore no short-circuit fault will occur between a potential different from the ground potential and the ground potential. Therefore, based on the basic idea of ​​this embodiment, short-circuit faults in circuits formed in semiconductor devices can be effectively suppressed without the need for protection circuits as described in the related technologies above. In other words, this basic idea can be considered an excellent technical concept because it can suppress short-circuit faults caused by dielectric breakdown through vias without increasing the chip size of the base chip.

[0068] Here, the definition of through holes in this specification will be described.

[0069] First, the vias in this specification are categorized as "active vias," "grand vias," and "floating vias." "Active via" refers to a via that is connected to a circuit in the completed state of a semiconductor device, and is used as a general term to include, for example, vias configured to apply a power supply potential or vias configured to apply a ground potential. However, even if a via has a floating potential and is connected to a circuit in the completed state of the semiconductor device, it is still included in "active vias." Specifically, some vias configured to allow a ground potential to be applied are called "ground vias."

[0070] Meanwhile, a "floating via" refers to a through-hole that is not connected to a circuit even when the semiconductor device is in its completed state and is configured to have a floating potential. In addition, because dielectric breakdown occurs in "floating vias", "floating vias" that are conductive to the substrate (ground potential) around the "floating via" are called "damaged vias" and are distinguished from "ground vias".

[0071] If the basic idea of ​​this embodiment is restated based on the above definition, the basic idea of ​​this embodiment can be described as follows: Other active vias connected to the circuit are protected from dielectric breakdown by intentionally providing "floating vias" that cause dielectric breakdown due to plasma charging. Then, in a semiconductor device employing the basic idea of ​​this embodiment, at least one of "floating vias" and "damaged vias" is included in a plurality of through-vias. That is, in a semiconductor device embodying this basic idea, any of the following aspects are achieved: all "floating vias" are dielectrically broken down and become "damaged vias"; some "floating vias" are dielectrically broken down and "floating vias" and "damaged vias" coexist; and all "floating vias" are retained without causing dielectric breakdown.

[0072] The basic idea of ​​this embodiment will be explained below with reference to the accompanying drawings.

[0073] Figure 7 This is a schematic diagram illustrating "active vias" and "floating vias".

[0074] exist Figure 7In this circuit, power supply wiring VDDM1 formed on the base chip and power supply wiring VDDM2 formed on the memory chip are connected via via TSV1. Since power supply wiring VDDM2 on the memory chip functions to provide a second power supply potential to the integrated circuit (memory circuit, etc.) formed on the memory chip, it is led out to connect to the circuit. Therefore, via TSV1 connecting power supply wiring VDDM1 and power supply wiring VDDM2 is also connected to the circuit. Thus, via TSV1 connecting power supply wiring VDDM1 and power supply wiring VDDM2 is called an "active via". Similarly, ground wiring VSS1 formed on the base chip and ground wiring VSS2 formed on the memory chip are connected via via TSV2. Since ground wiring VSS1 and ground wiring VSS2 each function to provide a ground potential to the integrated circuit, via TSV2 connecting ground wiring VSS1 and ground wiring VSS2 is also connected to the circuit. Therefore, the via TSV2 becomes an "active via", and in particular, since a grounding potential is applied, the via TSV2 becomes a "grounding via" within the "active via".

[0075] At the same time, Figure 7 In this embodiment, the via TSV3 is not formed in the memory chip or circuit (formed on the base chip) and has a floating potential, thus becoming a "floating via". The basic idea here is to provide a "floating via" that intentionally causes dielectric breakdown to protect "active vias" from dielectric breakdown caused by plasma charging. However, to embody this idea, "floating vias" need to be more susceptible to dielectric breakdown than "active vias".

[0076] In this regard, to make "floating vias" easier to break down than "active vias," it is important that "floating vias" are not connected to the circuit in the completed state of the semiconductor device, except in the unfinished state, and have a floating potential. In other words, because of the floating potential, "floating vias" are more easily dielectrically broken down than "active vias."

[0077] The qualitative mechanism by which floating vias are more likely to cause dielectric breakdown due to plasma charging than active vias will be explained below.

[0078] Figure 8 This diagram illustrates the qualitative mechanism by which "floating vias" are more likely to cause dielectric breakdown due to plasma charging than "active vias".

[0079] Figure 8The diagram shows a through-hole OP1 for an active via AV and a through-hole OP2 for a floating via FV. Here, the active via AV is electrically connected to the circuit, thus resulting in a connection to a long-extending wiring WL, for example, as... Figure 8 As shown. Meanwhile, the floating via FV is not electrically connected to the circuit and therefore not connected to the long-extending wiring. Due to this difference, the through-hole OP2 of the floating via FV is more prone to dielectric breakdown than the through-hole OP1 of the active via AV.

[0080] For example, such as Figure 8 As shown, in the through-hole OP1 forming the active via AV, positive ions accumulate on the inner wall of the through-hole OP1 due to the "electron shielding effect." However, the through-hole OP1 of the active via AV is connected to a long-extending wiring WL, preventing positive ions from concentrating on the inner wall of the through-hole OP1 and allowing them to diffuse into the wiring WL. Therefore, the density of positive ions accumulated on the inner wall of the through-hole OP1 of the active via AV is reduced. This means that a high electric field is unlikely to be generated inside the through-hole OP1, thus making dielectric breakdown due to plasma charging unlikely to occur in the through-hole OP1 of the active via AV.

[0081] In contrast, due to the "electron shielding effect," positive ions also accumulate on the inner wall of the floating via FV. Here, the through-hole OP2 of the floating via FV is not electrically connected to the circuit. That is, the through-hole OP2 of the floating via FV extends a considerable distance or is not connected to the wiring. Consequently, the positive ions accumulated in the inner wall of the through-hole OP2 of the floating via FV cannot diffuse and remain on the inner wall of the through-hole OP2. Therefore, the positive ion density in the through-hole OP2 of the floating via FV increases. This means that a high electric field is easily generated inside the through-hole OP2, making dielectric breakdown due to plasma charging more likely to occur in the through-hole OP2 of the floating via FV. Through the above qualitative mechanism, dielectric breakdown due to plasma charging is more likely to occur in the through-hole OP2 of the floating via FV compared to the through-hole OP1 of the active via AV.

[0082] In this way, based on the basic idea of ​​this embodiment, the intentional provision of a "floating via" that causes dielectric breakdown due to plasma charging can protect other "active vias" connected to the circuit from dielectric breakdown.

[0083] Specifically, the "floating via" provided in this basic concept has two important technical implications. First, a "floating via" is not connected to wiring used for circuit connection to have a floating potential, and therefore has a higher electric field density compared to an "active via," making it more prone to dielectric breakdown. Second, even if dielectric breakdown occurs in a "floating via," a short circuit fault between different potentials will not occur.

[0084] In this basic concept, given the two technical advantages of "floating vias," "floating vias" are designed for intentional dielectric breakdown and protect "active vias" that may cause short-circuit faults after dielectric breakdown. Based on this concept, circuits formed in semiconductor devices can be protected from short-circuit faults caused by plasma charging, and thus, the reliability of semiconductor devices can be improved.

[0085] (The inventor's new discovery)

[0086] Next, the inventor's new discovery will be described.

[0087] One reason for plasma charging is the "electron shielding effect," and another reason is the known spatial inhomogeneity of plasma. However, the location of this spatial inhomogeneity has not yet been investigated. Through dedicated research, the inventors have made the following new findings regarding the spatial inhomogeneity of plasma, which will be explained below.

[0088] Figure 9 It is a diagram used to illustrate the spatial inhomogeneities that occur in plasma.

[0089] For example, Figure 9 A magnified plan view of a portion of the base chip region is shown. Figure 9 In this context, the transistor region TR is, for example, a region in which an integrated circuit, including a field-effect transistor, is formed. Specifically, an active diffusion layer, serving as the source and drain regions for the field-effect transistor, is formed in the transistor region TR.

[0090] Meanwhile, the non-transistor region (NTR) is, for example, a region in which no integrated circuit, including field-effect transistors, is formed. In this NTR, since no field-effect transistors are formed, there is no need to form active diffusion layers to serve as source and drain regions. However, from the viewpoint of improving the microfabrication precision of the entire substrate chip, diffusion layers are also formed in the NTR. However, the diffusion layer formed in the NTR does not serve as a source and drain region, therefore it is called a passive diffusion layer. Furthermore, multiple through-holes (TSVs) are formed in the NTR.

[0091] The inventors have made a novel discovery: in the boundary region BR between the transistor region TR and the non-transistor region NTR, the spatial inhomogeneity of the plasma becomes significant, such as... Figure 9 As shown. For example, the arrangement density of the active diffusion layer formed in the transistor region TR is different from the arrangement density of the passive diffusion layer formed in the non-transistor region NTR, and no through-hole TSV is formed in the transistor region TR. Therefore, the arrangement density of the diffusion layer and the arrangement density of the through-hole TSV are different in the transistor region TR and the non-transistor region NTR. Therefore, the inventors have newly discovered that due to the difference between the arrangement density of the diffusion layer and the arrangement density of the through-hole TSV, a non-uniformity occurs between the plasma charge density accumulated in the transistor region TR and the plasma charge density accumulated in the non-transistor region NTR. That is, in the boundary region BR between the transistor region TR and the non-transistor region NTR, the spatial non-uniformity of the plasma due to the difference between the arrangement density of the diffusion layer and the arrangement density of the through-hole TSV becomes significant. Therefore, based on the spatial non-uniformity of the plasma, a high electric field is generated in the boundary region BR. Therefore, the through-hole TSV, which is arranged closest to the boundary region BR, is prone to dielectric breakdown not only due to the "electron shielding effect" but also due to the spatial non-uniformity of the plasma.

[0092] By combining these findings with the basic ideas in this embodiment, the following specific aspects have been achieved, and these specific aspects will be described subsequently.

[0093] (First specific aspect)

[0094] Figure 10 This diagram schematically illustrates the area near the boundary between the transistor region TR and the non-transistor region NTR formed on a base chip. The base chip is, for example, a semiconductor chip arranged in the lowest layer among the multiple semiconductor chips constituting the stacked structure in a semiconductor device having a stacked structure in which multiple semiconductor chips are stacked. Figure 10 As shown, such a base chip contains a transistor region TR in which field-effect transistors are formed and a non-transistor region NTR in which no field-effect transistors are formed. Then, as... Figure 10As shown, no through-vias are formed in the transistor region TR, but multiple through-vias TSVs are formed in the non-transistor region NTR. Among the multiple through-vias TSVs formed in the non-transistor region NTR, there are active vias AV and floating vias FV. At this time, at least a portion of the through-via TSV located closest to the boundary line BL in the plan view becomes a floating via FV, which lies between the transistor region TR and the non-transistor region NTR.

[0095] Next, Figure 11 It is along Figure 10 The cross-sectional view taken from line AA.

[0096] like Figure 11 As shown, on the front surface side of the semiconductor substrate 200 having a front surface 200a and a back surface 200b, diffusion layers are formed in both the transistor region TR and the non-transistor region NTR. The diffusion layer formed in the transistor region TR is an active diffusion layer 201 used as the source and drain regions of a field-effect transistor. Meanwhile, the diffusion layer formed in the non-transistor region NTR is a passive diffusion layer 202 not used as the source and drain regions. Here, the arrangement density of the active diffusion layer 201 formed in the transistor region TR is higher than the arrangement density of the passive diffusion layer 202 formed in the non-transistor region NTR.

[0097] An active diffusion layer 201 is connected to the first layer wiring L1 and the second layer wiring L2. In the transistor region TR, an integrated circuit is configured by electrically connecting a field-effect transistor, the first layer wiring L1, and the second layer wiring L2. That is, the integrated circuit is formed in the transistor region TR. Simultaneously, in the non-transistor region NTR, an active via AV and a floating via FV are formed, and the active via AV is connected to, for example, the first layer wiring L1 and the second layer wiring L2. The active via AV is electrically connected to the integrated circuit formed in the transistor region TR via the first layer wiring L1 and the second layer wiring L2. Conversely, the floating via FV is not electrically connected to the first layer wiring L1 and the second layer wiring L2. That is, the floating via FV is not connected to the circuit and has a floating potential.

[0098] Although not shown, for example, a memory chip is mounted on a base chip configured in this manner. Therefore, Figure 11 The active via AV shown is electrically connected to the memory chip. Specifically, the active via AV serves as a power supply path to be provided to the circuitry formed within the memory chip.

[0099] In this embodiment, no protection circuit is formed on the base chip, which is configured to suppress damage to the active via AV due to plasma charging. This is because, in this embodiment, a floating via FV is provided that has the function of suppressing damage to the active via AV due to plasma charging. In particular, the floating via FV is arranged at a location that is more prone to damage due to plasma charging compared to the location of the active via AV. Specifically, as... Figure 11 As shown in the plan view, at least one of the multiple floating vias FV is positioned closest to the boundary line BL, which lies between the transistor region TR and the non-transistor region NTR.

[0100] (Characteristics of the first specific aspect)

[0101] The feature points of the first specific aspect will then be described.

[0102] For example, Figure 10 and Figure 11 As shown, a key feature of the first aspect is that at least one of the plurality of through-vias TSVs arranged closest to the boundary line BL, which lies between the transistor region TR and the non-transistor region NTR, is a floating via FV. According to the first aspect, this allows for the protection of active vias AV formed in the non-transistor region NTR from dielectric breakdown due to plasma charging. This is because, near the boundary line BL between the transistor region TR and the non-transistor region NTR, not only the "electron shielding effect" but also the spatial inhomogeneity of the plasma caused by the difference between the arrangement density of the diffusion layer and the arrangement density of the through-vias TSVs becomes significant, thus generating a high electric field due to plasma charging. In other words, since the floating via FV, which is more prone to breakdown than the active via AV, is located closest to the boundary line BL, generating this high electric field at the boundary line BL, dielectric breakdown can be intentionally induced in the floating via FV, and therefore, dielectric breakdown at other active vias AV can be prevented. In this case, even if the floating via FV causes dielectric breakdown, the floating via FV is not connected to any circuit, thus preventing short-circuit faults and ensuring the reliability of the semiconductor device.

[0103] As can be seen from the first aspect, a floating via FV is provided near the boundary line BL between the transistor region TR and the non-transistor region NTR to intentionally induce dielectric breakdown. Due to the "electronic breakdown effect" and the spatial inhomogeneity of the plasma, the highest electric field is most easily generated at this boundary line BL, thereby protecting the active via AV, which may cause a short-circuit fault in the event of dielectric breakdown. Therefore, according to the first aspect, since intentional dielectric breakdown is induced in the floating via FV, which does not worry about short-circuit faults even in the event of dielectric breakdown, the circuit(s) formed in the semiconductor device can be protected from short-circuit faults caused by plasma charging. In other words, according to this aspect, the reliability of the semiconductor device can be improved.

[0104] (Second specific aspect)

[0105] Next, the second specific aspect will be described.

[0106] Figure 12 This is a schematic diagram illustrating the area near the boundary between the transistor region TR and the non-transistor region NTR formed on the base chip. Furthermore, Figure 13 It is along Figure 12 The cross-sectional view taken from line AA. Figure 12 In the plan view, the boundary line BL between the transistor region TR and the non-transistor region NTR includes a protrusion 300 protruding from the non-transistor region NTR toward the transistor region TR, and a floating via FV is formed in the protrusion 300.

[0107] According to the second specific aspect, this makes it possible to intentionally induce dielectric breakdown in floating vias (FVs). The reasons for this will be explained below.

[0108] Figure 14 This is a schematic diagram illustrating why floating vias FV arranged in the protruding portion 300 of the boundary line BL are prone to dielectric breakdown. Figure 14 In the process, the high electric field based on the spatial non-uniformity of plasma from Figure 14The directions indicated by the four arrows are applied to the floating vias FV arranged in the protrusion 300 of the boundary line BL. Therefore, the floating vias FV arranged in the protrusion 300 of the boundary line BL are more prone to dielectric breakdown than through-vias TSV arranged elsewhere. Thus, according to the second aspect, since the probability of dielectric breakdown of the floating vias FV arranged in the protrusion 300 of the boundary line BL is increased, active vias AV arranged elsewhere can be effectively protected from dielectric breakdown due to plasma charging. In this way, in the second aspect, the design of the shape of the boundary line BL creates multiple locations where a high electric field is effectively generated, and the arrangement of floating vias FV in these locations causes dielectric breakdown with a high probability. Therefore, according to the second aspect, circuits formed in semiconductor devices can be protected from short-circuit faults due to plasma charging, which improves the reliability of semiconductor devices.

[0109] (Third specific aspect)

[0110] The third specific aspect will then be described.

[0111] Figure 15 The diagram schematically illustrates the vicinity of a first boundary region between a first transistor region TR1 and a non-transistor region NTR formed on a base chip, and the vicinity of a second boundary region between a second transistor region TR2 and a non-transistor region NTR. Furthermore, Figure 16 It is along Figure 15 The cross-sectional view taken from line AA. Figure 15 In the plan view, the boundary line BL1 between the first transistor region TR1 and the non-transistor region NTR includes a protrusion 300 extending from the non-transistor region NTR toward the first transistor region TR1, and a floating via FV is formed in the protrusion 300. Meanwhile, the boundary line BL2 between the second transistor region TR2 and the non-transistor region NTR does not have a protrusion. Then, in addition to the floating via FV, active vias AV and AV2 are provided in the non-transistor region NTR. The active via AV is a through-hole connected to a circuit but not electrically connected to a protection circuit that protects the active via AV from plasma charging. Conversely, the active via AV2 is a through-hole electrically connected to a protection circuit that protects the active via AV2 from plasma charging. Here, the active via AV2 connected to the protection circuit is arranged at least closest to the boundary line BL2 between the second transistor region TR2 and the non-transistor region NTR. For example, as... Figure 16As shown, the active via AV2 is electrically connected to a protection circuit via a first layer wiring L1, a second layer wiring L2 and a third layer wiring L3. This protection circuit is included in an integrated circuit, which is formed in the transistor region TR1.

[0112] Based on the third specific aspect configured in this way, the following advantages can be obtained. That is, as... Figure 15 As shown, since the floating via FV is formed in the protruding portion 300 of the boundary line BL1 where a high electric field due to plasma charging is generated, dielectric breakdown can be intentionally induced at the floating via FV. Thus, the active via AV formed in the non-transistor region NTR can be protected from dielectric breakdown. Furthermore, in a third aspect, the active via AV2 connected to the protection circuit is arranged in the region near the boundary line BL2 where a high electric field due to plasma charging is generated, such that dielectric breakdown of the active via AV2 can be prevented even if a high electric field due to plasma charging is generated in the region near the boundary line BL2.

[0113] Specifically, in a third aspect, the through-via TSV connected to the protection circuit does not need to be located near boundary line BL1 and boundary line BL2, thereby reducing the number of protection circuits formed on the base chip. According to the third aspect, this allows the through-via TSV to be protected from dielectric breakdown due to plasma charging without increasing the chip size of the base chip (first advantage). Furthermore, in the third aspect, the protrusion 300 does not need to be located near boundary line BL1 and boundary line BL2, thereby achieving the following advantages: the occupied area of ​​the transistor regions (first transistor region TR1 and second transistor region TR2) can be ensured, and it is not necessary to provide more than necessary floating vias FV that are intentionally subject to dielectric breakdown (second advantage). Therefore, according to the third aspect, the aforementioned first and second advantages can be obtained by using an active via AV2 connected to the floating via FV and the protection circuit.

[0114] (Application Example)

[0115] In this embodiment, a floating via FV with a floating potential is provided to intentionally induce dielectric breakdown due to plasma charging. When dielectric breakdown occurs, the floating via FV causes conductivity with a substrate at a ground potential through the point where dielectric breakdown occurs, thus becoming a "damaged via".

[0116] Here, a "damaged via" itself does not cause a short-circuit fault in the integrated circuit, and therefore remains unchanged. However, for example, it is conceivable that the reliability of the semiconductor device starting from this "damaged via" may decrease due to long-term variations caused by factors such as temperature changes. Therefore, in this application example, a design for mitigating the potential reliability degradation caused by "damaged vias" will be described.

[0117] Figure 17 This is a diagram used to illustrate the design in the application example.

[0118] exist Figure 17 In this configuration, a damaged via (DV) formed due to dielectric breakdown in a floating via is connected to a redistribution (back surface routing) (RDL) that is provided with a ground potential. This results in the following: the dielectric breakdown portions present in the damaged via DV are repaired and covered by the redistribution RDL. Therefore, according to the application example, the dielectric breakdown portions present in the damaged via DV are not exposed, thereby reducing the likelihood of decreased reliability in the semiconductor device.

[0119] As described above, although the invention made by the inventors has been specifically described based on its embodiments, the invention is not limited to these embodiments, and needless to say, various modifications can be made without departing from its scope.

Claims

1. A semiconductor device, comprising: A first semiconductor chip has a first transistor region (TR; TR1) and a non-transistor region (NTR); as well as Multiple through-holes (TSVs) are formed in the non-transistor region (NTR). The plurality of through-holes (TSVs) include: Active vias (AV) are electrically connected to circuits; as well as Floating via (FV) has a floating potential. At least a portion of the through-holes located in the plan view closest to the first boundary line (BL; BL1) are floating vias (FV), the first boundary line (BL; BL1) being between the first transistor region (TR; TR1) and the non-transistor region (NTR).

2. The semiconductor device according to claim 1, wherein the arrangement density of the diffusion layer (201) formed in the first transistor region (TR; TR1) is higher than the arrangement density of the diffusion layer (202) formed in the non-transistor region (NTR).

3. The semiconductor device according to claim 1 or 2, wherein no through-hole is formed in the first transistor region (TR; TR1).

4. The semiconductor device according to any one of claims 1 to 3, further comprising a second semiconductor chip, wherein the second semiconductor chip is stacked on the first semiconductor chip. The active via (AV) is electrically connected to the second semiconductor chip.

5. The semiconductor device of claim 4, wherein the active via (AV) serves as a supply path for supplying power to a circuit formed on the second semiconductor chip.

6. The semiconductor device of claim 5, wherein no protection circuit is formed on the first semiconductor chip, the protection circuit being configured to suppress dielectric breakdown of the active via (AV) due to plasma charging.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first boundary line (BL; BL1) includes a protrusion (300) projecting in a plan view from the non-transistor region (NTR) toward the first transistor region (TR; TR1); and The floating via (FV) is formed in the protrusion (300).

8. The semiconductor device of claim 1, wherein the non-transistor region (NTR) is arranged in a plan view between the first transistor region (TR1) and the second transistor region (TR2).

9. The semiconductor device of claim 8, wherein the plurality of through-holes arranged in the plan view at the location closest to the second boundary line (BL2) are a plurality of active vias (AV2) consisting of active vias electrically connected to a protection circuit, the second boundary line (BL2) being between the second transistor region (TR2) and the non-transistor region (NTR).

10. The semiconductor device according to claim 1, further comprising a stacked structure (12), wherein a plurality of semiconductor chips are stacked in the stacked structure (12); The first semiconductor chip is a semiconductor device that is a semiconductor chip (13) arranged in the lowest layer of the plurality of semiconductor chips constituting the stacked structure (12).

11. A semiconductor device, comprising: A first semiconductor chip having a first transistor region (TR) and a non-transistor region (NTR); as well as Multiple through-holes are formed in the non-transistor region (NTR). The plurality of through holes include: Active vias (AV) are electrically connected to circuits; as well as A damaged via (DV) has a ground potential. At least a portion of the through-hole located closest to the first boundary line (BL) in the plan view is the damaged via (DV), the first boundary line (BL) being located between the first transistor region (TR) and the non-transistor region (NTR). The damaged via (DV) is a floating via with a floating potential, configured to cause dielectric breakdown of the floating via due to plasma charging, thereby suppressing dielectric breakdown of the active via (AV) due to plasma charging, and being dielectrically broken down, and The damaged via (DV) is formed on the back surface of the first semiconductor chip and connected to the back surface wiring (RDL) that provides a ground potential to it.

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