A method for controlling minority carrier lifetime

Abstract

The present application discloses a minority carrier lifetime control method, which is applied to a first silicon wafer, and the first silicon wafer belongs to an RC-IGBT, and the method includes: injecting a first ion into the first silicon wafer to obtain a P-type semiconductor; depositing a barrier layer on the P-type semiconductor; etching a first region from the barrier layer, and using the first region as a freewheeling diode region, and the first region does not have a barrier layer; injecting a second ion into the first region to form an N-type semiconductor on the first region; sputtering a heavy metal on the first region forming the N-type semiconductor; and using a first heat treatment method to heat treat the first silicon wafer including the first region sputtered with a heavy metal, so that the heavy metal forms a recombination center in the first silicon wafer. Since the recombination center can change the recombination mode of the minority carriers in the first silicon wafer, and change the recombination mode of the minority carriers from direct recombination to indirect recombination, the recombination time of the minority carriers can be effectively reduced, thereby reducing the reverse recovery time of the freewheeling diode.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a method for controlling minority carrier lifetime. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT), as a core semiconductor device for controlling strong current with weak current, is widely used in industries such as industry and home appliances.

[0003] IGBT generally needs a fast recovery diode (FRD) to be used with it, but using two chips at the same time increases the cost, so now IGBT is developing in the direction of integrating FRD, that is, integrating IGBT and FRD into one chip to make reverse conduction IGBT (RC-IGBT). If the diode area is made on a part of the area of ​​the traditional IGBT, the reverse recovery time of the diode will be very long, about 300ns, if the minority carrier lifetime control technology is not used, so it is necessary to control the minority carrier lifetime of the RC-IGBT to reduce the reverse recovery time of the FRD.

[0004] In the prior art, electron irradiation technology is usually used to control the minority carrier lifetime of the entire chip. However, controlling the minority carrier lifetime of the entire chip will affect the performance of the IGBT. Summary of the invention

[0005] In order to solve the problem that the performance of IGBT is affected by controlling the minority carrier lifetime of the entire chip using electron irradiation technology, the present application provides a minority carrier lifetime control method.

[0006] A minority carrier lifetime control method is applied to a first silicon wafer, wherein the first silicon wafer belongs to an RC-IGBT, and the method comprises:

[0007] Implanting first ions into the first silicon wafer to obtain a P-type semiconductor;

[0008] Depositing a barrier layer on the P-type semiconductor;

[0009] Etching a first region from the barrier layer and using the first region as a freewheeling diode region, wherein the first region does not have the barrier layer;

[0010] implanting second ions into the first region to form an N-type semiconductor on the first region;

[0011] Performing heavy metal sputtering on the first region forming the N-type semiconductor;

[0012] The first silicon wafer including the first region sputtered with the heavy metal is heat-treated by a first heat treatment method, so that the heavy metal forms a recombination center in the first silicon wafer.

[0013] Preferably, before the first ion is implanted into the first silicon wafer, the method further comprises:

[0014] thinning the first silicon wafer;

[0015] The step of implanting first ions into the first silicon wafer comprises:

[0016] The first ions are implanted into the thinned first silicon wafer.

[0017] Preferably, depositing a barrier layer on the P-type semiconductor comprises:

[0018] Silicon nitride is deposited on the P-type semiconductor.

[0019] Preferably, after the second ions are implanted into the first region to form an N-type semiconductor on the first region, the method further comprises:

[0020] Using a second heat treatment method to heat treat the first silicon wafer;

[0021] The step of performing heavy metal sputtering on the first region forming the N-type semiconductor comprises:

[0022] The heavy metal sputtering is performed on the first region where the N-type semiconductor is formed and heated by the second heat treatment method.

[0023] Preferably, after performing heavy metal sputtering on the first region forming the N-type semiconductor, the method further comprises:

[0024] Removing the heavy metals;

[0025] The step of heat treating the first silicon wafer including the first region sputtered with the heavy metal by a first heat treatment method so that the heavy metal forms a recombination center in the first silicon wafer comprises:

[0026] A first heat treatment method is used to heat treat the first silicon wafer including the first region where the heavy metal is removed, so that the heavy metal forms a recombination center in the first silicon wafer.

[0027] Preferably, after heat-treating the first silicon wafer including the first region where the heavy metal is removed by the first heat treatment method, the method further comprises:

[0028] Etching the barrier layer on the first silicon wafer except the first region;

[0029] A backside metal is deposited on a second silicon wafer, which is the first silicon wafer without the barrier layer.

[0030] Preferably, etching the first region from the barrier layer comprises:

[0031] The first region is etched from the barrier layer using a back mask.

[0032] Preferably, the first heat treatment method is used to heat treat the first area subjected to the heavy metal sputtering, including:

[0033] The first region where the heavy metal sputtering is performed is heat-treated by a thermal push junction method.

[0034] Preferably, the second heat treatment method is used to heat treat the first silicon wafer, including:

[0035] The first silicon wafer is heat treated by laser annealing.

[0036] Preferably, the removing of the heavy metals comprises:

[0037] The heavy metals are removed by acid corrosion.

[0038] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0039] The technical solution provided in the embodiment of the present application forms a P-type semiconductor on the first silicon wafer, forms an N-type semiconductor on the first region, and performs heavy metal sputtering and heat treatment on the first region, so that the heavy metal forms a recombination center in the first silicon wafer. Since the recombination center can change the recombination mode of minority carriers in the first silicon wafer, changing the recombination mode of minority carriers from direct recombination to indirect recombination, the recombination time of minority carriers can be effectively reduced, thereby reducing the reverse recovery time of the freewheeling diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1A flow chart of a minority carrier lifetime control method provided in an embodiment of the present application;

[0043] Figure 2 Another flow chart of a minority carrier lifetime control method provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of the RC-IGBT after thinning the first silicon wafer;

[0045] Figure 4 A schematic diagram of the structure of the RC-IGBT after the first ions are implanted into the thinned first silicon wafer;

[0046] Figure 5 It is a schematic diagram of the structure of RC-IGBT after silicon nitride is deposited on a P-type semiconductor;

[0047] Figure 6 A schematic diagram of the structure of the RC-IGBT after etching the first region from silicon nitride using a back mask;

[0048] Figure 7 is a top view of an RC-IGBT having a first region;

[0049] Figure 8 is a schematic diagram of the structure of the RC-IGBT after the second ions are implanted into the first region;

[0050] Fig. 9 is a schematic diagram of the structure of the RC-IGBT after heavy metal sputtering is performed on the first region;

[0051] Fig.10 This is the structural diagram of RC-IGBT after removing heavy metals;

[0052] Fig.11 A schematic diagram of the structure of the RC-IGBT after heat treatment of the first silicon wafer to remove heavy metals by using a thermal push junction method;

[0053] Fig.12 It is a schematic diagram of the structure of the RC-IGBT after etching silicon nitride on the first silicon wafer except the first region. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0055] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another similar entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0056] See also Figure 1 , Figure 1 A flowchart of a method for controlling the lifetime of minority carriers provided in an embodiment of the present application, the method comprising:

[0057] Step S101: implanting first ions into a first silicon wafer to obtain a P-type semiconductor.

[0058] The first silicon wafer is a form of the wafer in the process of manufacturing the RC-IGBT from the wafer. Therefore, the first silicon wafer belongs to the RC-IGBT.

[0059] Exemplarily, the first silicon wafer may be in the shape of a wafer after the front side process is completed.

[0060] Exemplarily, the process on the front side of the wafer may include the fabrication of an emitter and a gate of an IGBT and an anode of a freewheeling diode.

[0061] For example, the ions implanted into the first silicon wafer may be boron ions, the implantation dose may be 1e13, and the implantation energy may be 40 KeV. It should be noted that the above dose and energy values ​​are only examples, and the present application embodiment does not specifically limit this.

[0062] Exemplarily, P+ implantation may be performed on the first silicon wafer to implant boron ions to form a P-type semiconductor.

[0063] Step S102: depositing a barrier layer on the P-type semiconductor.

[0064] As an example, silicon nitride may be deposited on a P-type semiconductor.

[0065] The thickness of the deposited silicon nitride may be 3 um. The value of this thickness is only an example and is not specifically limited in the embodiments of the present application.

[0066] Step S103: etching a first region from the barrier layer and using the first region as a freewheeling diode region, wherein the first region does not have a barrier layer.

[0067] As an embodiment, a back mask may be used to etch a first region on the barrier layer, and the etched first region does not have the barrier layer.

[0068] Step S104 : implanting second ions into the first region to form an N-type semiconductor on the first region.

[0069] In practical applications, the second ions implanted into the first region may be phosphorus (P) ions, the implantation dose may be 2e15, and the implantation energy may be 120 KeV. It should be noted that the above dose and energy values ​​are only examples, and the present application embodiment does not specifically limit this.

[0070] Exemplarily, N+ implantation may be performed in the first region to form an N-type semiconductor.

[0071] Step S105 , performing heavy metal sputtering on the first region where the N-type semiconductor is formed.

[0072] In practical applications, the heavy metal sputtering may be implemented in the form of platinum (PT) sputtering or gold sputtering, etc., which is not limited in this embodiment.

[0073] It should be noted that, since there is a barrier layer outside the first region, the heavy metal sputtering is only performed locally in the first region, and the heavy metal cannot enter the silicon in other regions outside the first region due to the blocking of the barrier layer.

[0074] In practical applications, the thickness of the heavy metal sputtering may be 100 angstroms. The value of this thickness is only an example and is not specifically limited in the embodiments of the present application.

[0075] Step S106: using a first heat treatment method to heat treat the first silicon wafer including the first region sputtered with heavy metal, so that the heavy metal forms a recombination center in the first silicon wafer.

[0076] As an embodiment, the first heat treatment method is heat push junction, the temperature of heat push junction can be 400° C., and the time of heat push junction can be 50 minutes. It should be noted that the above temperature and time values ​​are only examples, and the embodiments of the present application do not specifically limit this.

[0077] In the embodiment of the present application, the diffusion of heavy metals in silicon forms a recombination center, which can effectively reduce the recombination time of minority carriers and thus reduce the reverse recovery time of the freewheeling diode.

[0078] The technical solution provided in the embodiment of the present application forms a P-type semiconductor on the first silicon wafer, forms an N-type semiconductor on the first region, performs heavy metal sputtering on the first region, and performs heat treatment on the first silicon wafer including the first region sputtered with heavy metal, so that the heavy metal forms a recombination center in the first silicon wafer. Since the recombination center can change the recombination mode of minority carriers in the first silicon wafer, changing the recombination mode of minority carriers from direct recombination to indirect recombination, the recombination time of minority carriers can be effectively reduced, thereby reducing the reverse recovery time of the freewheeling diode.

[0079] In other embodiments of the present application, before the first ions are implanted into the first silicon wafer, the first silicon wafer may be thinned. By thinning the first silicon wafer, Vcesat of the IGBT may be reduced, where Vcesat is the voltage between the collector and the emitter at saturation.

[0080] For example, the first silicon wafer may be thinned to 70 μm. The value of the thinned thickness is only an example and is not specifically limited in the embodiments of the present application.

[0081] In other embodiments of the present application, after the second ions are implanted into the first region to form an N-type semiconductor on the first region, the first silicon wafer may be heat-treated by a second treatment method.

[0082] Exemplarily, the second heat treatment method may be laser annealing, and the first ions and the second ions may be activated by laser annealing.

[0083] In other embodiments of the present application, after heavy metal sputtering is performed on the first region forming the N-type semiconductor, the heavy metal may be removed.

[0084] After sputtering is complete, the amount of heavy metals remaining in the silicon is sufficient so that they can be removed immediately after sputtering is completed.

[0085] In practical applications, aqua regia can be used to remove heavy metals by acid corrosion.

[0086] In other embodiments of the present application, after heat treating the first silicon wafer including the first area sputtered with heavy metal using the first processing method, the barrier layer on the first silicon wafer except the first area can be etched, and back metal can be deposited on the second silicon wafer, wherein the second silicon wafer is the first silicon wafer without the barrier layer.

[0087] In practical applications, the barrier layer except the first region on the first silicon wafer may be etched by hot phosphoric acid etching.

[0088] In practical applications, when depositing the back metal, aluminum, titanium, nickel and silver can be deposited layer by layer in the order from inside to outside.

[0089] See also Figure 2 , Figure 2 Another schematic flow chart of a minority carrier lifetime control method provided in an embodiment of the present application, the method comprising:

[0090] Step S201, thinning the first silicon wafer.

[0091] The first silicon wafer is a form of the wafer in the process of manufacturing the RC-IGBT from the wafer. Therefore, the first silicon wafer belongs to the RC-IGBT.

[0092] Exemplarily, the first silicon wafer may be in the shape of a wafer after the front side process is completed.

[0093] Exemplarily, the process on the front side of the wafer may include the fabrication of an emitter and a gate of an IGBT and an anode of a freewheeling diode.

[0094] Exemplarily, the first silicon wafer may be thinned to 70 μm.

[0095] in, Figure 3 Schematic diagram of the structure of the RC-IGBT after thinning the first silicon wafer.

[0096] Step S202: implanting first ions into the thinned first silicon wafer to obtain a P-type semiconductor.

[0097] For example, the ions implanted into the first silicon wafer may be boron ions, the implantation dose may be 1e13, and the implantation energy may be 40 KeV.

[0098] Exemplarily, P+ implantation may be performed on the first silicon wafer to implant boron ions to form a P-type semiconductor.

[0099] Figure 4 It is a schematic diagram of the structure of the RC-IGBT after the first ions are implanted into the thinned first silicon wafer.

[0100] Step S203: depositing silicon nitride on the P-type semiconductor.

[0101] The thickness of the deposited silicon nitride may be 3 um.

[0102] Figure 5 Schematic diagram of the structure of RC-IGBT after silicon nitride is deposited on a P-type semiconductor.

[0103] Step S204: using a back mask to etch a first region from the silicon nitride, and using the first region as a freewheeling diode region, the first region does not have silicon nitride.

[0104] Figure 6 It is a schematic diagram of the structure of the RC-IGBT after etching the first region from silicon nitride using a back mask.

[0105] Figure 7 FIG. 4 is a top view of an RC-IGBT having a first region.

[0106] It should be noted that Figure 7 The position of the first area in FIG. 1 is only a schematic diagram. In actual applications, the position of the first area can be set arbitrarily.

[0107] Step S205 , implanting second ions into the first region to form an N-type semiconductor on the first region.

[0108] In practical applications, the second ions implanted into the first region may be phosphorus (P) ions, the implantation dose may be 2e15, and the implantation energy may be 120 KeV.

[0109] Exemplarily, N+ implantation may be performed in the first region to form an N-type semiconductor.

[0110] Figure 8 It is a schematic diagram of the structure of the RC-IGBT after the second ions are implanted into the first region.

[0111] Step S206: heat-treating the first silicon wafer by laser annealing.

[0112] Step S207 , performing the heavy metal sputtering on the first region formed with the N-type semiconductor and heated by laser annealing.

[0113] In practical applications, the heavy metal sputtering may be implemented in the form of platinum (PT) sputtering or gold sputtering, etc., which is not limited in this embodiment.

[0114] It should be noted that, since there is a barrier layer outside the first region, the heavy metal sputtering is only performed locally in the first region, and the heavy metal cannot enter the silicon in other regions outside the first region due to the blocking of the barrier layer.

[0115] In practical applications, the thickness of heavy metal sputtering can be 100 angstroms.

[0116] Fig. 9 Schematic diagram of the structure of the RC-IGBT after heavy metal sputtering is performed on the first region.

[0117] Step S208: removing heavy metals by acid corrosion.

[0118] In practical applications, aqua regia can be used to remove heavy metals by acid corrosion.

[0119] Fig.10 This is a schematic diagram of the structure of the RC-IGBT after removing heavy metals.

[0120] Step S209: heat-treating the first silicon wafer from which the heavy metals have been removed by means of thermal push junction, so that the heavy metals form a recombination center in the first silicon wafer.

[0121] Fig.11 The schematic diagram of the structure of the RC-IGBT is shown after the first silicon wafer is heat-treated to remove heavy metals by means of thermally pushing the junction.

[0122] Step S210, etching silicon nitride on the first silicon wafer except the first region.

[0123] Fig.12 It is a schematic diagram of the structure of the RC-IGBT after etching silicon nitride on the first silicon wafer except the first region.

[0124] In practical applications, hot phosphoric acid etching may be used to etch the silicon nitride on the first silicon wafer except the first region.

[0125] Step S211, depositing a back metal on the second silicon wafer, where the second silicon wafer is the first silicon wafer without a barrier layer.

[0126] In practical applications, when depositing the back metal, aluminum, titanium, nickel and silver can be deposited layer by layer in the order from inside to outside.

[0127] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

[0128] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A method for controlling minority carrier lifetime, characterized in that: Applied to a first silicon wafer, the first silicon wafer being an RC-IGBT, the method comprises: Injecting first ions into the first silicon wafer to obtain a P-type semiconductor, wherein the first silicon wafer is a form of the wafer in the process of manufacturing the RC-IGBT from the wafer; Depositing a barrier layer on the P-type semiconductor; Etching a first region from the barrier layer and using the first region as a freewheeling diode region, wherein the first region does not have the barrier layer; implanting second ions into the first region to form an N-type semiconductor on the first region; Performing heavy metal sputtering on the first region forming the N-type semiconductor to remove the heavy metal; A first heat treatment method is used to heat treat the first silicon wafer including the first region sputtered with the heavy metal so that the heavy metal forms a recombination center in the first silicon wafer, including: a heat push junction method is used to heat treat the first silicon wafer including the first region where the heavy metal is removed so that the heavy metal forms a recombination center in the first silicon wafer.

2. The method according to claim 1, characterized in that Before the first ion is implanted into the first silicon wafer, the method further comprises: thinning the first silicon wafer; The step of implanting first ions into the first silicon wafer comprises: The first ions are implanted into the thinned first silicon wafer.

3. The method according to claim 2, characterized in that The step of depositing a barrier layer on the P-type semiconductor comprises: Silicon nitride is deposited on the P-type semiconductor.

4. The method according to claim 3, characterized in that After the second ions are implanted into the first region to form an N-type semiconductor on the first region, the method further includes: Using a second heat treatment method to heat treat the first silicon wafer; The step of performing heavy metal sputtering on the first region forming the N-type semiconductor comprises: The heavy metal sputtering is performed on the first region where the N-type semiconductor is formed and heated by the second heat treatment method.

5. The method according to claim 1, characterized in that After the first silicon wafer including the first region where the heavy metal is removed is subjected to heat treatment by the first heat treatment method, the method further comprises: Etching the barrier layer on the first silicon wafer except the first region; A backside metal is deposited on a second silicon wafer, which is the first silicon wafer without the barrier layer.

6. The method according to claim 5, characterized in that The etching of the first region from the barrier layer comprises: The first region is etched from the barrier layer using a back mask.

7. The method according to claim 6, characterized in that The step of heat treating the first region subjected to the heavy metal sputtering by using a first heat treatment method comprises: The first region where the heavy metal sputtering is performed is heat-treated by a thermal push junction method.

8. The method according to claim 4, characterized in that The step of heat treating the first silicon wafer by using a second heat treatment method includes: The first silicon wafer is heat treated by laser annealing.

9. The method according to claim 1, characterized in that: The removal of the heavy metals comprises: The heavy metals are removed by acid corrosion.

Images